| 1 | /* |
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| 2 | #************************************************************************ |
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| 3 | #* Coprocessor 0 Index Register Bits |
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| 4 | #************************************************************************ |
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| 5 | # No known functionality (32-bit register) |
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| 6 | */ |
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| 7 | |
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| 8 | /* |
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| 9 | #************************************************************************ |
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| 10 | #* Coprocessor 0 Entry Register Bits |
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| 11 | #************************************************************************ |
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| 12 | # No known functionality (32-bit register) |
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| 13 | */ |
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| 14 | |
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| 15 | /* |
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| 16 | #************************************************************************ |
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| 17 | #* Coprocessor 0 BvAddr Register Bits |
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| 18 | #************************************************************************ |
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| 19 | # Contains offending address (32-bit register) |
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| 20 | */ |
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| 21 | |
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| 22 | /* |
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| 23 | #************************************************************************ |
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| 24 | #* Coprocessor 0 Status Register Bits |
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| 25 | #************************************************************************ |
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| 26 | |
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| 27 | # Notes: COP2 is forced, then allowed to be overwritten |
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| 28 | # writing a '1' to bit 20 force bit 20 to '0' but no effect |
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| 29 | */ |
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| 30 | #ifndef _BCMMIPS_H |
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| 31 | #define _BCMMIPS_H |
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| 32 | |
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| 33 | #define BCM_CP0_SR_COP3 (1<<31) |
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| 34 | #define BCM_CP0_SR_COP2 (1<<30) |
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| 35 | #define BCM_CP0_SR_COP1 (1<<29) |
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| 36 | #define BCM_CP0_SR_COP0 (1<<28) |
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| 37 | #define BCM_CP0_SR_IST (1<<23) |
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| 38 | #define BCM_CP0_SR_BEV (1<<22) |
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| 39 | #define BCM_CP0_SR_SWC (1<<17) |
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| 40 | #define BCM_CP0_SR_ISC (1<<16) |
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| 41 | #define BCM_CP0_SR_KRNL (1<<1) |
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| 42 | #define BCM_CP0_SR_IE (1<<0) |
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| 43 | #define BCM_CP0_SR_IM5 (1<<15) |
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| 44 | #define BCM_CP0_SR_IM4 (1<<14) |
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| 45 | #define BCM_CP0_SR_IM3 (1<<13) |
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| 46 | #define BCM_CP0_SR_IM2 (1<<12) |
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| 47 | #define BCM_CP0_SR_IM1 (1<<11) |
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| 48 | #define BCM_CP0_SR_IM0 (1<<10) |
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| 49 | #define BCM_CP0_SR_SWM1 (1<<9) |
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| 50 | #define BCM_CP0_SR_SWM0 (1<<8) |
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| 51 | |
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| 52 | /* |
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| 53 | #************************************************************************ |
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| 54 | #* Coprocessor 0 Cause Register Bits |
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| 55 | #************************************************************************ |
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| 56 | # Notes: 5:2 hold exception cause |
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| 57 | # Notes: 29:28 hold Co-processor Number reference by Coproc unusable excptn |
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| 58 | # Notes: 7:6, 1:0, 27:15, 30 ***UNUSED*** |
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| 59 | */ |
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| 60 | #define BCM_CP0_CR_BD (1<<31) |
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| 61 | #define BCM_CP0_CR_EXTIRQ4 (1<<14) |
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| 62 | #define BCM_CP0_CR_EXTIRQ3 (1<<13) |
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| 63 | #define BCM_CP0_CR_EXTIRQ2 (1<<12) |
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| 64 | #define BCM_CP0_CR_EXTIRQ1 (1<<11) |
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| 65 | #define BCM_CP0_CR_EXTIRQ0 (1<<10) |
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| 66 | #define BCM_CP0_CR_SW1 (1<<9) |
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| 67 | #define BCM_CP0_CR_SW0 (1<<8) |
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| 68 | #define BCM_CP0_CR_EXC_CAUSE_MASK (0xf << 2) |
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| 69 | #define BCM_CP0_CR_EXC_COP_MASK (0x3 << 28) |
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| 70 | |
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| 71 | /* |
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| 72 | #************************************************************************ |
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| 73 | #* Coprocessor 0 EPC Register Bits |
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| 74 | #************************************************************************ |
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| 75 | # Contains PC or PC-4 for resuming program after exception (32-bit register) |
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| 76 | */ |
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| 77 | |
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| 78 | /* |
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| 79 | #************************************************************************ |
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| 80 | #* Coprocessor 0 PrID Register Bits |
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| 81 | #************************************************************************ |
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| 82 | # Notes: Company Options=0 |
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| 83 | # Company ID=0 |
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| 84 | # Processor ID = 0xa |
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| 85 | # Revision = 0xa |
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| 86 | */ |
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| 87 | |
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| 88 | /* |
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| 89 | #************************************************************************ |
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| 90 | #* Coprocessor 0 Debug Register Bits |
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| 91 | #************************************************************************ |
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| 92 | # Notes: Bits [29:13],[11], [9], [6] read as zero |
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| 93 | */ |
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| 94 | #define BCM_CP0_DBG_BRDLY (0x1 << 31) |
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| 95 | #define BCM_CP0_DBG_DBGMD (0x1 << 30) |
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| 96 | #define BCM_CP0_DBG_EXSTAT (0x1 << 12) |
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| 97 | #define BCM_CP0_DBG_BUS_ERR (0x1 << 10) |
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| 98 | #define BCM_CP0_DBG_1STEP (0x1 << 8) |
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| 99 | #define BCM_CP0_DBG_JTGRST (0x1 << 7) |
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| 100 | #define BCM_CP0_DBG_PBUSBRK (0x1 << 5) |
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| 101 | #define BCM_CP0_DBG_IADBRK (0x1 << 4) |
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| 102 | #define BCM_CP0_DBG_DABRKST (0x1 << 3) |
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| 103 | #define BCM_CP0_DBG_DABRKLD (0x1 << 2) |
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| 104 | #define BCM_CP0_DBG_SDBBPEX (0x1 << 1) |
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| 105 | #define BCM_CP0_DBG_SSEX (0x1 << 0) |
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| 106 | |
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| 107 | /* |
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| 108 | #************************************************************************ |
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| 109 | #* Coprocessor 0 DBEXCPC Register Bits |
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| 110 | #************************************************************************ |
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| 111 | # Debug Exception Program Counter (32-bits) |
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| 112 | */ |
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| 113 | |
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| 114 | /* |
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| 115 | #************************************************************************ |
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| 116 | #* Coprocessor 0 PROCCFG Register Bits |
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| 117 | #************************************************************************ |
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| 118 | # Select 0 |
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| 119 | */ |
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| 120 | #define BCM_CP0_CFG1EN (0x1 << 31) |
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| 121 | #define BCM_CP0_BE (0x1 << 15) |
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| 122 | #define BCM_CP0_MIPS32MSK (0x3 << 13) /* 0 = MIPS32 Arch */ |
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| 123 | #define BCM_CP0_ARMSK (0x7 << 10) /* Architecture Rev 0 */ |
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| 124 | #define BCM_CP0_MMUMSK (0x7 << 7) /* 0 no MMU */ |
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| 125 | #define BCM_CP0_K0Coherency (0x7 << 0) /* 0 no Coherency */ |
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| 126 | #define BCM_CP0_K0Uncached (0x2 << 0) /* 2 = Uncached */ |
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| 127 | #define BCM_CP0_K0WriteThrough (0x1 << 0) /* 0 = Cached, Dcache write thru */ |
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| 128 | #define BCM_CP0_K0Writeback (0x3) /* 0 = Cached, Dcache write back */ |
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| 129 | |
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| 130 | /* |
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| 131 | # Select 1 |
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| 132 | # Bit 31: unused |
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| 133 | # Bits 30:25 MMU Size (Num TLB entries-1) |
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| 134 | # Bits 24:22 ICache sets/way (2^n * 64) |
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| 135 | # Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache |
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| 136 | # Bits 18:16 ICache Associativity (n+1) way |
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| 137 | # Bits 15:13 DCache sets/way (2^n * 64) |
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| 138 | # Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache |
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| 139 | # Bits 9:7 DCache Associativity (n+1) way |
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| 140 | # Bits 6:4 unused |
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| 141 | # Bit 3: 1=At least 1 watch register |
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| 142 | # Bit 2: 1=MIPS16 code compression implemented |
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| 143 | # Bit 1: 1=EJTAG implemented |
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| 144 | # Bit 0: 1=FPU implemented |
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| 145 | */ |
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| 146 | #define BCM_CP0_CFG_ISMSK (0x7 << 22) |
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| 147 | #define BCM_CP0_CFG_ISSHF 22 |
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| 148 | #define BCM_CP0_CFG_ILMSK (0x7 << 19) |
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| 149 | #define BCM_CP0_CFG_ILSHF 19 |
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| 150 | #define BCM_CP0_CFG_IAMSK (0x7 << 16) |
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| 151 | #define BCM_CP0_CFG_IASHF 16 |
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| 152 | #define BCM_CP0_CFG_DSMSK (0x7 << 13) |
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| 153 | #define BCM_CP0_CFG_DSSHF 13 |
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| 154 | #define BCM_CP0_CFG_DLMSK (0x7 << 10) |
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| 155 | #define BCM_CP0_CFG_DLSHF 10 |
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| 156 | #define BCM_CP0_CFG_DAMSK (0x7 << 7) |
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| 157 | #define BCM_CP0_CFG_DASHF 7 |
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| 158 | |
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| 159 | /* |
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| 160 | #************************************************************************ |
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| 161 | #* Coprocessor 0 Config Register Bits |
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| 162 | #************************************************************************ |
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| 163 | */ |
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| 164 | #define BCM_CP0_CFG_ICSHEN (0x1 << 31) |
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| 165 | #define BCM_CP0_CFG_DCSHEN (0x1 << 30) |
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| 166 | |
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| 167 | |
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| 168 | /* |
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| 169 | #************************************************************************ |
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| 170 | #* KSEG Mapping Definitions and Macro's |
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| 171 | #************************************************************************ |
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| 172 | */ |
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| 173 | #define BCM_K0BASE 0x80000000 |
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| 174 | #define BCM_K0SIZE 0x20000000 |
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| 175 | #define BCM_K1BASE 0xa0000000 |
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| 176 | #define BCM_K1SIZE 0x20000000 |
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| 177 | #define BCM_K2BASE 0xc0000000 |
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| 178 | |
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| 179 | #define BCM_PHYS_TO_K0(x) ((x) | 0x80000000) |
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| 180 | #define BCM_PHYS_TO_K1(x) ((x) | 0xa0000000) |
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| 181 | #define BCM_K0_TO_PHYS(x) ((x) & 0x1fffffff) |
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| 182 | #define BCM_K1_TO_PHYS(x) (BCM_K0_TO_PHYS(x)) |
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| 183 | #define BCM_K0_TO_K1(x) ((x) | 0x20000000) |
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| 184 | #define BCM_K1_TO_K0(x) ((x) & 0xdfffffff) |
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| 185 | |
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| 186 | #endif |
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