| 1 | /***********************************************************************/ |
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| 2 | /* */ |
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| 3 | /* MODULE: bcmtimer.h */ |
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| 4 | /* DATE: 96/12/19 */ |
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| 5 | /* PURPOSE: Definitions for Timer block */ |
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| 6 | /* */ |
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| 7 | /***********************************************************************/ |
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| 8 | #ifndef BCMTIMER_H |
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| 9 | #define BCMTIMER_H |
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| 10 | |
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| 11 | #include "bcmmips.h" |
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| 12 | #include "bchp_common.h" |
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| 13 | #include "bchp_timer.h" |
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| 14 | |
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| 15 | |
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| 16 | #if !defined _ASMLANGUAGE |
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| 17 | #if __cplusplus |
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| 18 | extern "C" { |
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| 19 | #endif |
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| 20 | #endif |
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| 21 | |
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| 22 | #define TIMR_ADR_BASE BCM_PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_TIMER_TIMER_IS) |
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| 23 | |
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| 24 | #define TIMER_TIMER_IS 0x00 |
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| 25 | #define TIMER_TIMER_IE0 0x04 |
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| 26 | #define TIMER_TIMER0_CTRL 0x08 |
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| 27 | #define TIMER_TIMER1_CTRL 0x0c |
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| 28 | #define TIMER_TIMER2_CTRL 0x10 |
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| 29 | #define TIMER_TIMER3_CTRL 0x14 |
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| 30 | #define TIMER_TIMER0_STAT 0x18 |
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| 31 | #define TIMER_TIMER1_STAT 0x1c |
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| 32 | #define TIMER_TIMER2_STAT 0x20 |
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| 33 | #define TIMER_TIMER3_STAT 0x24 |
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| 34 | #define TIMER_WDTIMEOUT 0x28 |
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| 35 | #define TIMER_WDCMD 0x2c |
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| 36 | #define TIMER_WDCHIPRST_CNT 0x30 |
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| 37 | #define TIMER_WDCRS 0x34 |
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| 38 | #define TIMER_TIMER_IE1 0x38 |
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| 39 | |
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| 40 | /* Timer interrupt register */ |
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| 41 | #define TIMER_INT_TIMER0 0x01 |
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| 42 | #define TIMER_INT_TIMER1 0x02 |
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| 43 | #define TIMER_INT_TIMER2 0x04 |
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| 44 | #define TIMER_INT_TIMER3 0x08 |
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| 45 | #define TIMER_INT_WDINT 0x10 |
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| 46 | |
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| 47 | /* Timer control register */ |
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| 48 | #define TIMER_CTL_ENA 0x80000000 |
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| 49 | #define TIMER_CTL_MODE 0x40000000 |
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| 50 | #define TIMER_CTL_TIMEOUT_MASK 0x3FFFFFFF |
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| 51 | |
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| 52 | /* Timer status register */ |
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| 53 | #define TIMER_STS_COUNTER_MASK 0x3FFFFFFF |
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| 54 | |
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| 55 | #if !defined _ASMLANGUAGE |
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| 56 | |
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| 57 | |
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| 58 | |
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| 59 | typedef struct Timer { |
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| 60 | unsigned long TimerInts; /* 0x00 */ |
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| 61 | #define TIMER0 0x01 |
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| 62 | #define TIMER1 0x02 |
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| 63 | #define TIMER2 0x04 |
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| 64 | #define TIMER3 0x08 |
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| 65 | #define WATCHDOG 0x10 |
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| 66 | unsigned long TimerMask; /* 0x04 */ |
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| 67 | #define TIMER0EN 0x01 |
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| 68 | #define TIMER1EN 0x02 |
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| 69 | #define TIMER2EN 0x04 |
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| 70 | #define TIMER3EN 0x08 |
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| 71 | unsigned long TimerCtl0; /* 0x08 */ |
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| 72 | unsigned long TimerCtl1; /* 0x0c */ |
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| 73 | unsigned long TimerCtl2; /* 0x10 */ |
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| 74 | unsigned long TimerCtl3; /* 0x14 */ |
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| 75 | #define TIMERENABLE 0x80000000 |
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| 76 | #define RSTCNTCLR 0x40000000 |
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| 77 | unsigned long TimerCnt0; /* 0x18 */ |
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| 78 | unsigned long TimerCnt1; /* 0x1c */ |
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| 79 | unsigned long TimerCnt2; /* 0x20 */ |
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| 80 | unsigned long TimerCnt3; /* 0x24 */ |
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| 81 | unsigned long WatchDogDefCount; /* 0x28 */ |
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| 82 | |
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| 83 | /* Write 0xff00 0x00ff to Start timer |
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| 84 | * Write 0xee00 0x00ee to Stop and re-load default count |
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| 85 | * Read from this register returns current watch dog count |
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| 86 | */ |
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| 87 | unsigned long WatchDogCtl; /* 0x2c */ |
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| 88 | |
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| 89 | /* Number of 40-MHz ticks for WD Reset pulse to last */ |
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| 90 | unsigned long WDResetCount; /* 0x30 */ |
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| 91 | unsigned long WDResetStatus; /* 0x34 */ |
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| 92 | } Timer; |
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| 93 | |
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| 94 | #define TIMER ((volatile Timer * const)(TIMR_ADR_BASE)) |
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| 95 | |
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| 96 | |
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| 97 | |
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| 98 | |
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| 99 | #if __cplusplus |
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| 100 | } |
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| 101 | #endif |
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| 102 | #endif |
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| 103 | |
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| 104 | #endif |
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