/***************************************************************************
*     Copyright (c) 2003-2009, Broadcom Corporation
*     All Rights Reserved
*     Confidential Property of Broadcom Corporation
*
*  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
*  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
*  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
*
* $brcm_Workfile: bcmtm.c $
* $brcm_Revision: Hydra_Software_Devel/1 $
* $brcm_Date: 9/30/09 5:19p $
*
* Module Description:
*
* Revision History:
*
* $brcm_Log: /rockford/bsp/bcm97550/common/bcmtm.c $
* 
* Hydra_Software_Devel/1   9/30/09 5:19p farshidf
* SW7550-38: mini non-os code
* 
* Bsp_Software_Devel/4   8/25/08 5:11p farshidf
* PR41450: add teh IR
* 
* Bsp_Software_Devel/3   8/25/08 3:27p farshidf
* PR41450: correct the include
* 
* Bsp_Software_Devel/2   5/23/08 5:10p farshidf
* PR41450: fix compile issue
* 
* Bsp_Software_Devel/1   5/23/08 5:05p farshidf
* PR41450: add for Non_os
* 
* 
***************************************************************************/
#include "bstd.h"
#include "breg_mem.h"
#include "bchp_sun_top_ctrl.h"

#ifndef BCM_REF_BOARD
#define BCM_REF_BOARD 1
#endif

/****************************************************************
* bcmConfigureTm
*
* INPUTS:   hReg7401 - 7401 register handle
*           
* OUTPUTS:  
* RETURNS:  none
* FUNCTION: This function configures the BCM7401 pin muxing for
*           BCM97401 reference board.
*           On the 7401, various GPIO pins are MUXed together with 
*           other pins, e.g. I2C, SPI, etc.  In order to make these pins 
*           function as I2C, SPI, etc. instead of GPIO, you have to write 
*           to the SUNDRY top control register.
*
****************************************************************/
void bcmConfigureTm (BREG_Handle hReg7401)
{
    uint32_t        lval;



    /* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4

     * GPIO15  : UART_RXD_0(2)
     * GPIO16  : UART_TXD_0(2)
         */
    lval = BREG_Read32 (hReg7401, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4);
    lval &= ~(
            BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_4, gpio_15) |
            BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_4, gpio_16)
            );
    lval |= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_4, gpio_16, 2) | 
            BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_4, gpio_15, 2);
    BREG_Write32 (hReg7401, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, lval);

  

    /* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6

     */
    lval = BREG_Read32 (hReg7401, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6);
    lval &= ~(
            BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_31)  |
            BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_30)  
            );
    lval |= 
            BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_31, 2) | 
            BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_30, 2) ;
    BREG_Write32 (hReg7401, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, lval);;





 
}