/*************************************************************************** * Copyright (c) 2003-2009, Broadcom Corporation * All Rights Reserved * Confidential Property of Broadcom Corporation * * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. * * $brcm_Workfile: bcmtm.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 9/30/09 5:19p $ * * Module Description: * * Revision History: * * $brcm_Log: /rockford/bsp/bcm97550/common/bcmtm.h $ * * Hydra_Software_Devel/1 9/30/09 5:19p farshidf * SW7550-38: mini non-os code * * Hydra_Software_Devel/1 3/24/05 4:40p dlwin * PR 14606: Merge to main development branch. * * Hydra_Software_Devel/6 5/27/04 5:13p brianlee * PR11238: Enable LED/KPD pins for 7038 B0. * * Hydra_Software_Devel/5 5/25/04 6:39p brianlee * PR11214: Merge from B0 branch. * * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:06p brianlee * PR10857: Version for 7038 B0. * * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:03p brianlee * PR10857: Version for 7038 B0. * * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:02p brianlee * PR10857: Version for 7038 B0. * * Hydra_Software_Devel/4 2/18/04 11:21a brianlee * PR9791: Enable IR2 instead of PWM1. * * Hydra_Software_Devel/3 1/15/04 11:12a brianlee * PR8921: Enable PKT3 input pins. * * Hydra_Software_Devel/2 10/31/03 10:29a brianlee * Enable all external interrupt inputs. * * Hydra_Software_Devel/1 10/8/03 4:38p brianlee * Initial version. * * ***************************************************************************/ #ifndef BCMTM_H #define BCMTM_H #ifdef __cplusplus extern "C" { #endif /**************************************************************************** * BSC ***************************************************************************/ #define BSC0_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_03_SHIFT) #define BSC0_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_02_SHIFT) #define BSC1_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_05_SHIFT) #define BSC1_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_04_SHIFT) #define BSC2_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_07_SHIFT) #define BSC2_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_06_SHIFT) #define BSC3_SDA (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_01_SHIFT) #define BSC3_SCL (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_00_SHIFT) #define BSC0_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_03_MASK #define BSC0_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_02_MASK #define BSC1_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_05_MASK #define BSC1_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_04_MASK #define BSC2_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_07_MASK #define BSC2_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_06_MASK #define BSC3_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_01_MASK #define BSC3_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_00_MASK /**************************************************************************** * SPI ***************************************************************************/ #define SPI_SS1 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_SHIFT) #define SPI_SS0 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_39_SHIFT) #define SPI_MISO (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_38_SHIFT) #define SPI_MOSI (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_SHIFT) #define SPI_CLK (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_SHIFT) #define SPI_SS1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_MASK #define SPI_SS0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_39_MASK #define SPI_MISO_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_38_MASK #define SPI_MOSI_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_MASK #define SPI_CLK_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_MASK /**************************************************************************** * UART ***************************************************************************/ #define UARTB_TX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_SHIFT) #define UARTB_RX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_SHIFT) #define UARTA_TX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_SHIFT) #define UARTA_RX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_32_SHIFT) #define UARTB_TX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_MASK #define UARTB_RX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_MASK #define UARTA_TX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_MASK #define UARTA_RX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_32_MASK /**************************************************************************** * PWM ***************************************************************************/ #define PWM_1 (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SHIFT) #define PWM_0 (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_05_SHIFT) #define PWM_1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_MASK #define PWM_0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_05_MASK /**************************************************************************** * IR ***************************************************************************/ #define IR2_IN (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SHIFT) #define IR3_IN (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_SHIFT) #define IR2_IN_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_MASK #define IR3_IN_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_MASK /**************************************************************************** * PKT3 ***************************************************************************/ #define PKT3_CLK (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_SHIFT) #define PKT3_DATA (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_SHIFT) #define PKT3_SYNC (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_SHIFT) #define PKT3_CLK_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_MASK #define PKT3_DATA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_MASK #define PKT3_SYNC_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_MASK /**************************************************************************** * LED/Keypad ***************************************************************************/ #define LDK_LS_3 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_SHIFT) #define LDK_LS_2 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_SHIFT) #define LDK_LS_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_SHIFT) #define LDK_LS_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_SHIFT) #define LDK_LD_7 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_SHIFT) #define LDK_LD_6 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_SHIFT) #define LDK_LD_5 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_SHIFT) #define LDK_KD_2 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_55_SHIFT) #define LDK_KD_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_54_SHIFT) #define LDK_KD_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_53_SHIFT) #define LDK_LS_4 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_SHIFT) #define LDK_LD_4 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_SHIFT) #define LDK_LD_3 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_SHIFT) #define LDK_LD_2 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_48_SHIFT) #define LDK_LD_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_47_SHIFT) #define LDK_LD_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_46_SHIFT) #define LDK_KD_3 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_56_SHIFT) #define LDK_MUX_7_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_MASK ) #define LDK_MUX_8_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_MASK ) #define LDK_MUX_9_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_55_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_54_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_53_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_48_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_47_MASK | \ BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_46_MASK ) #define LDK_MUX_10_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_56_MASK) /**************************************************************************** * MISC. ***************************************************************************/ #define EXT_LONG_RST (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_SHIFT) #define EXT_LONG_RST_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_MASK #define EXT_IRQB_0 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_SHIFT) #define EXT_IRQB_1 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_SHIFT) #define EXT_IRQB_2 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_SHIFT) #define EXT_IRQB_3 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_SHIFT) #define EXT_IRQB_4 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_SHIFT) #define EXT_IRQB_5 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_SHIFT) #define EXT_IRQB_6 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_SHIFT) #define EXT_IRQB_0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_MASK #define EXT_IRQB_1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_MASK #define EXT_IRQB_2_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_MASK #define EXT_IRQB_3_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_MASK #define EXT_IRQB_4_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_MASK #define EXT_IRQB_5_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_MASK #define EXT_IRQB_6_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_MASK /**************************************************************************** * Function prototypes ****************************************************************************/ void bcmConfigureTm (BREG_Handle hReg7038); #ifdef __cplusplus } #endif #endif