source: svn/newcon3bcm2_21bu/rockford/bsp/bcm97552/common/boardmap.h @ 22

Last change on this file since 22 was 22, checked in by phkim, 11 years ago
  1. phkim
  2. newcon3sk 를 kctv 로 브랜치 함
  • Property svn:executable set to *
File size: 5.2 KB
Line 
1#ifndef BOARDMAP_H
2#define BOARDMAP_H
3
4/*****************************************************************************/
5/*                    Include common chip definitions                        */
6/*****************************************************************************/
7#include "bcmmips.h"
8#include "bchp_common.h"
9
10/*****************************************************************************/
11/*                    MIPS Physical Memory Map                               */
12/*****************************************************************************/
13#define CPU_PHYS_SDRAM_BASE             0x00000000      /* SDRAM Base */
14#define CPU_PHYS_ROM_BASE           0x1FC00000  /* ROM */
15#define CPU_PHYS_FLASH_BASE         0x1C000000
16#define CPU_PHYS_FPGA_BASE          0x1A000000
17#define CPU_PHYS_1394_BASE          0x19000000
18#define CPU_PHYS_POD_BASE                       0x19800000
19
20/*****************************************************************************/
21/*                   CPU to PCI Bridge Memory Map                            */
22/*****************************************************************************/
23
24#define CPU2PCI_CPU_PHYS_MEM_WIN_BASE     0xd0000000
25
26/* Allow CPU to access PCI memory addresses 0xd0000000 to 0xdfffffff */
27#define CPU2PCI_PCI_PHYS_MEM_WIN0_BASE    0xd0000000 /* Not used in A0 */
28#define CPU2PCI_PCI_PHYS_MEM_WIN1_BASE    0xd8000000 /* Not used in A0 */
29#define CPU2PCI_PCI_PHYS_MEM_WIN2_BASE    0xe0000000
30#define CPU2PCI_PCI_PHYS_MEM_WIN3_BASE    0xe8000000
31
32/* Allow CPU to access PCI I/O addresses 0xe0000000 to 0xe05fffff */
33#if (BRCM_ENDIAN_LITTLE == 1)
34#define CPU2PCI_PCI_PHYS_IO_WIN0_BASE     0x00000000
35#define CPU2PCI_PCI_PHYS_IO_WIN1_BASE     0x00200000
36#define CPU2PCI_PCI_PHYS_IO_WIN2_BASE     0x00400000
37#else
38#define CPU2PCI_PCI_PHYS_IO_WIN0_BASE     0x00000002
39#define CPU2PCI_PCI_PHYS_IO_WIN1_BASE     0x00200002
40#define CPU2PCI_PCI_PHYS_IO_WIN2_BASE     0x00400002
41#endif
42
43
44/*****************************************************************************/
45/*                      PCI Physical Memory Map                              */
46/*****************************************************************************/
47
48/* PCI physical memory map */
49#define PCI_7401_PHYS_ISB_WIN_BASE    0x10000000
50#if BCHP_CHIP == 7400 && (defined(BCHP_REV_B0) || defined(BCHP_REV_C0)|| defined(BCHP_REV_D0))
51#define PCI_7401_PHYS_MEM_WIN0_BASE   0x00000001
52#else
53#define PCI_7401_PHYS_MEM_WIN0_BASE   0x00000000
54#endif
55#define PCI_7401_PHYS_MEM_WIN1_BASE   0x02000000
56#define PCI_7401_PHYS_MEM_WIN2_BASE   0x04000000
57
58#define PCI_1394_PHYS_MEM_WIN0_BASE   0xd0000000
59#if BCM_BOARD==97456 || CFG_ECM==1
60#define PCI_3255_PHYS_REG_WIN0_BASE   0xd1000000
61#define PCI_3255_PHYS_MEM_WIN0_BASE   0xd8000000
62#define PCI_3255_PHYS_MEM_WIN1_BASE   0xd9000000
63#endif
64
65#define PCI_DEVICE_ID_EXT       0x0d
66#define PCI_DEVICE_ID_1394      0x0e
67#define PCI_DEVICE_ID_MINI      0x04
68#define PCI_DEVICE_ID_SATA      0 /* On 2ndary PCI bus */
69#if BCM_BOARD==97456 || CFG_ECM==1
70#define PCI_DEVICE_ID_3255              0x7 /* PCI AD23; PCI AD16=0, AD17=1... */
71#endif
72
73#define PCI_IDSEL_EXT           (0x10000 << PCI_DEVICE_ID_EXT)
74#define PCI_IDSEL_1394          (0x10000 << PCI_DEVICE_ID_1394)
75#define PCI_IDSEL_MINI          (0x10000 << PCI_DEVICE_ID_MINI)
76#define PCI_IDSEL_SATA          (0x10000 << PCI_DEVICE_ID_SATA)
77
78#define PCI_DEV_NUM_EXT         (PCI_DEVICE_ID_EXT  << 11)
79#define PCI_DEV_NUM_1394        (PCI_DEVICE_ID_1394 << 11)
80#define PCI_DEV_NUM_MINI        (PCI_DEVICE_ID_MINI << 11)
81#define PCI_DEV_NUM_SATA        (PCI_DEVICE_ID_SATA << 11)
82#if BCM_BOARD==97456 || CFG_ECM==1
83#define PCI_DEV_NUM_3255        (PCI_DEVICE_ID_3255 << 11)
84#endif
85
86/* SATA device */
87#define PCS0_OFS                                0x200
88#define PCS1_OFS                                0x240
89#define SCS0_OFS                                0x280
90#define SCS1_OFS                                0x2c0
91#define BM_OFS                                  0x300
92#define MMIO_OFS                                0xb0510000
93#define PCI_SATA_PHYS_REG_BASE  (0xb0520000 + PCS0_OFS)
94
95#define DRAM_SIZE (256*1024*1024)
96
97/*****************************************************************************/
98/*                      MIPS Virtual Memory Map                              */
99/*                                                                           */
100/* Note that the addresses above are physical addresses and that programs    */
101/* have to use converted addresses defined below:                            */
102/*****************************************************************************/
103#define DRAM_BASE_CACHE         BCM_PHYS_TO_K0(CPU_PHYS_SDRAM_BASE)   /* cached DRAM */
104#define DRAM_BASE_NOCACHE       BCM_PHYS_TO_K1(CPU_PHYS_SDRAM_BASE)   /* uncached DRAM */
105#define ROM_BASE_CACHE          BCM_PHYS_TO_K0(CPU_PHYS_ROM_BASE)
106#define ROM_BASE_NOCACHE        BCM_PHYS_TO_K1(CPU_PHYS_ROM_BASE)
107#define FLASH_BASE_NOCACHE  BCM_PHYS_TO_K1(CPU_PHYS_FLASH_BASE)
108#define FPGA_BASE_NOCACHE   BCM_PHYS_TO_K1(CPU_PHYS_FPGA_BASE)
109#define IEEE1394_BASE_NOCACHE   BCM_PHYS_TO_K1(CPU_PHYS_1394_BASE)
110
111#define PCI_MEM_WIN_BASE    0xd0000000
112#define PCI_MEM_WIN_SIZE    0x10000000
113#define PCI_IO_WIN_BASE     0xf0000000
114#define PCI_IO_WIN_SIZE     0x00600000
115
116
117
118/*****************************************************************************/
119/* Include chip specific .h files                                            */
120/*****************************************************************************/
121
122
123
124#endif
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