| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2012-2013, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: bmips4380.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/1 $ |
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| 12 | * $brcm_Date: 3/26/13 10:20a $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /rockford/bsp/common_bsp/mips/bmips4380.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/1 3/26/13 10:20a jkim |
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| 21 | * SWCFE-1131: Use common files for all chips. |
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| 22 | * |
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| 23 | ***************************************************************************/ |
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| 24 | #ifndef __BMIPS_4380_H__ |
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| 25 | #define __BMIPS_4380_H__ |
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| 26 | |
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| 27 | #include "bmips.h" |
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| 28 | |
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| 29 | |
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| 30 | #if defined(__ASSEMBLER__) |
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| 31 | #define CP0_INDEX $0 |
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| 32 | #define CP0_RANDOM $1 |
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| 33 | #define CP0_ENTRY_LO_0 $2 |
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| 34 | #define CP0_ENTRY_LO_1 $3 |
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| 35 | #define CP0_CONTEXT $4 |
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| 36 | #define CP0_PAGE_MASK $5 |
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| 37 | #define CP0_WIRED $6 |
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| 38 | #define CP0_BAD_VADDR $8 |
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| 39 | #define CP0_COUNT $9 |
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| 40 | #define CP0_ENTRY_HI $10 |
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| 41 | #define CP0_COMPARE $11 |
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| 42 | #define CP0_STATUS $12 |
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| 43 | #define CP0_CAUSE $13 |
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| 44 | #define CP0_EPC $14 |
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| 45 | #define CPO_PROC_ID $15 |
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| 46 | #define CP0_CONFIG $16 |
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| 47 | #define CP0_CONFIG1 $16,1 |
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| 48 | #define CP0_LLADDR $17 |
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| 49 | #define CP0_BRCM_CONFIG0 $22 |
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| 50 | #define CP0_CMT_INTERRUPT $22,1 |
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| 51 | #define CP0_CMT_CONTROL $22,2 |
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| 52 | #define CP0_CMT_LOCAL $22,3 |
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| 53 | #define CP0_EXCP_SER $22,4 |
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| 54 | #define CP0_BRCM_CONFIG1 $22,5 |
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| 55 | #define CP0_CORE_BASE $22,6 |
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| 56 | #define CP0_DEBUG $23 |
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| 57 | #define CP0_DEBUG_EPC $24 |
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| 58 | #define CP0_TAG_LO $28 |
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| 59 | #define CP0_DATA_LO $28,1 |
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| 60 | #define CP0_ERROR_EPC $30 |
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| 61 | #define CP0_DE_SAVE $31 |
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| 62 | #endif |
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| 63 | |
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| 64 | #define CP0_INDEX_Index_MASK _MM_MAKEMASK(5,0) |
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| 65 | #define CCP0_INDEX_Index_SHIFT (0) |
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| 66 | |
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| 67 | #define CP0_RANDOM_P_MASK _MM_MAKEMASK1(31) |
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| 68 | #define CP0_RANDOM_P_SHIFT (31) |
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| 69 | |
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| 70 | #define CP0_RANDOM_RANDOM_MASK _MM_MAKEMASK(5,0) |
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| 71 | #define CP0_RANDOM_RANDOM_SHIFT (0) |
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| 72 | |
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| 73 | #define CP0_ENTRY_LO_0_G_MASK _MM_MAKEMASK1(0) |
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| 74 | #define CP0_ENTRY_LO_0_G_SHIFT (0) |
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| 75 | |
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| 76 | #define CP0_ENTRY_LO_0_V_MASK _MM_MAKEMASK1(1) |
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| 77 | #define CP0_ENTRY_LO_0_V_SHIFT (1) |
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| 78 | |
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| 79 | #define CP0_ENTRY_LO_0_D_MASK _MM_MAKEMASK1(2) |
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| 80 | #define CP0_ENTRY_LO_0_D_SHIFT (2) |
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| 81 | |
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| 82 | #define CP0_ENTRY_LO_0_CA_MASK _MM_MAKEMASK(3,3) |
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| 83 | #define CP0_ENTRY_LO_0_CA_SHIFT (3) |
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| 84 | |
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| 85 | #define CP0_ENTRY_LO_0_PFN_MASK _MM_MAKEMASK(20,6) |
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| 86 | #define CP0_ENTRY_LO_0_PFN_SHIFT (6) |
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| 87 | |
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| 88 | #define CP0_ENTRY_LO_1_G_MASK _MM_MAKEMASK1(0) |
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| 89 | #define CP0_ENTRY_LO_1_G_SHIFT (0) |
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| 90 | |
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| 91 | #define CP0_ENTRY_LO_1_V_MASK _MM_MAKEMASK1(1) |
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| 92 | #define CP0_ENTRY_LO_1_V_SHIFT (1) |
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| 93 | |
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| 94 | #define CP0_ENTRY_LO_1_D_MASK _MM_MAKEMASK1(2) |
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| 95 | #define CP0_ENTRY_LO_1_D_SHIFT (2) |
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| 96 | |
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| 97 | #define CP0_ENTRY_LO_1_CA_MASK _MM_MAKEMASK(3,3) |
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| 98 | #define CP0_ENTRY_LO_1_CA_SHIFT (3) |
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| 99 | |
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| 100 | #define CP0_ENTRY_LO_1_PFN_MASK _MM_MAKEMASK(20,6) |
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| 101 | #define CP0_ENTRY_LO_1_PFN_SHIFT (6) |
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| 102 | |
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| 103 | #define CP0_CONTEXT_BadVPN2_MASK _MM_MAKEMASK(19,4) |
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| 104 | #define CP0_CONTEXT_BadVPN2_SHIFT (4) |
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| 105 | |
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| 106 | #define CP0_CONTEXT_PTEBASE_MASK _MM_MAKEMASK(9,23) |
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| 107 | #define CP0_CONTEXT_PTEBASE_SHIFT (23) |
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| 108 | |
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| 109 | #define CP0_PAGE_MASK_MASK_MASK _MM_MAKEMASK(16,13) |
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| 110 | #define CP0_PAGE_MASK_MASK_SHIFT (13) |
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| 111 | |
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| 112 | #define CP0_WIRED_WIRED_MASK _MM_MAKEMASK(5,0) |
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| 113 | #define CP0_WIRED_WIRED_SHIFT (0) |
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| 114 | |
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| 115 | #define CP0_BAD_VADDR_BadVAddr_MASK _MM_MAKEMASK(32,0) |
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| 116 | #define CP0_BAD_VADDR_BadVAddr_SHIFT (0) |
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| 117 | |
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| 118 | #define CP0_COUNT_COUNT_MASK _MM_MAKEMASK(32,0) |
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| 119 | #define CP0_COUNT_COUNT_SHIFT (0) |
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| 120 | |
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| 121 | #define CP0_ENTRY_HI_ASID_MASK _MM_MAKEMASK(8,0) |
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| 122 | #define CP0_ENTRY_HI_ASID_SHIFT (0) |
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| 123 | |
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| 124 | #define CP0_ENTRY_HI_VPN2_MASK _MM_MAKEMASK(19,13) |
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| 125 | #define CP0_ENTRY_HI_VPN2_SHIFT (13) |
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| 126 | |
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| 127 | #define CP0_COMPARE_COMPARE_MASK _MM_MAKEMASK(32,0) |
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| 128 | #define CP0_COMPARE_COMPARE_SHIFT (0) |
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| 129 | |
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| 130 | #define CP0_STATUS_CU0_MASK _MM_MAKEMASK1(28) |
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| 131 | #define CP0_STATUS_CU0_SHIFT (28) |
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| 132 | |
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| 133 | #define CP0_STATUS_CU1_MASK _MM_MAKEMASK1(29) |
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| 134 | #define CP0_STATUS_CU1_SHIFT (28) |
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| 135 | |
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| 136 | #define CP0_STATUS_CU2_MASK _MM_MAKEMASK1(30) |
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| 137 | #define CP0_STATUS_CU2_SHIFT (28) |
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| 138 | |
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| 139 | #define CP0_STATUS_CU3_MASK _MM_MAKEMASK1(31) |
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| 140 | #define CP0_STATUS_CU3_SHIFT (28) |
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| 141 | |
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| 142 | #define CP0_STATUS_FR_MASK _MM_MAKEMASK1(26) |
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| 143 | #define CP0_STATUS_FR_SHIFT (26) |
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| 144 | |
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| 145 | #define CP0_STATUS_RE_MASK _MM_MAKEMASK1(25) |
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| 146 | #define CP0_STATUS_RE_SHIFT (25) |
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| 147 | |
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| 148 | #define CP0_STATUS_BEV_MASK _MM_MAKEMASK1(22) |
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| 149 | #define CP0_STATUS_BEV_SHIFT (22) |
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| 150 | |
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| 151 | #define CP0_STATUS_TS_MASK _MM_MAKEMASK1(21) |
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| 152 | #define CP0_STATUS_TS_SHIFT (21) |
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| 153 | |
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| 154 | #define CP0_STATUS_SR_MASK _MM_MAKEMASK1(20) |
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| 155 | #define CP0_STATUS_SR_SHIFT (20) |
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| 156 | |
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| 157 | #define CP0_STATUS_NMI_MASK _MM_MAKEMASK1(19) |
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| 158 | #define CP0_STATUS_NMI_SHIFT (19) |
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| 159 | |
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| 160 | #define CP0_STATUS_IM_MASK _MM_MAKEMASK(8,8) |
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| 161 | #define CP0_STATUS_IM_SHIFT (8) |
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| 162 | |
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| 163 | #define CP0_STATUS_KSU_MASK _MM_MAKEMASK(2,3) |
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| 164 | #define CP0_STATUS_KSU_SHIFT (3) |
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| 165 | |
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| 166 | #define CP0_STATUS_ERL_MASK _MM_MAKEMASK1(2) |
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| 167 | #define CP0_STATUS_ERL_SHIFT (2) |
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| 168 | |
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| 169 | #define CP0_STATUS_EXL_MASK _MM_MAKEMASK1(1) |
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| 170 | #define CP0_STATUS_EXL_SHIFT (1) |
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| 171 | |
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| 172 | #define CP0_STATUS_IE_MASK _MM_MAKEMASK1(0) |
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| 173 | #define CP0_STATUS_IE_SHIFT (0) |
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| 174 | |
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| 175 | #define CP0_CAUSE_BD_MASK _MM_MAKEMASK1(31) |
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| 176 | #define CP0_CAUSE_BD_SHIFT (31) |
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| 177 | |
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| 178 | #define CP0_CAUSE_CE_MASK _MM_MAKEMASK(2,28) |
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| 179 | #define CP0_CAUSE_CE_SHIFT (28) |
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| 180 | |
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| 181 | #define CP0_CAUSE_IV_MASK _MM_MAKEMASK1(23) |
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| 182 | #define CP0_CAUSE_IV_SHIFT (23) |
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| 183 | |
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| 184 | #define CP0_CAUSE_IP_MASK _MM_MAKEMASK(6,10) |
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| 185 | #define CP0_CAUSE_IP_SHIFT (10) |
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| 186 | |
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| 187 | #define CP0_CAUSE_SW_MASK _MM_MAKEMASK(2,8) |
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| 188 | #define CP0_CAUSE_SW_SHIFT (8) |
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| 189 | |
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| 190 | #define CP0_CAUSE_EXCCODE_MASK _MM_MAKEMASK(5,2) |
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| 191 | #define CP0_CAUSE_EXCCODE_SHIFT (2) |
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| 192 | |
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| 193 | #define CP0_EPC_EPC_MASK _MM_MAKEMASK(32,0) |
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| 194 | #define CP0_EPC_EPC_SHIFT (0) |
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| 195 | |
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| 196 | #define CPO_PROC_ID_COMPANYOPTIONS_MASK _MM_MAKEMASK(8,24) |
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| 197 | #define CPO_PROC_ID_COMPANYOPTIONS_SHIFT (24) |
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| 198 | |
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| 199 | #define CPO_PROC_ID_COMPANYID_MASK _MM_MAKEMASK(8,16) |
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| 200 | #define CPO_PROC_ID_COMPANYID_SHIFT (16) |
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| 201 | |
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| 202 | #define CPO_PROC_ID_PROCESSORID_MASK _MM_MAKEMASK(8,8) |
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| 203 | #define CPO_PROC_ID_PROCESSORID_SHIFT (8) |
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| 204 | |
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| 205 | #define CPO_PROC_ID_REVISION_MASK _MM_MAKEMASK(8,0) |
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| 206 | #define CPO_PROC_ID_REVISION_SHIFT (0) |
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| 207 | |
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| 208 | #define CP0_CONFIG_M_MASK _MM_MAKEMASK1(31) |
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| 209 | #define CP0_CONFIG_M_SHIFT (31) |
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| 210 | |
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| 211 | #define CP0_CONFIG_U_MASK _MM_MAKEMASK(15,16) |
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| 212 | #define CP0_CONFIG_U_SHIFT (16) |
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| 213 | |
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| 214 | #define CP0_CONFIG_BE_MASK _MM_MAKEMASK1(15) |
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| 215 | #define CP0_CONFIG_BE_SHIFT (15) |
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| 216 | |
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| 217 | #define CP0_CONFIG_AT_MASK _MM_MAKEMASK(2,13) |
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| 218 | #define CP0_CONFIG_AT_SHIFT (13) |
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| 219 | |
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| 220 | #define CP0_CONFIG_AR_MASK _MM_MAKEMASK(3,10) |
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| 221 | #define CP0_CONFIG_AR_SHIFT (10) |
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| 222 | |
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| 223 | #define CP0_CONFIG_MT_MASK _MM_MAKEMASK(3,7) |
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| 224 | #define CP0_CONFIG_MT_SHIFT (7) |
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| 225 | |
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| 226 | #define CP0_CONFIG_K0_MASK _MM_MAKEMASK(3,0) |
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| 227 | #define CP0_CONFIG_K0_SHIFT (0) |
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| 228 | |
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| 229 | #define CP0_CONFIG1_M_MASK _MM_MAKEMASK1(31) |
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| 230 | #define CP0_CONFIG1_M_SHIFT (31) |
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| 231 | |
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| 232 | #define CP0_CONFIG1_TLBSZ_MASK _MM_MAKEMASK(6,25) |
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| 233 | #define CP0_CONFIG1_TLBSZ_SHIFT (25) |
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| 234 | |
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| 235 | #define CP0_CONFIG1_IS_MASK _MM_MAKEMASK(3,22) |
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| 236 | #define CP0_CONFIG1_IS_SHIFT (22) |
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| 237 | |
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| 238 | #define CP0_CONFIG1_IL_MASK _MM_MAKEMASK(3,19) |
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| 239 | #define CP0_CONFIG1_IL_SHIFT (19) |
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| 240 | |
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| 241 | #define CP0_CONFIG1_IA_MASK _MM_MAKEMASK(3,16) |
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| 242 | #define CP0_CONFIG1_IA_SHIFT (16) |
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| 243 | |
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| 244 | #define CP0_CONFIG1_DS_MASK _MM_MAKEMASK(3,13) |
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| 245 | #define CP0_CONFIG1_DS_SHIFT (13) |
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| 246 | |
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| 247 | #define CP0_CONFIG1_DL_MASK _MM_MAKEMASK(3,10) |
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| 248 | #define CP0_CONFIG1_DL_SHIFT (10) |
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| 249 | |
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| 250 | #define CP0_CONFIG1_DA_MASK _MM_MAKEMASK(3,7) |
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| 251 | #define CP0_CONFIG1_DA_SHIFT (7) |
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| 252 | |
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| 253 | #define CP0_CONFIG1_C2_MASK _MM_MAKEMASK1(6) |
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| 254 | #define CP0_CONFIG1_C2_SHIFT (6) |
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| 255 | |
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| 256 | #define CP0_CONFIG1_MD_MASK _MM_MAKEMASK1(5) |
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| 257 | #define CP0_CONFIG1_MD_SHIFT (5) |
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| 258 | |
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| 259 | #define CP0_CONFIG1_PC_MASK _MM_MAKEMASK1(4) |
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| 260 | #define CP0_CONFIG1_PC_SHIFT (4) |
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| 261 | |
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| 262 | #define CP0_CONFIG1_WR_MASK _MM_MAKEMASK1(3) |
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| 263 | #define CP0_CONFIG1_WR_SHIFT (3) |
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| 264 | |
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| 265 | #define CP0_CONFIG1_CA_MASK _MM_MAKEMASK1(2) |
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| 266 | #define CP0_CONFIG1_CA_SHIFT (2) |
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| 267 | |
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| 268 | #define CP0_CONFIG1_EP_MASK _MM_MAKEMASK1(1) |
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| 269 | #define CP0_CONFIG1_EP_SHIFT (1) |
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| 270 | |
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| 271 | #define CP0_CONFIG1_FP_MASK _MM_MAKEMASK1(0) |
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| 272 | #define CP0_CONFIG1_FP_SHIFT (0) |
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| 273 | |
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| 274 | #define CP0_LLADDR_PADDR_MASK _MM_MAKEMASK(28,0) |
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| 275 | #define CP0_LLADDR_PADDR_SHIFT (0) |
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| 276 | |
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| 277 | #define CP0_BRCM_CONFIG0_ICE_MASK _MM_MAKEMASK1(31) |
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| 278 | #define CP0_BRCM_CONFIG0_ICE_SHIFT (31) |
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| 279 | |
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| 280 | #define CP0_BRCM_CONFIG0_DCE_MASK _MM_MAKEMASK1(30) |
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| 281 | #define CP0_BRCM_CONFIG0_DCE_SHIFT (30) |
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| 282 | |
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| 283 | #define CP0_BRCM_CONFIG0_RAC_MASK _MM_MAKEMASK1(29) |
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| 284 | #define CP0_BRCM_CONFIG0_RAC_SHIFT (29) |
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| 285 | |
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| 286 | #define CP0_BRCM_CONFIG0_TLBPD_MASK _MM_MAKEMASK1(28) |
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| 287 | #define CP0_BRCM_CONFIG0_TLBPD_SHIFT (28) |
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| 288 | |
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| 289 | #define CP0_BRCM_CONFIG0_EJTGPD_MASK _MM_MAKEMASK1(27) |
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| 290 | #define CP0_BRCM_CONFIG0_EJTGPD_SHIFT (27) |
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| 291 | |
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| 292 | #define CP0_BRCM_CONFIG0_DSUP_MASK _MM_MAKEMASK1(25) |
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| 293 | #define CP0_BRCM_CONFIG0_DSUP_SHIFT (25) |
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| 294 | |
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| 295 | #define CP0_BRCM_CONFIG0_DCP_MASK _MM_MAKEMASK1(24) |
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| 296 | #define CP0_BRCM_CONFIG0_DCP_SHIFT (24) |
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| 297 | |
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| 298 | #define CP0_BRCM_CONFIG0_BHTD_MASK _MM_MAKEMASK1(21) |
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| 299 | #define CP0_BRCM_CONFIG0_BHTD_SHIFT (21) |
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| 300 | |
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| 301 | #define CP0_BRCM_CONFIG0_CLF_MASK _MM_MAKEMASK1(20) |
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| 302 | #define CP0_BRCM_CONFIG0_CLF_SHIFT (20) |
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| 303 | |
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| 304 | #define CP0_BRCM_CONFIG0_LMB_MASK _MM_MAKEMASK1(19) |
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| 305 | #define CP0_BRCM_CONFIG0_LMB_SHIFT (19) |
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| 306 | |
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| 307 | #define CP0_BRCM_CONFIG0_CMT_MASK _MM_MAKEMASK1(18) |
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| 308 | #define CP0_BRCM_CONFIG0_CMT_SHIFT (18) |
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| 309 | |
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| 310 | #define CP0_BRCM_CONFIG0_NBK_MASK _MM_MAKEMASK1(17) |
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| 311 | #define CP0_BRCM_CONFIG0_NBK_SHIFT (17) |
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| 312 | |
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| 313 | #define CP0_BRCM_CONFIG0_CM_MASK _MM_MAKEMASK1(16) |
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| 314 | #define CP0_BRCM_CONFIG0_CM_SHIFT (16) |
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| 315 | |
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| 316 | #define CP0_BRCM_CONFIG0_L2_MASK _MM_MAKEMASK1(13) |
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| 317 | #define CP0_BRCM_CONFIG0_L2_SHIFT (13) |
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| 318 | |
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| 319 | #define CP0_BRCM_CONFIG0_SIC_MASK _MM_MAKEMASK1(12) |
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| 320 | #define CP0_BRCM_CONFIG0_SIC_SHIFT (12) |
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| 321 | |
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| 322 | #define CP0_BRCM_CONFIG0_nHILO_MASK _MM_MAKEMASK(2,2) |
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| 323 | #define CP0_BRCM_CONFIG0_nHILO_SHIFT (2) |
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| 324 | |
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| 325 | #define CP0_BRCM_CONFIG0_eDSP_MASK _MM_MAKEMASK1(1) |
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| 326 | #define CP0_BRCM_CONFIG0_eDSP_SHIFT (1) |
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| 327 | |
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| 328 | #define CP0_BRCM_CONFIG0_CNTD_MASK _MM_MAKEMASK1(0) |
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| 329 | #define CP0_BRCM_CONFIG0_CNTD_SHIFT (0) |
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| 330 | |
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| 331 | #define CP0_CMT_INTERRUPT_XIR_MASK _MM_MAKEMASK(5,27) |
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| 332 | #define CP0_CMT_INTERRUPT_XIR_SHIFT (27) |
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| 333 | |
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| 334 | #define CP0_CMT_INTERRUPT_SIR_MASK _MM_MAKEMASK(2,15) |
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| 335 | #define CP0_CMT_INTERRUPT_SIR_SHIFT (15) |
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| 336 | |
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| 337 | #define CP0_CMT_INTERRUPT_NMIR_MASK _MM_MAKEMASK(2,0) |
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| 338 | #define CP0_CMT_INTERRUPT_NMIR_SHIFT (0) |
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| 339 | |
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| 340 | #define CP0_CMT_CONTROL_DSUTP_MASK _MM_MAKEMASK(2,30) |
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| 341 | #define CP0_CMT_CONTROL_DSUTP_SHIFT (30) |
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| 342 | |
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| 343 | #define CP0_CMT_CONTROL_PRTY_MASK _MM_MAKEMASK(2,4) |
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| 344 | #define CP0_CMT_CONTROL_PRTY_SHIFT (4) |
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| 345 | |
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| 346 | #define CP0_CMT_CONTROL_RSTSE_MASK _MM_MAKEMASK1(0) |
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| 347 | #define CP0_CMT_CONTROL_RSTSE_SHIFT (0) |
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| 348 | |
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| 349 | #define CP0_CMT_LOCAL_TPID_MASK _MM_MAKEMASK1(31) |
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| 350 | #define CP0_CMT_LOCAL_TPID_SHIFT (31) |
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| 351 | |
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| 352 | #define CP0_CMT_LOCAL_DCC_MASK _MM_MAKEMASK1(28) |
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| 353 | #define CP0_CMT_LOCAL_DCC_SHIFT (28) |
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| 354 | |
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| 355 | #define CP0_CMT_LOCAL_BPUC_MASK _MM_MAKEMASK1(26) |
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| 356 | #define CP0_CMT_LOCAL_BPUC_SHIFT (26) |
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| 357 | |
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| 358 | #define CP0_CMT_LOCAL_GSSL_MASK _MM_MAKEMASK(2,0) |
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| 359 | #define CP0_CMT_LOCAL_GSSL_SHIFT (0) |
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| 360 | |
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| 361 | #define CP0_EXCP_SER_ETPL_MASK _MM_MAKEMASK(2,30) |
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| 362 | #define CP0_EXCP_SER_ETP_SHIFT (30) |
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| 363 | |
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| 364 | #define CP0_REG_22_SEL4_SCN_MASK _MM_MAKEMASK(8,0) |
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| 365 | #define CP0_REG_22_SEL4_SCN_SHIFT (0) |
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| 366 | |
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| 367 | #define CP0_BRCM_CONFIG1_ASCR_MASK _MM_MAKEMASK(2,29) |
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| 368 | #define CP0_BRCM_CONFIG1_ASCR_SHIFT (29) |
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| 369 | |
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| 370 | #define CP0_BRCM_CONFIG1_ASC_MASK _MM_MAKEMASK1(28) |
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| 371 | #define CP0_BRCM_CONFIG1_ASC_SHIFT (28) |
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| 372 | |
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| 373 | #define CP0_BRCM_CONFIG1_SSMR_MASK _MM_MAKEMASK1(18) |
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| 374 | #define CP0_BRCM_CONFIG1_SSMR_SHIFT (18) |
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| 375 | |
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| 376 | #define CP0_BRCM_CONFIG1_SSR_MASK _MM_MAKEMASK1(2) |
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| 377 | #define CP0_BRCM_CONFIG1_SSR_SHIFT (2) |
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| 378 | |
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| 379 | #define CP0_BRCM_CONFIG1_SHR_MASK _MM_MAKEMASK1(1) |
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| 380 | #define CP0_BRCM_CONFIG1_SHR_SHIFT (1) |
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| 381 | |
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| 382 | #define CP0_BRCM_CONFIG1_BDR_MASK _MM_MAKEMASK1(0) |
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| 383 | #define CP0_BRCM_CONFIG1_BDR_SHIFT (0) |
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| 384 | |
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| 385 | #define CP0_CORE_BASE_CBA_MASK _MM_MAKEMASK(14,18) |
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| 386 | #define CP0_CORE_BASE_CBA_SHIFT (18) |
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| 387 | |
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| 388 | #define CP0_CORE_BASE_MSK_MASK _MM_MAKEMASK(4,2) |
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| 389 | #define CP0_CORE_BASE_MSK_SHIFT (2) |
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| 390 | |
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| 391 | #define CP0_DEBUG_DBD_MASK _MM_MAKEMASK1(31) |
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| 392 | #define CP0_DEBUG_DBD_SHIFT (31) |
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| 393 | |
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| 394 | #define CP0_DEBUG_DM_MASK _MM_MAKEMASK1(30) |
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| 395 | #define CP0_DEBUG_DM_SHIFT (30) |
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| 396 | |
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| 397 | #define CP0_DEBUG_NIS_MASK _MM_MAKEMASK1(14) |
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| 398 | #define CP0_DEBUG_NIS_SHIFT (14) |
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| 399 | |
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| 400 | #define CP0_DEBUG_UMS_MASK _MM_MAKEMASK1(13) |
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| 401 | #define CP0_DEBUG_UMS_SHIFT (13) |
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| 402 | |
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| 403 | #define CP0_DEBUG_OES_MASK _MM_MAKEMASK1(12) |
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| 404 | #define CP0_DEBUG_OES_SHIFT (12) |
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| 405 | |
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| 406 | #define CP0_DEBUG_TLF_MASK _MM_MAKEMASK1(11) |
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| 407 | #define CP0_DEBUG_TLF_SHIFT (11) |
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| 408 | |
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| 409 | #define CP0_DEBUG_BsF_MASK _MM_MAKEMASK1(10) |
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| 410 | #define CP0_DEBUG_BsF_SHIFT (10) |
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| 411 | |
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| 412 | #define CP0_DEBUG_SSt_MASK _MM_MAKEMASK1(8) |
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| 413 | #define CP0_DEBUG_SSt_SHIFT (8) |
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| 414 | |
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| 415 | #define CP0_DEBUG_Jtag_Rst_MASK _MM_MAKEMASK1(7) |
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| 416 | #define CP0_DEBUG_Jtag_Rst_SHIFT (7) |
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| 417 | |
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| 418 | #define CP0_DEBUG_DINT_MASK _MM_MAKEMASK1(5) |
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| 419 | #define CP0_DEBUG_DINT_SHIFT (5) |
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| 420 | |
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| 421 | #define CP0_DEBUG_DIB_MASK _MM_MAKEMASK1(4) |
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| 422 | #define CP0_DEBUG_DIB_SHIFT (4) |
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| 423 | |
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| 424 | #define CP0_DEBUG_DDBS_MASK _MM_MAKEMASK1(3) |
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| 425 | #define CP0_DEBUG_DDBS_SHIFT (3) |
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| 426 | |
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| 427 | #define CP0_DEBUG_DDBS_MASK _MM_MAKEMASK1(3) |
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| 428 | #define CP0_DEBUG_DDBS_SHIFT (3) |
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| 429 | |
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| 430 | #define CP0_DEBUG_DDBL_MASK _MM_MAKEMASK1(2) |
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| 431 | #define CP0_DEBUG_DDBL_SHIFT (2) |
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| 432 | |
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| 433 | #define CP0_DEBUG_DBp_MASK _MM_MAKEMASK1(1) |
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| 434 | #define CP0_DEBUG_DBp_SHIFT (1) |
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| 435 | |
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| 436 | #define CP0_DEBUG_DSS_MASK _MM_MAKEMASK1(0) |
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| 437 | #define CP0_DEBUG_DSS_SHIFT (0) |
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| 438 | |
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| 439 | #define CP0_DEBUG_EPC_DEPC_MASK _MM_MAKEMASK(32,0) |
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| 440 | #define CP0_DEBUG_EPC_DEPC_SHIFT (0) |
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| 441 | |
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| 442 | #define CP0_TAG_LO_PA_MASK _MM_MAKEMASK(20,12) |
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| 443 | #define CP0_TAG_LO_PA_SHIFT (12) |
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| 444 | |
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| 445 | #define CP0_TAG_LO_Dirty_MASK _MM_MAKEMASK1(7) |
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| 446 | #define CP0_TAG_LO_Dirty_SHIFT (7) |
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| 447 | |
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| 448 | #define CP0_TAG_LO_Valid_MASK _MM_MAKEMASK1(6) |
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| 449 | #define CP0_TAG_LO_Valid_SHIFT (6) |
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| 450 | |
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| 451 | #define CP0_TAG_LO_Lock_MASK _MM_MAKEMASK1(5) |
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| 452 | #define CP0_TAG_LO_Lock_SHIFT (5) |
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| 453 | |
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| 454 | #define CP0_DATA_LO_DATA_MASK _MM_MAKEMASK(32,0) |
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| 455 | #define CP0_DATA_LO_DATA_SHIFT (0) |
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| 456 | |
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| 457 | #define CP0_ERROR_EPC_ErrorEPC_MASK _MM_MAKEMASK(32,0) |
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| 458 | #define CP0_ERROR_EPC_ErrorEPC_SHIFT (0) |
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| 459 | |
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| 460 | #define CP0_DE_SAVE_DESAVE_MASK _MM_MAKEMASK(32,0) |
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| 461 | #define CP0_DE_SAVE_DESAVE_SHIFT (0) |
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| 462 | |
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| 463 | #define CP0_L2_CONFIG_L2E_DCACHE_MISS_LOOKUP 0x40000000 |
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| 464 | #define CP0_L2_CONFIG_L2E_ICACHE_MISS_LOOKUP_TP0 0x20000000 |
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| 465 | #define CP0_L2_CONFIG_L2E_ICACHE_MISS_LOOKUP_TP1 0x10000000 |
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| 466 | |
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| 467 | #ifdef NEW_BSP_CFE |
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| 468 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
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| 469 | #endif |
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| 470 | |
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| 471 | #endif |
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