| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2012-2011, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: chipcfg.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/1 $ |
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| 12 | * $brcm_Date: 4/28/11 1:39p $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /rockford/bsp/bcm97358/no-os/src/sde/chipcfg.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/1 4/28/11 1:39p jkim |
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| 21 | * SWCFE-507: Initial file |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/1 11/9/10 4:53p jkim |
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| 24 | * SWCFE-399: initial files |
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| 25 | * |
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| 26 | * Bsp_Software_Devel/2 3/16/10 1:30p jkim |
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| 27 | * SW7340-135: 1. Add SPI flash support. |
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| 28 | * |
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| 29 | * Bsp_Software_Devel/6 12/19/07 11:17a farshidf |
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| 30 | * PR36839: SATA |
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| 31 | * |
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| 32 | * Bsp_Software_Devel/5 12/18/07 6:50p farshidf |
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| 33 | * PR36869: Fix warning |
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| 34 | * |
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| 35 | * Bsp_Software_Devel/4 12/18/07 3:02p farshidf |
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| 36 | * PR36869: remove warning |
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| 37 | * |
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| 38 | * Bsp_Software_Devel/3 12/18/07 2:56p farshidf |
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| 39 | * PR36869: Add Sata |
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| 40 | * |
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| 41 | * Bsp_Software_Devel/2 11/13/07 12:35p farshidf |
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| 42 | * PR36869: 7335 CFE |
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| 43 | * |
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| 44 | * Bsp_Software_Devel/2 10/31/07 3:47p farshidf |
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| 45 | * PR36360: new CFE/BSP code |
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| 46 | * |
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| 47 | * Bsp_Software_Devel/1 10/22/07 4:41p farshidf |
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| 48 | * PR36360: New BSP code |
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| 49 | * |
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| 50 | |
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| 51 | ***************************************************************************/ |
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| 52 | |
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| 53 | #ifndef __CHIPCFG_H__ |
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| 54 | #define __CHIPCFG_H__ |
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| 55 | |
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| 56 | |
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| 57 | /*****************************************************************************/ |
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| 58 | /* CPU to PCI Bridge Memory Map */ |
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| 59 | /*****************************************************************************/ |
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| 60 | |
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| 61 | #define CPU2PCI_CPU_PHYS_MEM_WIN_BASE 0xd0000000 |
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| 62 | |
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| 63 | /* Allow CPU to access PCI memory addresses 0xd0000000 to 0xdfffffff */ |
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| 64 | #define CPU2PCI_PCI_PHYS_MEM_WIN0_BASE 0xd0000000 /* Not used in A0 */ |
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| 65 | #define CPU2PCI_PCI_PHYS_MEM_WIN1_BASE 0xd8000000 /* Not used in A0 */ |
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| 66 | #define CPU2PCI_PCI_PHYS_MEM_WIN2_BASE 0xe0000000 |
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| 67 | #define CPU2PCI_PCI_PHYS_MEM_WIN3_BASE 0xe8000000 |
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| 68 | |
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| 69 | /* Allow CPU to access PCI I/O addresses 0xe0000000 to 0xe05fffff */ |
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| 70 | #if (BRCM_ENDIAN_LITTLE == 1) |
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| 71 | #define CPU2PCI_PCI_PHYS_IO_WIN0_BASE 0x00000000 |
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| 72 | #define CPU2PCI_PCI_PHYS_IO_WIN1_BASE 0x00200000 |
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| 73 | #define CPU2PCI_PCI_PHYS_IO_WIN2_BASE 0x00400000 |
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| 74 | #else |
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| 75 | #define CPU2PCI_PCI_PHYS_IO_WIN0_BASE 0x00000002 |
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| 76 | #define CPU2PCI_PCI_PHYS_IO_WIN1_BASE 0x00200002 |
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| 77 | #define CPU2PCI_PCI_PHYS_IO_WIN2_BASE 0x00400002 |
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| 78 | #endif |
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| 79 | |
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| 80 | |
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| 81 | /*****************************************************************************/ |
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| 82 | /* PCI Physical Memory Map */ |
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| 83 | /*****************************************************************************/ |
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| 84 | |
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| 85 | /* PCI physical memory map */ |
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| 86 | #define PCI_PHYS_ISB_WIN_BASE 0x10000000 |
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| 87 | #define PCI_PHYS_MEM_WIN0_BASE 0x00000000 |
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| 88 | #define PCI_PHYS_MEM_WIN1_BASE 0x02000000 |
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| 89 | #define PCI_PHYS_MEM_WIN2_BASE 0x04000000 |
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| 90 | |
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| 91 | #define PCI_1394_PHYS_MEM_WIN0_BASE 0xd0000000 |
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| 92 | |
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| 93 | |
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| 94 | #define PCI_3255_PHYS_REG_WIN0_BASE 0xd1000000 |
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| 95 | #define PCI_3255_PHYS_MEM_WIN0_BASE 0xd8000000 |
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| 96 | #define PCI_3255_PHYS_MEM_WIN1_BASE 0xd9000000 |
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| 97 | |
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| 98 | |
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| 99 | #define PCI_DEVICE_ID_EXT 0x0d |
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| 100 | #define PCI_DEVICE_ID_1394 0x0e |
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| 101 | #define PCI_DEVICE_ID_MINI 0x04 |
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| 102 | #define PCI_DEVICE_ID_SATA 0 /* On 2ndary PCI bus */ |
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| 103 | |
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| 104 | #define PCI_DEVICE_ID_3255 0x7 /* PCI AD23; PCI AD16=0, AD17=1... */ |
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| 105 | |
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| 106 | |
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| 107 | #define PCI_IDSEL_EXT (0x10000 << PCI_DEVICE_ID_EXT) |
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| 108 | #define PCI_IDSEL_1394 (0x10000 << PCI_DEVICE_ID_1394) |
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| 109 | #define PCI_IDSEL_MINI (0x10000 << PCI_DEVICE_ID_MINI) |
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| 110 | #define PCI_IDSEL_SATA (0x10000 << PCI_DEVICE_ID_SATA) |
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| 111 | |
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| 112 | #define PCI_DEV_NUM_EXT (PCI_DEVICE_ID_EXT << 11) |
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| 113 | #define PCI_DEV_NUM_1394 (PCI_DEVICE_ID_1394 << 11) |
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| 114 | #define PCI_DEV_NUM_MINI (PCI_DEVICE_ID_MINI << 11) |
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| 115 | #define PCI_DEV_NUM_SATA (PCI_DEVICE_ID_SATA << 11) |
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| 116 | |
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| 117 | #define PCI_DEV_NUM_3255 (PCI_DEVICE_ID_3255 << 11) |
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| 118 | |
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| 119 | |
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| 120 | /* SATA device */ |
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| 121 | #define PCS0_OFS 0x200 |
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| 122 | #define PCS1_OFS 0x240 |
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| 123 | #define SCS0_OFS 0x280 |
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| 124 | #define SCS1_OFS 0x2c0 |
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| 125 | #define BM_OFS 0x300 |
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| 126 | #define MMIO_OFS 0xb0510000 |
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| 127 | #define PCI_SATA_PHYS_REG_BASE (0xb0520000 + PCS0_OFS) |
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| 128 | |
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| 129 | #define PCI_MEM_WIN_BASE 0xd0000000 |
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| 130 | #define PCI_MEM_WIN_SIZE 0x10000000 |
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| 131 | #define PCI_IO_WIN_BASE 0xf0000000 |
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| 132 | #define PCI_IO_WIN_SIZE 0x00600000 |
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| 133 | |
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| 134 | #define PCI_BUS_MASTER BCHP_PCI_CFG_STATUS_COMMAND_BUS_MASTER_MASK |
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| 135 | #define PCI_IO_ENABLE BCHP_PCI_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK |
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| 136 | #define PCI_MEM_ENABLE BCHP_PCI_CFG_STATUS_COMMAND_IO_SPACE_MASK |
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| 137 | |
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| 138 | #define BCHP_SATA_PHYSICAL_OFFSET 0x10500000 |
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| 139 | #define BCHP_SATA_PCI_BRIDGE_PCI_CTRL 0x204 |
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| 140 | #define PCI_SATA_MEM_ENABLE 1 |
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| 141 | #define PCI_SATA_BUS_MASTER_ENABLE 2 |
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| 142 | #define PCI_SATA_PERR_ENABLE 0x10 |
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| 143 | #define PCI_SATA_SERR_ENABLE 0x20 |
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| 144 | |
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| 145 | |
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| 146 | #define BCHP_PCI_SATA_CFG_SLV_MEMORY_BASE_W0 0x210 |
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| 147 | #define BCHP_PCI_SATA_CFG_SLV_MEMORY_BASE_W0_MODE 0x214 |
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| 148 | #define BCHP_PCI_SATA_CFG_CPU_2_PCI_MEM_WIN0 0x218 |
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| 149 | #define BCHP_PCI_SATA_CFG_CPU_2_PCI_IO_WIN0 0x21c |
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| 150 | #define CPU2PCI_PCI_SATA_PHYS_MEM_WIN0_BASE 0xB0510000 |
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| 151 | #define CPU2PCI_PCI_SATA_PHYS_IO_WIN0_BASE 0xB0520000 |
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| 152 | |
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| 153 | /*****************************************************************************/ |
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| 154 | /* PCI device init */ |
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| 155 | /*****************************************************************************/ |
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| 156 | #define MIPS_PCI_XCFG_INDEX 0xf0600004 |
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| 157 | #define MIPS_PCI_XCFG_DATA 0xf0600008 |
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| 158 | #define PCI_CMD_IO_ENABLE 0x00000001 |
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| 159 | #define PCI_CMD_MEM_ENABLE 0x00000002 |
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| 160 | #define PCI_CMD_MASTER_ENABLE 0x00000004 |
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| 161 | |
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| 162 | #define MIPS_PCI_SATA_XCFG_INDEX 0xB0500208 |
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| 163 | #define MIPS_PCI_SATA_XCFG_DATA 0xB050020c |
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| 164 | /*****************************************************************************/ |
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| 165 | /* MIPS Physical Memory Map */ |
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| 166 | /*****************************************************************************/ |
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| 167 | #define CPU_PHYS_SDRAM_BASE 0x00000000 /* SDRAM Base */ |
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| 168 | #define DRAM_SIZE (256*1024*1024) |
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| 169 | |
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| 170 | /*****************************************************************************/ |
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| 171 | /* MIPS Virtual Memory Map */ |
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| 172 | /*****************************************************************************/ |
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| 173 | #define DRAM_BASE_CACHE PHYS_TO_K0(CPU_PHYS_SDRAM_BASE) /* cached DRAM */ |
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| 174 | |
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| 175 | |
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| 176 | |
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| 177 | #endif |
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