| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2012-2011, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: tlb.s $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/1 $ |
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| 12 | * $brcm_Date: 4/28/11 1:41p $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /rockford/bsp/bcm97358/no-os/src/sde/tlb.s $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/1 4/28/11 1:41p jkim |
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| 21 | * SWCFE-507: Initial file |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/1 11/9/10 4:56p jkim |
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| 24 | * SWCFE-399: initial files |
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| 25 | * |
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| 26 | * Bsp_Software_Devel/7 8/31/10 1:24p rpereira |
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| 27 | * SWCFE-380: Update tlb.s to expand entries used for 3255 from d000_0000 |
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| 28 | * -> d800_0000 to d000_0000 -> e000_0000 |
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| 29 | * |
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| 30 | * Bsp_Software_Devel/6 8/26/10 5:46p rpereira |
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| 31 | * SWCFE-377: Updated pagemask entry as it was incorrect |
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| 32 | * |
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| 33 | * Bsp_Software_Devel/5 8/26/10 5:32p rpereira |
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| 34 | * SWCFE-377: Updated, was writing ENTRYLO0 twice. |
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| 35 | * |
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| 36 | * Bsp_Software_Devel/4 8/26/10 5:04p rpereira |
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| 37 | * SWCFE-377: Updated TLB routines to fix conflict in tlb entries |
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| 38 | * |
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| 39 | * Bsp_Software_Devel/3 5/21/10 11:15a kaushikb |
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| 40 | * SWCFE-311: Fixed #of tlb entries |
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| 41 | * |
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| 42 | * Bsp_Software_Devel/2 9/25/09 1:54p kaushikb |
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| 43 | * SWCFE-239: Updating for 7420 CFE release v2.11 |
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| 44 | * |
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| 45 | * Bsp_Software_Devel/1 3/13/09 10:07a kaushikb |
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| 46 | * PR49990: Adding to src cntrl |
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| 47 | * |
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| 48 | * Hydra_Software_Devel/Bsp_Software_Devel/2 3/11/08 4:38p jkim |
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| 49 | * PR37963: fix compilation warning and error |
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| 50 | * |
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| 51 | * Hydra_Software_Devel/Bsp_Software_Devel/1 10/22/07 4:28p farshidf |
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| 52 | * PR36360: New BSP code |
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| 53 | * |
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| 54 | |
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| 55 | ***************************************************************************/ |
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| 56 | #ifndef __ASSEMBLER__ |
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| 57 | #define __ASSEMBLER__ |
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| 58 | #endif |
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| 59 | |
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| 60 | #include "bmips.h" |
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| 61 | #include "bmips_5xxx.h" |
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| 62 | #include "mips_config.h" |
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| 63 | #include "chipcfg.h" |
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| 64 | #include "boardcfg.h" |
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| 65 | |
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| 66 | #define PM_64MB 0x07ffe000 |
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| 67 | #define OFFS_64MB 0x04000000 |
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| 68 | #define OFFS_128MB 0x08000000 |
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| 69 | |
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| 70 | #define ENTRYLO_UNCACHED(x) ((((x) >> 6) & 0x3fffffc0) | 0x17) |
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| 71 | #define ENTRYLO_CACHED(x) ((((x) >> 6) & 0x3fffffc0) | 0x1f) |
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| 72 | |
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| 73 | .text |
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| 74 | |
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| 75 | #define BARRIER ssnop; ssnop; ssnop |
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| 76 | |
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| 77 | LEAF(init_tlb) |
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| 78 | |
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| 79 | .set noreorder |
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| 80 | |
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| 81 | /********************************************************************* |
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| 82 | * Initialize all TLB entries |
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| 83 | *********************************************************************/ |
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| 84 | /* Set page size to 4KB */ |
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| 85 | mtc0 zero, CP0_PAGE_MASK |
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| 86 | |
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| 87 | /* set all entries to valid=0 with unique kseg0 VAs */ |
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| 88 | li t0, 0x80000000 |
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| 89 | li v0, 0 |
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| 90 | li v1, NUM_TLB_ENTRIES |
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| 91 | li t4, 0 |
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| 92 | |
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| 93 | zero_tlb_loop: |
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| 94 | mtc0 t0, CP0_ENTRY_HI |
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| 95 | mtc0 zero, CP0_ENTRY_LO_0 |
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| 96 | mtc0 zero, CP0_ENTRY_LO_1 |
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| 97 | mtc0 t4, CP0_INDEX |
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| 98 | BARRIER |
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| 99 | tlbwi |
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| 100 | BARRIER |
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| 101 | addi t0,t0,0x2000 |
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| 102 | addi t4,t4,1 |
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| 103 | addi v0,v0,1 |
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| 104 | bne v0,v1,zero_tlb_loop |
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| 105 | nop |
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| 106 | |
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| 107 | |
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| 108 | /* set up 2x 64MB uncached mappings: VA d000_0000 -> PA d000_0000 (PCI2.3 MEM) */ |
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| 109 | |
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| 110 | li t0, PM_64MB |
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| 111 | mtc0 t0, CP0_PAGE_MASK |
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| 112 | li t0, PCI_MEM_WIN_BASE |
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| 113 | mtc0 t0, CP0_ENTRY_HI |
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| 114 | li t0, ENTRYLO_UNCACHED(CPU2PCI_CPU_PHYS_MEM_WIN_BASE) |
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| 115 | mtc0 t0, CP0_ENTRY_LO_0 |
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| 116 | li t0, ENTRYLO_UNCACHED(CPU2PCI_CPU_PHYS_MEM_WIN_BASE + OFFS_64MB) |
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| 117 | mtc0 t0, CP0_ENTRY_LO_1 |
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| 118 | li t0, 1 |
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| 119 | mtc0 t0, CP0_INDEX |
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| 120 | BARRIER |
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| 121 | tlbwi |
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| 122 | BARRIER |
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| 123 | |
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| 124 | /* set up 2x 64MB uncached mappings: VA d800_0000 -> PA d800_0000 (PCI2.3 MEM) */ |
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| 125 | |
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| 126 | li t0, PM_64MB |
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| 127 | mtc0 t0, CP0_PAGE_MASK |
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| 128 | li t0, (PCI_MEM_WIN_BASE + OFFS_128MB) |
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| 129 | mtc0 t0, CP0_ENTRY_HI |
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| 130 | li t0, ENTRYLO_UNCACHED(CPU2PCI_CPU_PHYS_MEM_WIN_BASE + OFFS_128MB) |
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| 131 | mtc0 t0, CP0_ENTRY_LO_0 |
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| 132 | li t0, ENTRYLO_UNCACHED(CPU2PCI_CPU_PHYS_MEM_WIN_BASE + OFFS_128MB + OFFS_64MB) |
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| 133 | mtc0 t0, CP0_ENTRY_LO_1 |
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| 134 | li t0, 2 |
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| 135 | mtc0 t0, CP0_INDEX |
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| 136 | BARRIER |
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| 137 | tlbwi |
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| 138 | BARRIER |
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| 139 | |
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| 140 | /* set up 64MB uncached mapping: VA f000_0000 -> PA f000_0000 (PCI2.3 IO) */ |
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| 141 | |
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| 142 | li t0, PCI_IO_WIN_BASE |
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| 143 | mtc0 t0, CP0_ENTRY_HI |
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| 144 | li t0, ENTRYLO_UNCACHED(PCI_IO_WIN_BASE) |
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| 145 | mtc0 t0, CP0_ENTRY_LO_0 |
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| 146 | mtc0 zero, CP0_ENTRY_LO_1 |
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| 147 | li t0, 3 |
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| 148 | mtc0 t0, CP0_INDEX |
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| 149 | BARRIER |
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| 150 | tlbwi |
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| 151 | BARRIER |
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| 152 | |
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| 153 | li t0, 4 |
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| 154 | mtc0 t0, CP0_WIRED |
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| 155 | |
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| 156 | .set reorder |
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| 157 | jr ra |
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| 158 | nop |
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| 159 | |
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| 160 | END(init_tlb) |
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| 161 | |
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| 162 | LEAF(map_dram1_to_mips) |
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| 163 | |
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| 164 | /* set up 2x 64MB cached mappings: VA e000_0000 -> PA 9000_0000 (MEMC1) */ |
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| 165 | |
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| 166 | li t0, PM_64MB |
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| 167 | mtc0 t0, CP0_PAGE_MASK |
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| 168 | li t0, DRAM_VIRT_ADDR_START |
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| 169 | mtc0 t0, CP0_ENTRY_HI |
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| 170 | li t0, ENTRYLO_CACHED(DRAM_PHYS_ADDR_START) |
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| 171 | mtc0 t0, CP0_ENTRY_LO_0 |
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| 172 | li t0, ENTRYLO_CACHED(DRAM_PHYS_ADDR_START + OFFS_64MB) |
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| 173 | mtc0 t0, CP0_ENTRY_LO_1 |
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| 174 | |
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| 175 | mfc0 t0, CP0_WIRED |
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| 176 | mtc0 t0, CP0_INDEX |
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| 177 | addiu t0, 1 |
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| 178 | mtc0 t0, CP0_WIRED |
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| 179 | BARRIER |
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| 180 | tlbwi |
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| 181 | BARRIER |
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| 182 | |
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| 183 | jr ra |
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| 184 | nop |
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| 185 | |
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| 186 | END(map_dram1_to_mips) |
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| 187 | |
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| 188 | |
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