| 1 | /* |
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| 2 | * header file specific for ddb5476 |
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| 3 | * |
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| 4 | * Copyright (C) 2001 MontaVista Software Inc. |
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| 5 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
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| 6 | * |
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| 7 | * This program is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU General Public License as published by the |
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| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
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| 10 | * option) any later version. |
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| 11 | * |
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| 12 | */ |
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| 13 | |
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| 14 | /* |
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| 15 | * Memory map (physical address) |
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| 16 | * |
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| 17 | * Note most of the following address must be properly aligned by the |
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| 18 | * corresponding size. For example, if PCI_IO_SIZE is 16MB, then |
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| 19 | * PCI_IO_BASE must be aligned along 16MB boundary. |
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| 20 | */ |
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| 21 | #define DDB_SDRAM_BASE 0x00000000 |
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| 22 | #define DDB_SDRAM_SIZE 0x04000000 /* 64MB */ |
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| 23 | |
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| 24 | #define DDB_DCS3_BASE 0x04000000 /* flash 1 */ |
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| 25 | #define DDB_DCS3_SIZE 0x01000000 /* 16MB */ |
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| 26 | |
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| 27 | #define DDB_DCS2_BASE 0x05000000 /* flash 2 */ |
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| 28 | #define DDB_DCS2_SIZE 0x01000000 /* 16MB */ |
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| 29 | |
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| 30 | #define DDB_PCI_IO_BASE 0x06000000 |
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| 31 | #define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */ |
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| 32 | |
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| 33 | #define DDB_PCI_MEM_BASE 0x08000000 |
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| 34 | #define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */ |
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| 35 | |
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| 36 | #define DDB_DCS5_BASE 0x13000000 /* DDB status regs */ |
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| 37 | #define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */ |
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| 38 | |
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| 39 | #define DDB_DCS4_BASE 0x14000000 /* DDB control regs */ |
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| 40 | #define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */ |
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| 41 | |
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| 42 | #define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */ |
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| 43 | #define DDB_INTCS_SIZE 0x00200000 /* 2MB */ |
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| 44 | |
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| 45 | #define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ |
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| 46 | #define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ |
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| 47 | |
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| 48 | |
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| 49 | /* aliases */ |
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| 50 | #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE |
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| 51 | #define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE |
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| 52 | |
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| 53 | /* PCI intr ack share PCIW0 with PCI IO */ |
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| 54 | #define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE |
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| 55 | |
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| 56 | /* |
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| 57 | * Interrupt mapping |
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| 58 | * |
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| 59 | * We have three interrupt controllers: |
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| 60 | * |
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| 61 | * . CPU itself - 8 sources |
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| 62 | * . i8259 - 16 sources |
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| 63 | * . vrc5476 - 16 sources |
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| 64 | * |
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| 65 | * They connected as follows: |
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| 66 | * all vrc5476 interrupts are routed to cpu IP2 (by software setting) |
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| 67 | * all i2869 are routed to INTC in vrc5476 (by hardware connection) |
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| 68 | * |
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| 69 | * All VRC5476 PCI interrupts are level-triggered (no ack needed). |
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| 70 | * All PCI irq but INTC are active low. |
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| 71 | */ |
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| 72 | |
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| 73 | /* |
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| 74 | * irq number block assignment |
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| 75 | */ |
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| 76 | |
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| 77 | #define NUM_CPU_IRQ 8 |
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| 78 | #define NUM_I8259_IRQ 16 |
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| 79 | #define NUM_VRC5476_IRQ 16 |
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| 80 | |
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| 81 | #define DDB_IRQ_BASE 0 |
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| 82 | |
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| 83 | #define I8259_IRQ_BASE DDB_IRQ_BASE |
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| 84 | #define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) |
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| 85 | #define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ) |
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| 86 | |
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| 87 | /* |
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| 88 | * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual |
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| 89 | */ |
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| 90 | |
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| 91 | #define VRC5476_IRQ_CPCE 0 /* cpu parity error */ |
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| 92 | #define VRC5476_IRQ_CNTD 1 /* cpu no target */ |
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| 93 | #define VRC5476_IRQ_MCE 2 /* memory check error */ |
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| 94 | #define VRC5476_IRQ_DMA 3 /* DMA */ |
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| 95 | #define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */ |
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| 96 | #define VRC5476_IRQ_WDOG 5 /* watchdog timer */ |
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| 97 | #define VRC5476_IRQ_GPT 6 /* general purpose timer */ |
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| 98 | #define VRC5476_IRQ_LBRT 7 /* local bus read timeout */ |
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| 99 | #define VRC5476_IRQ_INTA 8 /* PCI INT #A */ |
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| 100 | #define VRC5476_IRQ_INTB 9 /* PCI INT #B */ |
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| 101 | #define VRC5476_IRQ_INTC 10 /* PCI INT #C */ |
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| 102 | #define VRC5476_IRQ_INTD 11 /* PCI INT #D */ |
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| 103 | #define VRC5476_IRQ_INTE 12 /* PCI INT #E */ |
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| 104 | #define VRC5476_IRQ_RESERVED_13 13 /* reserved */ |
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| 105 | #define VRC5476_IRQ_PCIS 14 /* PCI SERR # */ |
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| 106 | #define VRC5476_IRQ_PCI 15 /* PCI internal error */ |
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| 107 | |
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| 108 | /* |
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| 109 | * i2859 irq assignment |
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| 110 | */ |
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| 111 | #define I8259_IRQ_RESERVED_0 0 |
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| 112 | #define I8259_IRQ_KEYBOARD 1 /* M1543 default */ |
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| 113 | #define I8259_IRQ_CASCADE 2 |
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| 114 | #define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */ |
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| 115 | #define I8259_IRQ_UART_A 4 /* M1543 default */ |
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| 116 | #define I8259_IRQ_PARALLEL 5 /* M1543 default */ |
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| 117 | #define I8259_IRQ_RESERVED_6 6 |
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| 118 | #define I8259_IRQ_RESERVED_7 7 |
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| 119 | #define I8259_IRQ_RTC 8 /* who set this? */ |
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| 120 | #define I8259_IRQ_USB 9 /* ddb_setup */ |
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| 121 | #define I8259_IRQ_PMU 10 /* ddb_setup */ |
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| 122 | #define I8259_IRQ_RESERVED_11 11 |
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| 123 | #define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */ |
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| 124 | #define I8259_IRQ_RESERVED_13 13 |
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| 125 | #define I8259_IRQ_HDC1 14 /* default and ddb_setup */ |
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| 126 | #define I8259_IRQ_HDC2 15 /* default */ |
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| 127 | |
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| 128 | |
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| 129 | /* |
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| 130 | * misc |
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| 131 | */ |
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| 132 | #define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC |
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| 133 | #define CPU_VRC5476_CASCADE 2 |
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| 134 | |
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| 135 | #define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ) |
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| 136 | #define nile4_to_irq(n) ((n)+NUM_I8259_IRQ) |
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| 137 | #define irq_to_nile4(n) ((n)-NUM_I8259_IRQ) |
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| 138 | |
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| 139 | /* |
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| 140 | * low-level irq functions |
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| 141 | */ |
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| 142 | #ifndef __ASSEMBLY__ |
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| 143 | extern void nile4_map_irq(int nile4_irq, int cpu_irq); |
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| 144 | extern void nile4_map_irq_all(int cpu_irq); |
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| 145 | extern void nile4_enable_irq(int nile4_irq); |
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| 146 | extern void nile4_disable_irq(int nile4_irq); |
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| 147 | extern void nile4_disable_irq_all(void); |
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| 148 | extern __u16 nile4_get_irq_stat(int cpu_irq); |
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| 149 | extern void nile4_enable_irq_output(int cpu_irq); |
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| 150 | extern void nile4_disable_irq_output(int cpu_irq); |
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| 151 | extern void nile4_set_pci_irq_polarity(int pci_irq, int high); |
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| 152 | extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); |
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| 153 | extern void nile4_clear_irq(int nile4_irq); |
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| 154 | extern void nile4_clear_irq_mask(__u32 mask); |
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| 155 | extern __u8 nile4_i8259_iack(void); |
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| 156 | extern void nile4_dump_irq_status(void); /* Debug */ |
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| 157 | #endif /* !__ASSEMBLY__ */ |
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