| 1 | /* |
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| 2 | * Hardware info about DECstation 5000/2x0 systems (otherwise known as |
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| 3 | * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which |
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| 4 | * differ mechanically but are otherwise identical (both are known as |
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| 5 | * KN03). |
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| 6 | * |
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| 7 | * This file is subject to the terms and conditions of the GNU General Public |
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| 8 | * License. See the file "COPYING" in the main directory of this archive |
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| 9 | * for more details. |
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| 10 | * |
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| 11 | * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions |
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| 12 | * are by courtesy of Chris Fraser. |
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| 13 | * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki |
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| 14 | */ |
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| 15 | #ifndef __ASM_MIPS_DEC_KN03_H |
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| 16 | #define __ASM_MIPS_DEC_KN03_H |
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| 17 | |
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| 18 | #include <asm/addrspace.h> |
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| 19 | #include <asm/dec/ecc.h> |
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| 20 | #include <asm/dec/ioasic_addrs.h> |
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| 21 | |
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| 22 | #define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) |
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| 23 | |
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| 24 | /* |
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| 25 | * Some port addresses... |
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| 26 | */ |
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| 27 | #define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ |
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| 28 | #define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */ |
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| 29 | #define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */ |
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| 30 | |
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| 31 | |
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| 32 | /* |
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| 33 | * CPU interrupt bits. |
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| 34 | */ |
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| 35 | #define KN03_CPU_INR_HALT 6 /* HALT button */ |
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| 36 | #define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ |
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| 37 | #define KN03_CPU_INR_RES_4 4 /* unused */ |
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| 38 | #define KN03_CPU_INR_RTC 3 /* DS1287 RTC */ |
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| 39 | #define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */ |
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| 40 | |
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| 41 | /* |
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| 42 | * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. |
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| 43 | */ |
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| 44 | #define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */ |
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| 45 | #define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ |
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| 46 | #define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */ |
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| 47 | #define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */ |
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| 48 | #define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */ |
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| 49 | #define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ |
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| 50 | #define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ |
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| 51 | #define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ |
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| 52 | #define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ |
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| 53 | #define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ |
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| 54 | #define KN03_IO_INR_RTC 5 /* DS1287 RTC */ |
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| 55 | #define KN03_IO_INR_PSU 4 /* power supply unit warning */ |
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| 56 | #define KN03_IO_INR_RES_3 3 /* unused */ |
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| 57 | #define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ |
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| 58 | #define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */ |
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| 59 | #define KN03_IO_INR_PBNO 0 /* HALT button debouncer */ |
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| 60 | |
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| 61 | |
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| 62 | /* |
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| 63 | * Memory Control Register bits. |
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| 64 | */ |
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| 65 | #define KN03_MCR_RES_16 (0xffff<<16) /* unused */ |
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| 66 | #define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ |
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| 67 | #define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ |
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| 68 | #define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */ |
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| 69 | #define KN03_MCR_RES_11 (0x3<<12) /* unused */ |
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| 70 | #define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */ |
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| 71 | #define KN03_MCR_RES_7 (0x7<<7) /* unused */ |
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| 72 | #define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */ |
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| 73 | |
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| 74 | /* |
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| 75 | * I/O ASIC System Support Register bits. |
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| 76 | */ |
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| 77 | #define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ |
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| 78 | #define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ |
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| 79 | #define KN03_IO_SSR_RES_12 (1<<12) /* unused */ |
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| 80 | |
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| 81 | #define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ |
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| 82 | |
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| 83 | #endif /* __ASM_MIPS_DEC_KN03_H */ |
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