| 1 | /* |
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| 2 | * include/asm-mips/dec/kn05.h |
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| 3 | * |
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| 4 | * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260 |
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| 5 | * definitions. |
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| 6 | * |
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| 7 | * Copyright (C) 2002, 2003 Maciej W. Rozycki |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or |
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| 10 | * modify it under the terms of the GNU General Public License |
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| 11 | * as published by the Free Software Foundation; either version |
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| 12 | * 2 of the License, or (at your option) any later version. |
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| 13 | * |
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| 14 | * WARNING! All this information is pure guesswork based on the |
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| 15 | * ROM. It is provided here in hope it will give someone some |
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| 16 | * food for thought. No documentation for the KN05 module has |
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| 17 | * been located so far. |
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| 18 | */ |
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| 19 | #ifndef __ASM_MIPS_DEC_KN05_H |
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| 20 | #define __ASM_MIPS_DEC_KN05_H |
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| 21 | |
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| 22 | #include <asm/dec/ioasic_addrs.h> |
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| 23 | |
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| 24 | /* |
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| 25 | * The oncard MB (Memory Buffer) ASIC provides an additional address |
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| 26 | * decoder. Certain address ranges within the "high" 16 slots are |
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| 27 | * passed to the I/O ASIC's decoder like with the KN03. Others are |
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| 28 | * handled locally. "Low" slots are always passed. |
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| 29 | */ |
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| 30 | #define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ |
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| 31 | #define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ |
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| 32 | #define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ |
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| 33 | #define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ |
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| 34 | #define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */ |
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| 35 | #define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */ |
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| 36 | #define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */ |
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| 37 | #define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ |
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| 38 | #define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */ |
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| 39 | #define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */ |
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| 40 | #define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */ |
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| 41 | #define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */ |
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| 42 | #define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ |
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| 43 | #define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */ |
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| 44 | #define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */ |
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| 45 | #define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */ |
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| 46 | |
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| 47 | /* |
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| 48 | * Bits for the MB interrupt register. |
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| 49 | * The register appears read-only. |
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| 50 | */ |
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| 51 | #define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ |
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| 52 | #define KN05_MB_INT_RTC (1<<1) /* RTC? */ |
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| 53 | #define KN05_MB_INT_MT (1<<3) /* ??? */ |
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| 54 | |
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| 55 | /* |
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| 56 | * Bits for the MB control & status register. |
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| 57 | * Set to 0x00bf8001 on my system by the ROM. |
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| 58 | */ |
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| 59 | #define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */ |
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| 60 | #define KN05_MB_CSR_F (1<<1) /* ??? */ |
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| 61 | #define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ |
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| 62 | #define KN05_MB_CSR_OD (1<<10) /* ??? */ |
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| 63 | #define KN05_MB_CSR_CP (1<<11) /* ??? */ |
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| 64 | #define KN05_MB_CSR_UNC (1<<12) /* ??? */ |
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| 65 | #define KN05_MB_CSR_IM (1<<13) /* ??? */ |
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| 66 | #define KN05_MB_CSR_NC (1<<14) /* ??? */ |
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| 67 | #define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ |
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| 68 | #define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ |
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| 69 | #define KN05_MB_CSR_FW (1<<21) /* ??? */ |
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| 70 | |
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| 71 | #endif /* __ASM_MIPS_DEC_KN05_H */ |
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