| 1 | /* |
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| 2 | * Copyright 2000 MontaVista Software Inc. |
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| 3 | * Author: MontaVista Software, Inc. |
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| 4 | * stevel@mvista.com or source@mvista.com |
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| 5 | * |
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| 6 | * This program is free software; you can distribute it and/or modify it |
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| 7 | * under the terms of the GNU General Public License (Version 2) as |
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| 8 | * published by the Free Software Foundation. |
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| 9 | * |
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| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 13 | * for more details. |
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| 14 | * |
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| 15 | * You should have received a copy of the GNU General Public License along |
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| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 18 | * |
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| 19 | * Register offsets of the MIPS GT96100 Advanced Communication Controller. |
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| 20 | */ |
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| 21 | #ifndef _GT96100_H |
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| 22 | #define _GT96100_H |
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| 23 | |
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| 24 | /* |
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| 25 | * Galileo GT96100 internal register base. |
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| 26 | */ |
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| 27 | #define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) |
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| 28 | |
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| 29 | #define GT96100_WRITE(ofs, data) \ |
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| 30 | *(volatile __u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) |
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| 31 | #define GT96100_READ(ofs) \ |
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| 32 | le32_to_cpu(*(volatile __u32 *)(MIPS_GT96100_BASE+ofs)) |
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| 33 | |
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| 34 | #define GT96100_ETH_IO_SIZE 0x4000 |
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| 35 | |
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| 36 | /************************************************************************ |
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| 37 | * Register offset addresses follow |
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| 38 | ************************************************************************/ |
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| 39 | |
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| 40 | /* CPU Interface Control Registers */ |
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| 41 | #define GT96100_CPU_INTERF_CONFIG 0x000000 |
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| 42 | |
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| 43 | /* Ethernet Ports */ |
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| 44 | #define GT96100_ETH_PHY_ADDR_REG 0x080800 |
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| 45 | #define GT96100_ETH_SMI_REG 0x080810 |
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| 46 | /* |
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| 47 | These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to |
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| 48 | get offsets to port 1 registers. |
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| 49 | */ |
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| 50 | #define GT96100_ETH_PORT_CONFIG 0x084800 |
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| 51 | #define GT96100_ETH_PORT_CONFIG_EXT 0x084808 |
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| 52 | #define GT96100_ETH_PORT_COMM 0x084810 |
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| 53 | #define GT96100_ETH_PORT_STATUS 0x084818 |
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| 54 | #define GT96100_ETH_SER_PARAM 0x084820 |
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| 55 | #define GT96100_ETH_HASH_TBL_PTR 0x084828 |
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| 56 | #define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 |
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| 57 | #define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 |
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| 58 | #define GT96100_ETH_SDMA_CONFIG 0x084840 |
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| 59 | #define GT96100_ETH_SDMA_COMM 0x084848 |
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| 60 | #define GT96100_ETH_INT_CAUSE 0x084850 |
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| 61 | #define GT96100_ETH_INT_MASK 0x084858 |
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| 62 | #define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 |
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| 63 | #define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 |
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| 64 | #define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 |
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| 65 | #define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C |
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| 66 | #define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 |
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| 67 | #define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 |
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| 68 | #define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 |
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| 69 | #define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC |
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| 70 | #define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 |
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| 71 | #define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 |
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| 72 | #define GT96100_ETH_MIB_COUNT_BASE 0x085800 |
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| 73 | |
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| 74 | /* SDMAs */ |
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| 75 | #define GT96100_SDMA_GROUP_CONFIG 0x101AF0 |
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| 76 | /* SDMA Group 0 */ |
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| 77 | #define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 |
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| 78 | #define GT96100_SDMA_G0_CHAN0_COMM 0x000908 |
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| 79 | #define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 |
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| 80 | #define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 |
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| 81 | #define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 |
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| 82 | #define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 |
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| 83 | #define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 |
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| 84 | #define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 |
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| 85 | #define GT96100_SDMA_G0_CHAN1_COMM 0x010908 |
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| 86 | #define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 |
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| 87 | #define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 |
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| 88 | #define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 |
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| 89 | #define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 |
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| 90 | #define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 |
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| 91 | #define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 |
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| 92 | #define GT96100_SDMA_G0_CHAN2_COMM 0x020908 |
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| 93 | #define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 |
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| 94 | #define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 |
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| 95 | #define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 |
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| 96 | #define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 |
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| 97 | #define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 |
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| 98 | #define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 |
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| 99 | #define GT96100_SDMA_G0_CHAN3_COMM 0x030908 |
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| 100 | #define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 |
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| 101 | #define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 |
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| 102 | #define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 |
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| 103 | #define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 |
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| 104 | #define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 |
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| 105 | #define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 |
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| 106 | #define GT96100_SDMA_G0_CHAN4_COMM 0x040908 |
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| 107 | #define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 |
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| 108 | #define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 |
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| 109 | #define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 |
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| 110 | #define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 |
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| 111 | #define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 |
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| 112 | #define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 |
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| 113 | #define GT96100_SDMA_G0_CHAN5_COMM 0x050908 |
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| 114 | #define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 |
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| 115 | #define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 |
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| 116 | #define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 |
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| 117 | #define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 |
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| 118 | #define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 |
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| 119 | #define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 |
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| 120 | #define GT96100_SDMA_G0_CHAN6_COMM 0x060908 |
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| 121 | #define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 |
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| 122 | #define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 |
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| 123 | #define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 |
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| 124 | #define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 |
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| 125 | #define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 |
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| 126 | #define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 |
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| 127 | #define GT96100_SDMA_G0_CHAN7_COMM 0x070908 |
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| 128 | #define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 |
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| 129 | #define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 |
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| 130 | #define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 |
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| 131 | #define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 |
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| 132 | #define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 |
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| 133 | /* SDMA Group 1 */ |
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| 134 | #define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 |
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| 135 | #define GT96100_SDMA_G1_CHAN0_COMM 0x100908 |
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| 136 | #define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 |
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| 137 | #define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 |
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| 138 | #define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 |
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| 139 | #define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 |
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| 140 | #define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 |
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| 141 | #define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 |
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| 142 | #define GT96100_SDMA_G1_CHAN1_COMM 0x110908 |
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| 143 | #define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 |
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| 144 | #define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 |
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| 145 | #define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 |
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| 146 | #define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 |
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| 147 | #define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 |
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| 148 | #define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 |
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| 149 | #define GT96100_SDMA_G1_CHAN2_COMM 0x120908 |
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| 150 | #define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 |
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| 151 | #define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 |
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| 152 | #define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 |
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| 153 | #define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 |
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| 154 | #define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 |
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| 155 | #define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 |
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| 156 | #define GT96100_SDMA_G1_CHAN3_COMM 0x130908 |
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| 157 | #define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 |
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| 158 | #define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 |
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| 159 | #define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 |
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| 160 | #define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 |
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| 161 | #define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 |
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| 162 | #define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 |
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| 163 | #define GT96100_SDMA_G1_CHAN4_COMM 0x140908 |
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| 164 | #define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 |
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| 165 | #define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 |
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| 166 | #define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 |
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| 167 | #define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 |
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| 168 | #define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 |
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| 169 | #define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 |
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| 170 | #define GT96100_SDMA_G1_CHAN5_COMM 0x150908 |
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| 171 | #define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 |
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| 172 | #define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 |
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| 173 | #define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 |
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| 174 | #define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 |
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| 175 | #define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 |
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| 176 | #define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 |
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| 177 | #define GT96100_SDMA_G1_CHAN6_COMM 0x160908 |
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| 178 | #define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 |
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| 179 | #define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 |
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| 180 | #define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 |
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| 181 | #define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 |
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| 182 | #define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 |
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| 183 | #define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 |
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| 184 | #define GT96100_SDMA_G1_CHAN7_COMM 0x170908 |
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| 185 | #define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 |
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| 186 | #define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 |
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| 187 | #define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 |
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| 188 | #define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 |
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| 189 | #define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 |
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| 190 | /* MPSCs */ |
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| 191 | #define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 |
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| 192 | #define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 |
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| 193 | #define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 |
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| 194 | #define GT96100_MPSC_CHAN0_REG1 0x000A0C |
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| 195 | #define GT96100_MPSC_CHAN0_REG2 0x000A10 |
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| 196 | #define GT96100_MPSC_CHAN0_REG3 0x000A14 |
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| 197 | #define GT96100_MPSC_CHAN0_REG4 0x000A18 |
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| 198 | #define GT96100_MPSC_CHAN0_REG5 0x000A1C |
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| 199 | #define GT96100_MPSC_CHAN0_REG6 0x000A20 |
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| 200 | #define GT96100_MPSC_CHAN0_REG7 0x000A24 |
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| 201 | #define GT96100_MPSC_CHAN0_REG8 0x000A28 |
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| 202 | #define GT96100_MPSC_CHAN0_REG9 0x000A2C |
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| 203 | #define GT96100_MPSC_CHAN0_REG10 0x000A30 |
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| 204 | #define GT96100_MPSC_CHAN0_REG11 0x000A34 |
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| 205 | #define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 |
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| 206 | #define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 |
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| 207 | #define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 |
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| 208 | #define GT96100_MPSC_CHAN1_REG1 0x008A0C |
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| 209 | #define GT96100_MPSC_CHAN1_REG2 0x008A10 |
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| 210 | #define GT96100_MPSC_CHAN1_REG3 0x008A14 |
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| 211 | #define GT96100_MPSC_CHAN1_REG4 0x008A18 |
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| 212 | #define GT96100_MPSC_CHAN1_REG5 0x008A1C |
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| 213 | #define GT96100_MPSC_CHAN1_REG6 0x008A20 |
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| 214 | #define GT96100_MPSC_CHAN1_REG7 0x008A24 |
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| 215 | #define GT96100_MPSC_CHAN1_REG8 0x008A28 |
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| 216 | #define GT96100_MPSC_CHAN1_REG9 0x008A2C |
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| 217 | #define GT96100_MPSC_CHAN1_REG10 0x008A30 |
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| 218 | #define GT96100_MPSC_CHAN1_REG11 0x008A34 |
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| 219 | #define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 |
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| 220 | #define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 |
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| 221 | #define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 |
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| 222 | #define GT96100_MPSC_CHAN2_REG1 0x010A0C |
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| 223 | #define GT96100_MPSC_CHAN2_REG2 0x010A10 |
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| 224 | #define GT96100_MPSC_CHAN2_REG3 0x010A14 |
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| 225 | #define GT96100_MPSC_CHAN2_REG4 0x010A18 |
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| 226 | #define GT96100_MPSC_CHAN2_REG5 0x010A1C |
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| 227 | #define GT96100_MPSC_CHAN2_REG6 0x010A20 |
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| 228 | #define GT96100_MPSC_CHAN2_REG7 0x010A24 |
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| 229 | #define GT96100_MPSC_CHAN2_REG8 0x010A28 |
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| 230 | #define GT96100_MPSC_CHAN2_REG9 0x010A2C |
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| 231 | #define GT96100_MPSC_CHAN2_REG10 0x010A30 |
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| 232 | #define GT96100_MPSC_CHAN2_REG11 0x010A34 |
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| 233 | #define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 |
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| 234 | #define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 |
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| 235 | #define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 |
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| 236 | #define GT96100_MPSC_CHAN3_REG1 0x018A0C |
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| 237 | #define GT96100_MPSC_CHAN3_REG2 0x018A10 |
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| 238 | #define GT96100_MPSC_CHAN3_REG3 0x018A14 |
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| 239 | #define GT96100_MPSC_CHAN3_REG4 0x018A18 |
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| 240 | #define GT96100_MPSC_CHAN3_REG5 0x018A1C |
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| 241 | #define GT96100_MPSC_CHAN3_REG6 0x018A20 |
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| 242 | #define GT96100_MPSC_CHAN3_REG7 0x018A24 |
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| 243 | #define GT96100_MPSC_CHAN3_REG8 0x018A28 |
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| 244 | #define GT96100_MPSC_CHAN3_REG9 0x018A2C |
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| 245 | #define GT96100_MPSC_CHAN3_REG10 0x018A30 |
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| 246 | #define GT96100_MPSC_CHAN3_REG11 0x018A34 |
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| 247 | #define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 |
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| 248 | #define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 |
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| 249 | #define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 |
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| 250 | #define GT96100_MPSC_CHAN4_REG1 0x020A0C |
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| 251 | #define GT96100_MPSC_CHAN4_REG2 0x020A10 |
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| 252 | #define GT96100_MPSC_CHAN4_REG3 0x020A14 |
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| 253 | #define GT96100_MPSC_CHAN4_REG4 0x020A18 |
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| 254 | #define GT96100_MPSC_CHAN4_REG5 0x020A1C |
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| 255 | #define GT96100_MPSC_CHAN4_REG6 0x020A20 |
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| 256 | #define GT96100_MPSC_CHAN4_REG7 0x020A24 |
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| 257 | #define GT96100_MPSC_CHAN4_REG8 0x020A28 |
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| 258 | #define GT96100_MPSC_CHAN4_REG9 0x020A2C |
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| 259 | #define GT96100_MPSC_CHAN4_REG10 0x020A30 |
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| 260 | #define GT96100_MPSC_CHAN4_REG11 0x020A34 |
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| 261 | #define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 |
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| 262 | #define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 |
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| 263 | #define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 |
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| 264 | #define GT96100_MPSC_CHAN5_REG1 0x028A0C |
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| 265 | #define GT96100_MPSC_CHAN5_REG2 0x028A10 |
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| 266 | #define GT96100_MPSC_CHAN5_REG3 0x028A14 |
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| 267 | #define GT96100_MPSC_CHAN5_REG4 0x028A18 |
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| 268 | #define GT96100_MPSC_CHAN5_REG5 0x028A1C |
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| 269 | #define GT96100_MPSC_CHAN5_REG6 0x028A20 |
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| 270 | #define GT96100_MPSC_CHAN5_REG7 0x028A24 |
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| 271 | #define GT96100_MPSC_CHAN5_REG8 0x028A28 |
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| 272 | #define GT96100_MPSC_CHAN5_REG9 0x028A2C |
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| 273 | #define GT96100_MPSC_CHAN5_REG10 0x028A30 |
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| 274 | #define GT96100_MPSC_CHAN5_REG11 0x028A34 |
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| 275 | #define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 |
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| 276 | #define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 |
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| 277 | #define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 |
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| 278 | #define GT96100_MPSC_CHAN6_REG1 0x030A0C |
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| 279 | #define GT96100_MPSC_CHAN6_REG2 0x030A10 |
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| 280 | #define GT96100_MPSC_CHAN6_REG3 0x030A14 |
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| 281 | #define GT96100_MPSC_CHAN6_REG4 0x030A18 |
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| 282 | #define GT96100_MPSC_CHAN6_REG5 0x030A1C |
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| 283 | #define GT96100_MPSC_CHAN6_REG6 0x030A20 |
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| 284 | #define GT96100_MPSC_CHAN6_REG7 0x030A24 |
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| 285 | #define GT96100_MPSC_CHAN6_REG8 0x030A28 |
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| 286 | #define GT96100_MPSC_CHAN6_REG9 0x030A2C |
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| 287 | #define GT96100_MPSC_CHAN6_REG10 0x030A30 |
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| 288 | #define GT96100_MPSC_CHAN6_REG11 0x030A34 |
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| 289 | #define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 |
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| 290 | #define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 |
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| 291 | #define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 |
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| 292 | #define GT96100_MPSC_CHAN7_REG1 0x038A0C |
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| 293 | #define GT96100_MPSC_CHAN7_REG2 0x038A10 |
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| 294 | #define GT96100_MPSC_CHAN7_REG3 0x038A14 |
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| 295 | #define GT96100_MPSC_CHAN7_REG4 0x038A18 |
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| 296 | #define GT96100_MPSC_CHAN7_REG5 0x038A1C |
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| 297 | #define GT96100_MPSC_CHAN7_REG6 0x038A20 |
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| 298 | #define GT96100_MPSC_CHAN7_REG7 0x038A24 |
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| 299 | #define GT96100_MPSC_CHAN7_REG8 0x038A28 |
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| 300 | #define GT96100_MPSC_CHAN7_REG9 0x038A2C |
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| 301 | #define GT96100_MPSC_CHAN7_REG10 0x038A30 |
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| 302 | #define GT96100_MPSC_CHAN7_REG11 0x038A34 |
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| 303 | /* FlexTDMs */ |
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| 304 | /* TDPR0 - Transmit Dual Port RAM. block size 0xff */ |
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| 305 | #define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 |
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| 306 | #define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 |
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| 307 | #define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 |
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| 308 | #define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 |
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| 309 | /* RDPR0 - Receive Dual Port RAM. block size 0xff */ |
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| 310 | #define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 |
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| 311 | #define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 |
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| 312 | #define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 |
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| 313 | #define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 |
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| 314 | #define GT96100_FXTDM0_TX_READ_PTR 0x008B00 |
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| 315 | #define GT96100_FXTDM0_RX_READ_PTR 0x008B04 |
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| 316 | #define GT96100_FXTDM0_CONFIG 0x008B08 |
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| 317 | #define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C |
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| 318 | #define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 |
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| 319 | #define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 |
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| 320 | #define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 |
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| 321 | #define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 |
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| 322 | #define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 |
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| 323 | #define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 |
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| 324 | #define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 |
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| 325 | #define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 |
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| 326 | #define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 |
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| 327 | #define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 |
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| 328 | #define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 |
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| 329 | #define GT96100_FXTDM1_TX_READ_PTR 0x018B00 |
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| 330 | #define GT96100_FXTDM1_RX_READ_PTR 0x018B04 |
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| 331 | #define GT96100_FXTDM1_CONFIG 0x018B08 |
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| 332 | #define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C |
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| 333 | #define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 |
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| 334 | #define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 |
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| 335 | #define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 |
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| 336 | #define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 |
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| 337 | #define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 |
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| 338 | #define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 |
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| 339 | #define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 |
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| 340 | #define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 |
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| 341 | #define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 |
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| 342 | #define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 |
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| 343 | #define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 |
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| 344 | #define GT96100_FLTDM2_TX_READ_PTR 0x028B00 |
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| 345 | #define GT96100_FLTDM2_RX_READ_PTR 0x028B04 |
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| 346 | #define GT96100_FLTDM2_CONFIG 0x028B08 |
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| 347 | #define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C |
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| 348 | #define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 |
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| 349 | #define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 |
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| 350 | #define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 |
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| 351 | #define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 |
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| 352 | #define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 |
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| 353 | #define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 |
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| 354 | #define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 |
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| 355 | #define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 |
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| 356 | #define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 |
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| 357 | #define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 |
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| 358 | #define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 |
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| 359 | #define GT96100_FXTDM3_TX_READ_PTR 0x038B00 |
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| 360 | #define GT96100_FXTDM3_RX_READ_PTR 0x038B04 |
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| 361 | #define GT96100_FXTDM3_CONFIG 0x038B08 |
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| 362 | #define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C |
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| 363 | #define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 |
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| 364 | #define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 |
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| 365 | #define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 |
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| 366 | /* Baud Rate Generators */ |
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| 367 | #define GT96100_BRG0_CONFIG 0x102A00 |
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| 368 | #define GT96100_BRG0_BAUD_TUNE 0x102A04 |
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| 369 | #define GT96100_BRG1_CONFIG 0x102A08 |
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| 370 | #define GT96100_BRG1_BAUD_TUNE 0x102A0C |
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| 371 | #define GT96100_BRG2_CONFIG 0x102A10 |
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| 372 | #define GT96100_BRG2_BAUD_TUNE 0x102A14 |
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| 373 | #define GT96100_BRG3_CONFIG 0x102A18 |
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| 374 | #define GT96100_BRG3_BAUD_TUNE 0x102A1C |
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| 375 | #define GT96100_BRG4_CONFIG 0x102A20 |
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| 376 | #define GT96100_BRG4_BAUD_TUNE 0x102A24 |
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| 377 | #define GT96100_BRG5_CONFIG 0x102A28 |
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| 378 | #define GT96100_BRG5_BAUD_TUNE 0x102A2C |
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| 379 | #define GT96100_BRG6_CONFIG 0x102A30 |
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| 380 | #define GT96100_BRG6_BAUD_TUNE 0x102A34 |
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| 381 | #define GT96100_BRG7_CONFIG 0x102A38 |
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| 382 | #define GT96100_BRG7_BAUD_TUNE 0x102A3C |
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| 383 | /* Routing Registers */ |
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| 384 | #define GT96100_ROUTE_MAIN 0x101A00 |
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| 385 | #define GT96100_ROUTE_RX_CLOCK 0x101A10 |
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| 386 | #define GT96100_ROUTE_TX_CLOCK 0x101A20 |
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| 387 | /* General Purpose Ports */ |
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| 388 | #define GT96100_GPP_CONFIG0 0x100A00 |
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| 389 | #define GT96100_GPP_CONFIG1 0x100A04 |
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| 390 | #define GT96100_GPP_CONFIG2 0x100A08 |
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| 391 | #define GT96100_GPP_CONFIG3 0x100A0C |
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| 392 | #define GT96100_GPP_IO0 0x100A20 |
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| 393 | #define GT96100_GPP_IO1 0x100A24 |
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| 394 | #define GT96100_GPP_IO2 0x100A28 |
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| 395 | #define GT96100_GPP_IO3 0x100A2C |
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| 396 | #define GT96100_GPP_DATA0 0x100A40 |
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| 397 | #define GT96100_GPP_DATA1 0x100A44 |
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| 398 | #define GT96100_GPP_DATA2 0x100A48 |
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| 399 | #define GT96100_GPP_DATA3 0x100A4C |
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| 400 | #define GT96100_GPP_LEVEL0 0x100A60 |
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| 401 | #define GT96100_GPP_LEVEL1 0x100A64 |
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| 402 | #define GT96100_GPP_LEVEL2 0x100A68 |
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| 403 | #define GT96100_GPP_LEVEL3 0x100A6C |
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| 404 | /* Watchdog */ |
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| 405 | #define GT96100_WD_CONFIG 0x101A80 |
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| 406 | #define GT96100_WD_VALUE 0x101A84 |
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| 407 | /* Communication Unit Arbiter */ |
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| 408 | #define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 |
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| 409 | /* PCI Arbiters */ |
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| 410 | #define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 |
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| 411 | #define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 |
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| 412 | /* CIU Arbiter */ |
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| 413 | #define GT96100_CIU_ARBITER_CONFIG 0x101AC0 |
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| 414 | /* Interrupt Controller */ |
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| 415 | #define GT96100_MAIN_CAUSE 0x000C18 |
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| 416 | #define GT96100_INT0_MAIN_MASK 0x000C1C |
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| 417 | #define GT96100_INT1_MAIN_MASK 0x000C24 |
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| 418 | #define GT96100_HIGH_CAUSE 0x000C98 |
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| 419 | #define GT96100_INT0_HIGH_MASK 0x000C9C |
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| 420 | #define GT96100_INT1_HIGH_MASK 0x000CA4 |
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| 421 | #define GT96100_INT0_SELECT 0x000C70 |
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| 422 | #define GT96100_INT1_SELECT 0x000C74 |
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| 423 | #define GT96100_SERIAL_CAUSE 0x103A00 |
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| 424 | #define GT96100_SERINT0_MASK 0x103A80 |
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| 425 | #define GT96100_SERINT1_MASK 0x103A88 |
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| 426 | |
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| 427 | #endif /* _GT96100_H */ |
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