| 1 | /* |
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| 2 | * Carsten Langgaard, carstenl@mips.com |
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| 3 | * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. |
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| 4 | * |
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| 5 | * ######################################################################## |
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| 6 | * |
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| 7 | * This program is free software; you can distribute it and/or modify it |
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| 8 | * under the terms of the GNU General Public License (Version 2) as |
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| 9 | * published by the Free Software Foundation. |
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| 10 | * |
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| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 14 | * for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU General Public License along |
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| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 19 | * |
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| 20 | * ######################################################################## |
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| 21 | * |
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| 22 | * Defines for the Atlas interrupt controller. |
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| 23 | * |
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| 24 | */ |
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| 25 | #ifndef _MIPS_ATLASINT_H |
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| 26 | #define _MIPS_ATLASINT_H |
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| 27 | |
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| 28 | #define ATLASINT_BASE 1 |
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| 29 | #define ATLASINT_UART (ATLASINT_BASE+0) |
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| 30 | #define ATLASINT_TIM0 (ATLASINT_BASE+1) |
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| 31 | #define ATLASINT_RES2 (ATLASINT_BASE+2) |
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| 32 | #define ATLASINT_RES3 (ATLASINT_BASE+3) |
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| 33 | #define ATLASINT_RTC (ATLASINT_BASE+4) |
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| 34 | #define ATLASINT_COREHI (ATLASINT_BASE+5) |
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| 35 | #define ATLASINT_CORELO (ATLASINT_BASE+6) |
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| 36 | #define ATLASINT_RES7 (ATLASINT_BASE+7) |
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| 37 | #define ATLASINT_PCIA (ATLASINT_BASE+8) |
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| 38 | #define ATLASINT_PCIB (ATLASINT_BASE+9) |
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| 39 | #define ATLASINT_PCIC (ATLASINT_BASE+10) |
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| 40 | #define ATLASINT_PCID (ATLASINT_BASE+11) |
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| 41 | #define ATLASINT_ENUM (ATLASINT_BASE+12) |
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| 42 | #define ATLASINT_DEG (ATLASINT_BASE+13) |
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| 43 | #define ATLASINT_ATXFAIL (ATLASINT_BASE+14) |
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| 44 | #define ATLASINT_INTA (ATLASINT_BASE+15) |
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| 45 | #define ATLASINT_INTB (ATLASINT_BASE+16) |
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| 46 | #define ATLASINT_ETH ATLASINT_INTB |
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| 47 | #define ATLASINT_INTC (ATLASINT_BASE+17) |
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| 48 | #define ATLASINT_SCSI ATLASINT_INTC |
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| 49 | #define ATLASINT_INTD (ATLASINT_BASE+18) |
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| 50 | #define ATLASINT_SERR (ATLASINT_BASE+19) |
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| 51 | #define ATLASINT_RES20 (ATLASINT_BASE+20) |
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| 52 | #define ATLASINT_RES21 (ATLASINT_BASE+21) |
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| 53 | #define ATLASINT_RES22 (ATLASINT_BASE+22) |
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| 54 | #define ATLASINT_RES23 (ATLASINT_BASE+23) |
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| 55 | #define ATLASINT_RES24 (ATLASINT_BASE+24) |
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| 56 | #define ATLASINT_RES25 (ATLASINT_BASE+25) |
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| 57 | #define ATLASINT_RES26 (ATLASINT_BASE+26) |
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| 58 | #define ATLASINT_RES27 (ATLASINT_BASE+27) |
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| 59 | #define ATLASINT_RES28 (ATLASINT_BASE+28) |
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| 60 | #define ATLASINT_RES29 (ATLASINT_BASE+29) |
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| 61 | #define ATLASINT_RES30 (ATLASINT_BASE+30) |
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| 62 | #define ATLASINT_RES31 (ATLASINT_BASE+31) |
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| 63 | #define ATLASINT_END (ATLASINT_BASE+31) |
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| 64 | |
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| 65 | /* |
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| 66 | * Atlas registers are memory mapped on 64-bit aligned boundaries and |
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| 67 | * only word access are allowed. |
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| 68 | */ |
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| 69 | struct atlas_ictrl_regs { |
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| 70 | volatile unsigned int intraw; |
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| 71 | int dummy1; |
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| 72 | volatile unsigned int intseten; |
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| 73 | int dummy2; |
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| 74 | volatile unsigned int intrsten; |
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| 75 | int dummy3; |
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| 76 | volatile unsigned int intenable; |
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| 77 | int dummy4; |
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| 78 | volatile unsigned int intstatus; |
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| 79 | int dummy5; |
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| 80 | }; |
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| 81 | |
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| 82 | extern void atlasint_init(void); |
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| 83 | |
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| 84 | #endif /* !(_MIPS_ATLASINT_H) */ |
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