| 1 | /* |
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| 2 | * Carsten Langgaard, carstenl@mips.com |
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| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
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| 4 | * |
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| 5 | * This program is free software; you can distribute it and/or modify it |
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| 6 | * under the terms of the GNU General Public License (Version 2) as |
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| 7 | * published by the Free Software Foundation. |
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| 8 | * |
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| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 12 | * for more details. |
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| 13 | * |
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| 14 | * You should have received a copy of the GNU General Public License along |
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| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 17 | * |
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| 18 | * Defines of the MIPS boards specific address-MAP, registers, etc. |
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| 19 | */ |
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| 20 | #ifndef __ASM_MIPS_BOARDS_GENERIC_H |
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| 21 | #define __ASM_MIPS_BOARDS_GENERIC_H |
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| 22 | |
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| 23 | #include <asm/addrspace.h> |
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| 24 | #include <asm/byteorder.h> |
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| 25 | #include <asm/mips-boards/bonito64.h> |
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| 26 | |
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| 27 | /* |
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| 28 | * Display register base. |
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| 29 | */ |
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| 30 | #ifdef CONFIG_MIPS_SEAD |
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| 31 | #define ASCII_DISPLAY_POS_BASE 0x1f0005c0 |
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| 32 | #else |
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| 33 | #define ASCII_DISPLAY_WORD_BASE 0x1f000410 |
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| 34 | #define ASCII_DISPLAY_POS_BASE 0x1f000418 |
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| 35 | #endif |
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| 36 | |
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| 37 | |
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| 38 | /* |
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| 39 | * Yamon Prom print address. |
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| 40 | */ |
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| 41 | #define YAMON_PROM_PRINT_ADDR 0x1fc00504 |
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| 42 | |
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| 43 | |
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| 44 | /* |
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| 45 | * Reset register. |
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| 46 | */ |
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| 47 | #ifdef CONFIG_MIPS_SEAD |
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| 48 | #define SOFTRES_REG 0x1e800050 |
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| 49 | #define GORESET 0x4d |
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| 50 | #else |
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| 51 | #define SOFTRES_REG 0x1f000500 |
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| 52 | #define GORESET 0x42 |
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| 53 | #endif |
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| 54 | |
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| 55 | /* |
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| 56 | * Revision register. |
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| 57 | */ |
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| 58 | #define MIPS_REVISION_REG 0x1fc00010 |
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| 59 | #define MIPS_REVISION_CORID_QED_RM5261 0 |
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| 60 | #define MIPS_REVISION_CORID_CORE_LV 1 |
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| 61 | #define MIPS_REVISION_CORID_BONITO64 2 |
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| 62 | #define MIPS_REVISION_CORID_CORE_20K 3 |
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| 63 | #define MIPS_REVISION_CORID_CORE_FPGA 4 |
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| 64 | #define MIPS_REVISION_CORID_CORE_MSC 5 |
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| 65 | #define MIPS_REVISION_CORID_CORE_EMUL 6 |
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| 66 | #define MIPS_REVISION_CORID_CORE_FPGA2 7 |
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| 67 | #define MIPS_REVISION_CORID_CORE_FPGAR2 8 |
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| 68 | |
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| 69 | /**** Artificial corid defines ****/ |
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| 70 | /* |
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| 71 | * CoreEMUL with Bonito System Controller is treated like a Core20K |
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| 72 | * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC |
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| 73 | */ |
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| 74 | #define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 |
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| 75 | #define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 |
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| 76 | |
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| 77 | #define MIPS_REVISION_CORID (((*(volatile __u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) |
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| 78 | |
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| 79 | extern unsigned int mips_revision_corid; |
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| 80 | |
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| 81 | #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ |
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