| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * ip22.h: Definitions for SGI IP22 machines |
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| 7 | * |
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| 8 | * Copyright (C) 1996 David S. Miller |
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| 9 | * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _SGI_IP22_H |
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| 13 | #define _SGI_IP22_H |
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| 14 | |
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| 15 | /* |
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| 16 | * These are the virtual IRQ numbers, we divide all IRQ's into |
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| 17 | * 'spaces', the 'space' determines where and how to enable/disable |
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| 18 | * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups |
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| 19 | * are not supported this way. Driver is supposed to allocate HPC/MC |
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| 20 | * interrupt as shareable and then look to proper status bit (see |
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| 21 | * HAL2 driver). This will prevent many complications, trust me ;-) |
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| 22 | */ |
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| 23 | |
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| 24 | #include <asm/sgi/ioc.h> |
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| 25 | |
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| 26 | #define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ |
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| 27 | #define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */ |
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| 28 | #define SGINT_LOCAL0 24 /* 8 local0 irq levels */ |
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| 29 | #define SGINT_LOCAL1 32 /* 8 local1 irq levels */ |
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| 30 | #define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */ |
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| 31 | #define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */ |
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| 32 | #define SGINT_END 56 /* End of 'spaces' */ |
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| 33 | |
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| 34 | /* |
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| 35 | * Individual interrupt definitions for the Indy and Indigo2 |
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| 36 | */ |
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| 37 | |
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| 38 | #define SGI_SOFT_0_IRQ SGINT_CPU + 0 |
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| 39 | #define SGI_SOFT_1_IRQ SGINT_CPU + 1 |
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| 40 | #define SGI_LOCAL_0_IRQ SGINT_CPU + 2 |
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| 41 | #define SGI_LOCAL_1_IRQ SGINT_CPU + 3 |
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| 42 | #define SGI_8254_0_IRQ SGINT_CPU + 4 |
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| 43 | #define SGI_8254_1_IRQ SGINT_CPU + 5 |
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| 44 | #define SGI_BUSERR_IRQ SGINT_CPU + 6 |
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| 45 | #define SGI_TIMER_IRQ SGINT_CPU + 7 |
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| 46 | |
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| 47 | #define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */ |
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| 48 | #define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */ |
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| 49 | #define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ |
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| 50 | #define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ |
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| 51 | #define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ |
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| 52 | #define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ |
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| 53 | #define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ |
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| 54 | #define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ |
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| 55 | #define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ |
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| 56 | |
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| 57 | #define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */ |
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| 58 | #define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ |
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| 59 | #define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */ |
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| 60 | #define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */ |
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| 61 | #define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */ |
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| 62 | #define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */ |
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| 63 | #define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ |
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| 64 | #define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */ |
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| 65 | |
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| 66 | /* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */ |
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| 67 | #define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */ |
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| 68 | #define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ |
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| 69 | #define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ |
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| 70 | #define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ |
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| 71 | |
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| 72 | #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) |
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| 73 | |
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| 74 | extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg); |
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| 75 | extern unsigned short ip22_nvram_read(int reg); |
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| 76 | |
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| 77 | #endif |
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