| 1 | /* |
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| 2 | * Lowlevel hardware stuff for the MIPS based Cobalt microservers. |
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| 3 | * |
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| 4 | * This file is subject to the terms and conditions of the GNU General Public |
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| 5 | * License. See the file "COPYING" in the main directory of this archive |
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| 6 | * for more details. |
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| 7 | * |
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| 8 | * Copyright (C) 1997 Cobalt Microserver |
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| 9 | * Copyright (C) 1997, 2003 Ralf Baechle |
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| 10 | * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) |
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| 11 | */ |
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| 12 | #ifndef __ASM_COBALT_H |
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| 13 | #define __ASM_COBALT_H |
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| 14 | |
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| 15 | /* |
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| 16 | * i8259 legacy interrupts used on Cobalt: |
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| 17 | * |
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| 18 | * 8 - RTC |
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| 19 | * 9 - PCI |
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| 20 | * 14 - IDE0 |
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| 21 | * 15 - IDE1 |
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| 22 | * |
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| 23 | * CPU IRQs are 16 ... 23 |
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| 24 | */ |
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| 25 | #define COBALT_TIMER_IRQ 18 |
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| 26 | #define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */ |
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| 27 | #define COBALT_RAQ_SCSI_IRQ 19 |
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| 28 | #define COBALT_ETH0_IRQ 19 |
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| 29 | #define COBALT_ETH1_IRQ 20 |
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| 30 | #define COBALT_SERIAL_IRQ 21 |
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| 31 | #define COBALT_SCSI_IRQ 21 |
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| 32 | #define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */ |
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| 33 | #define COBALT_QUBE_SLOT_IRQ 23 |
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| 34 | |
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| 35 | /* |
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| 36 | * PCI configuration space manifest constants. These are wired into |
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| 37 | * the board layout according to the PCI spec to enable the software |
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| 38 | * to probe the hardware configuration space in a well defined manner. |
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| 39 | * |
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| 40 | * The PCI_DEVSHFT() macro transforms these values into numbers |
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| 41 | * suitable for passing as the dev parameter to the various |
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| 42 | * pcibios_read/write_config routines. |
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| 43 | */ |
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| 44 | #define COBALT_PCICONF_CPU 0x06 |
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| 45 | #define COBALT_PCICONF_ETH0 0x07 |
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| 46 | #define COBALT_PCICONF_RAQSCSI 0x08 |
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| 47 | #define COBALT_PCICONF_VIA 0x09 |
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| 48 | #define COBALT_PCICONF_PCISLOT 0x0A |
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| 49 | #define COBALT_PCICONF_ETH1 0x0C |
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| 50 | |
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| 51 | |
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| 52 | /* |
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| 53 | * The Cobalt board id information. The boards have an ID number wired |
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| 54 | * into the VIA that is available in the high nibble of register 94. |
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| 55 | * This register is available in the VIA configuration space through the |
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| 56 | * interface routines qube_pcibios_read/write_config. See cobalt/pci.c |
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| 57 | */ |
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| 58 | #define VIA_COBALT_BRD_ID_REG 0x94 |
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| 59 | #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) |
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| 60 | #define COBALT_BRD_ID_QUBE1 0x3 |
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| 61 | #define COBALT_BRD_ID_RAQ1 0x4 |
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| 62 | #define COBALT_BRD_ID_QUBE2 0x5 |
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| 63 | #define COBALT_BRD_ID_RAQ2 0x6 |
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| 64 | |
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| 65 | /* |
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| 66 | * Galileo chipset access macros for the Cobalt. The base address for |
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| 67 | * the GT64111 chip is 0x14000000 |
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| 68 | * |
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| 69 | * Most of this really should go into a separate GT64111 header file. |
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| 70 | */ |
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| 71 | #define GT64111_IO_BASE 0x10000000UL |
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| 72 | #define GT64111_BASE 0x14000000UL |
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| 73 | #define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs)) |
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| 74 | |
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| 75 | #define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) |
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| 76 | #define GALILEO_OUTL(val, port) \ |
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| 77 | do { \ |
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| 78 | *(volatile unsigned int *) GALILEO_REG(port) = (port); \ |
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| 79 | } while (0) |
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| 80 | |
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| 81 | #define GALILEO_T0EXP 0x0100 |
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| 82 | #define GALILEO_ENTC0 0x01 |
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| 83 | #define GALILEO_SELTC0 0x02 |
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| 84 | |
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| 85 | #define PCI_CFG_SET(devfn,where) \ |
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| 86 | GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ |
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| 87 | (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) |
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| 88 | |
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| 89 | |
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| 90 | #endif /* __ASM_COBALT_H */ |
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