| 1 | /* |
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| 2 | * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory |
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| 3 | * Engine) |
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| 4 | * |
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| 5 | * This file is subject to the terms and conditions of the GNU General Public |
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| 6 | * License. See the file "COPYING" in the main directory of this archive |
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| 7 | * for more details. |
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| 8 | * |
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| 9 | * Copyright (C) 2000 Harald Koerfgen |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __ASM_CRIME_H__ |
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| 13 | #define __ASM_CRIME_H__ |
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| 14 | |
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| 15 | /* |
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| 16 | * Address map |
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| 17 | */ |
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| 18 | #define CRIME_BASE 0x14000000 /* physical */ |
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| 19 | |
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| 20 | #undef BIT |
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| 21 | #define BIT(x) (1UL << (x)) |
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| 22 | |
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| 23 | struct sgi_crime { |
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| 24 | volatile unsigned long id; |
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| 25 | #define CRIME_ID_MASK 0xff |
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| 26 | #define CRIME_ID_IDBITS 0xf0 |
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| 27 | #define CRIME_ID_IDVALUE 0xa0 |
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| 28 | #define CRIME_ID_REV 0x0f |
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| 29 | #define CRIME_REV_PETTY 0x00 |
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| 30 | #define CRIME_REV_11 0x11 |
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| 31 | #define CRIME_REV_13 0x13 |
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| 32 | #define CRIME_REV_14 0x14 |
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| 33 | |
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| 34 | volatile unsigned long control; |
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| 35 | #define CRIME_CONTROL_MASK 0x3fff |
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| 36 | #define CRIME_CONTROL_TRITON_SYSADC 0x2000 |
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| 37 | #define CRIME_CONTROL_CRIME_SYSADC 0x1000 |
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| 38 | #define CRIME_CONTROL_HARD_RESET 0x0800 |
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| 39 | #define CRIME_CONTROL_SOFT_RESET 0x0400 |
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| 40 | #define CRIME_CONTROL_DOG_ENA 0x0200 |
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| 41 | #define CRIME_CONTROL_ENDIANESS 0x0100 |
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| 42 | #define CRIME_CONTROL_ENDIAN_BIG 0x0100 |
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| 43 | #define CRIME_CONTROL_ENDIAN_LITTLE 0x0000 |
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| 44 | #define CRIME_CONTROL_CQUEUE_HWM 0x000f |
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| 45 | #define CRIME_CONTROL_CQUEUE_SHFT 0 |
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| 46 | #define CRIME_CONTROL_WBUF_HWM 0x00f0 |
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| 47 | #define CRIME_CONTROL_WBUF_SHFT 8 |
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| 48 | |
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| 49 | volatile unsigned long istat; |
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| 50 | volatile unsigned long imask; |
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| 51 | volatile unsigned long soft_int; |
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| 52 | volatile unsigned long hard_int; |
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| 53 | #define MACE_VID_IN1_INT BIT(0) |
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| 54 | #define MACE_VID_IN2_INT BIT(1) |
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| 55 | #define MACE_VID_OUT_INT BIT(2) |
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| 56 | #define MACE_ETHERNET_INT BIT(3) |
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| 57 | #define MACE_SUPERIO_INT BIT(4) |
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| 58 | #define MACE_MISC_INT BIT(5) |
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| 59 | #define MACE_AUDIO_INT BIT(6) |
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| 60 | #define MACE_PCI_BRIDGE_INT BIT(7) |
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| 61 | #define MACEPCI_SCSI0_INT BIT(8) |
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| 62 | #define MACEPCI_SCSI1_INT BIT(9) |
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| 63 | #define MACEPCI_SLOT0_INT BIT(10) |
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| 64 | #define MACEPCI_SLOT1_INT BIT(11) |
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| 65 | #define MACEPCI_SLOT2_INT BIT(12) |
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| 66 | #define MACEPCI_SHARED0_INT BIT(13) |
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| 67 | #define MACEPCI_SHARED1_INT BIT(14) |
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| 68 | #define MACEPCI_SHARED2_INT BIT(15) |
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| 69 | #define CRIME_GBE0_INT BIT(16) |
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| 70 | #define CRIME_GBE1_INT BIT(17) |
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| 71 | #define CRIME_GBE2_INT BIT(18) |
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| 72 | #define CRIME_GBE3_INT BIT(19) |
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| 73 | #define CRIME_CPUERR_INT BIT(20) |
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| 74 | #define CRIME_MEMERR_INT BIT(21) |
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| 75 | #define CRIME_RE_EMPTY_E_INT BIT(22) |
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| 76 | #define CRIME_RE_FULL_E_INT BIT(23) |
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| 77 | #define CRIME_RE_IDLE_E_INT BIT(24) |
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| 78 | #define CRIME_RE_EMPTY_L_INT BIT(25) |
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| 79 | #define CRIME_RE_FULL_L_INT BIT(26) |
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| 80 | #define CRIME_RE_IDLE_L_INT BIT(27) |
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| 81 | #define CRIME_SOFT0_INT BIT(28) |
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| 82 | #define CRIME_SOFT1_INT BIT(29) |
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| 83 | #define CRIME_SOFT2_INT BIT(30) |
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| 84 | #define CRIME_SYSCORERR_INT CRIME_SOFT2_INT |
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| 85 | #define CRIME_VICE_INT BIT(31) |
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| 86 | /* Masks for deciding who handles the interrupt */ |
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| 87 | #define CRIME_MACE_INT_MASK 0x8f |
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| 88 | #define CRIME_MACEISA_INT_MASK 0x70 |
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| 89 | #define CRIME_MACEPCI_INT_MASK 0xff00 |
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| 90 | #define CRIME_CRIME_INT_MASK 0xffff0000 |
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| 91 | |
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| 92 | volatile unsigned long watchdog; |
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| 93 | #define CRIME_DOG_POWER_ON_RESET 0x00010000 |
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| 94 | #define CRIME_DOG_WARM_RESET 0x00080000 |
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| 95 | #define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET) |
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| 96 | #define CRIME_DOG_VALUE 0x00007fff |
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| 97 | |
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| 98 | volatile unsigned long timer; |
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| 99 | #define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */ |
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| 100 | #define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ |
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| 101 | |
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| 102 | volatile unsigned long cpu_error_addr; |
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| 103 | #define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff |
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| 104 | |
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| 105 | volatile unsigned long cpu_error_stat; |
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| 106 | #define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */ |
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| 107 | #define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4 |
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| 108 | #define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2 |
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| 109 | #define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1 |
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| 110 | |
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| 111 | unsigned long _pad0[54]; |
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| 112 | |
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| 113 | volatile unsigned long mc_ctrl; |
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| 114 | volatile unsigned long bank_ctrl[8]; |
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| 115 | #define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */ |
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| 116 | #define CRIME_MEM_BANK_CONTROL_ADDR 0x01f |
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| 117 | #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100 |
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| 118 | #define CRIME_MAXBANKS 8 |
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| 119 | |
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| 120 | volatile unsigned long mem_ref_counter; |
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| 121 | #define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ |
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| 122 | |
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| 123 | volatile unsigned long mem_error_stat; |
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| 124 | #define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ |
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| 125 | #define CRIME_MEM_ERROR_MACE_ID 0x0000007f |
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| 126 | #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 |
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| 127 | #define CRIME_MEM_ERROR_RE_ID 0x00007f00 |
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| 128 | #define CRIME_MEM_ERROR_RE_ACCESS 0x00008000 |
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| 129 | #define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000 |
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| 130 | #define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000 |
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| 131 | #define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000 |
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| 132 | #define CRIME_MEM_ERROR_RESERVED 0x00080000 |
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| 133 | #define CRIME_MEM_ERROR_SOFT_ERR 0x00100000 |
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| 134 | #define CRIME_MEM_ERROR_HARD_ERR 0x00200000 |
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| 135 | #define CRIME_MEM_ERROR_MULTIPLE 0x00400000 |
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| 136 | #define CRIME_MEM_ERROR_ECC 0x01800000 |
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| 137 | #define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 |
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| 138 | #define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 |
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| 139 | #define CRIME_MEM_ERROR_INV 0x0e000000 |
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| 140 | #define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 |
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| 141 | #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 |
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| 142 | #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 |
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| 143 | |
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| 144 | volatile unsigned long mem_error_addr; |
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| 145 | #define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff |
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| 146 | |
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| 147 | volatile unsigned long mem_ecc_syn; |
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| 148 | #define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff |
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| 149 | |
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| 150 | volatile unsigned long mem_ecc_chk; |
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| 151 | #define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff |
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| 152 | |
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| 153 | volatile unsigned long mem_ecc_repl; |
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| 154 | #define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff |
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| 155 | }; |
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| 156 | |
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| 157 | extern struct sgi_crime *crime; |
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| 158 | |
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| 159 | #define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */ |
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| 160 | |
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| 161 | #endif /* __ASM_CRIME_H__ */ |
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