| 1 | /* |
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| 2 | * Carsten Langgaard, carstenl@mips.com |
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| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
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| 4 | * |
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| 5 | * This program is free software; you can distribute it and/or modify it |
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| 6 | * under the terms of the GNU General Public License (Version 2) as |
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| 7 | * published by the Free Software Foundation. |
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| 8 | * |
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| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 12 | * for more details. |
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| 13 | * |
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| 14 | * You should have received a copy of the GNU General Public License along |
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| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 17 | * |
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| 18 | * Defines of the Malta board specific address-MAP, registers, etc. |
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| 19 | */ |
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| 20 | #ifndef __ASM_MIPS_BOARDS_MALTA_H |
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| 21 | #define __ASM_MIPS_BOARDS_MALTA_H |
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| 22 | |
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| 23 | #include <asm/addrspace.h> |
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| 24 | #include <asm/io.h> |
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| 25 | #include <asm/mips-boards/msc01_pci.h> |
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| 26 | #include <asm/gt64120.h> |
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| 27 | |
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| 28 | /* |
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| 29 | * Malta I/O ports base address for the Galileo GT64120 and Algorithmics |
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| 30 | * Bonito system controllers. |
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| 31 | */ |
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| 32 | #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) |
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| 33 | #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) |
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| 34 | #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) |
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| 35 | |
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| 36 | static inline unsigned long get_gt_port_base(unsigned long reg) |
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| 37 | { |
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| 38 | unsigned long addr; |
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| 39 | addr = GT_READ(reg); |
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| 40 | return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); |
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| 41 | } |
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| 42 | |
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| 43 | static inline unsigned long get_msc_port_base(unsigned long reg) |
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| 44 | { |
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| 45 | unsigned long addr; |
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| 46 | MSC_READ(reg, addr); |
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| 47 | return (unsigned long) ioremap(addr, 0x10000); |
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| 48 | } |
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| 49 | |
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| 50 | /* |
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| 51 | * Malta RTC-device indirect register access. |
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| 52 | */ |
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| 53 | #define MALTA_RTC_ADR_REG 0x70 |
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| 54 | #define MALTA_RTC_DAT_REG 0x71 |
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| 55 | |
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| 56 | /* |
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| 57 | * Malta SMSC FDC37M817 Super I/O Controller register. |
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| 58 | */ |
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| 59 | #define SMSC_CONFIG_REG 0x3f0 |
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| 60 | #define SMSC_DATA_REG 0x3f1 |
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| 61 | |
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| 62 | #define SMSC_CONFIG_DEVNUM 0x7 |
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| 63 | #define SMSC_CONFIG_ACTIVATE 0x30 |
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| 64 | #define SMSC_CONFIG_ENTER 0x55 |
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| 65 | #define SMSC_CONFIG_EXIT 0xaa |
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| 66 | |
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| 67 | #define SMSC_CONFIG_DEVNUM_FLOPPY 0 |
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| 68 | |
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| 69 | #define SMSC_CONFIG_ACTIVATE_ENABLE 1 |
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| 70 | |
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| 71 | #define SMSC_WRITE(x,a) outb(x,a) |
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| 72 | |
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| 73 | #define MALTA_JMPRS_REG 0x1f000210 |
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| 74 | |
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| 75 | #endif /* __ASM_MIPS_BOARDS_MALTA_H */ |
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