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bridge.h @ 74

Last change on this file since 74 was 74, checked in by phkim, 10 years ago
phkim zasc 변경 내용 CT_ChMapUpdatePMTAC3AudioDescriptor 메모리 leak 버그 수정
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1	/*
2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.
5	*
6	* bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
7	* revision 1.76.
8	*
9	* Copyright (C) 1996, 1999 Silcon Graphics, Inc.
10	* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
11	*/
12	#ifndef _ASM_PCI_BRIDGE_H
13	#define _ASM_PCI_BRIDGE_H
14
15	#include <linux/types.h>
16	#include <linux/pci.h>
17	#include <asm/xtalk/xwidget.h> /* generic widget header */
18
19	/* I/O page size */
20
21	#define IOPFNSHIFT 12 /* 4K per mapped page */
22
23	#define IOPGSIZE (1 << IOPFNSHIFT)
24	#define IOPG(x) ((x) >> IOPFNSHIFT)
25	#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
26
27	/* Bridge RAM sizes */
28
29	#define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */
30
31	#define BRIDGE_CONFIG_BASE 0x20000
32	#define BRIDGE_CONFIG1_BASE 0x28000
33	#define BRIDGE_CONFIG_END 0x30000
34	#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
35
36	#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
37	#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
38	#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
39	#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
40
41	/* ========================================================================
42	* Bridge address map
43	*/
44
45	#ifndef __ASSEMBLY__
46
47	/*
48	* All accesses to bridge hardware registers must be done
49	* using 32-bit loads and stores.
50	*/
51	typedef __u32 bridgereg_t;
52
53	typedef __u64 bridge_ate_t;
54
55	/* pointers to bridge ATEs
56	* are always "pointer to volatile"
57	*/
58	typedef volatile bridge_ate_t *bridge_ate_p;
59
60	/*
61	* It is generally preferred that hardware registers on the bridge
62	* are located from C code via this structure.
63	*
64	* Generated from Bridge spec dated 04oct95
65	*/
66
67	typedef volatile struct bridge_s {
68	/* Local Registers 0x000000-0x00FFFF */
69
70	/* standard widget configuration 0x000000-0x000057 */
71	widget_cfg_t b_widget; /* 0x000000 */
72
73	/* helper fieldnames for accessing bridge widget */
74
75	#define b_wid_id b_widget.w_id
76	#define b_wid_stat b_widget.w_status
77	#define b_wid_err_upper b_widget.w_err_upper_addr
78	#define b_wid_err_lower b_widget.w_err_lower_addr
79	#define b_wid_control b_widget.w_control
80	#define b_wid_req_timeout b_widget.w_req_timeout
81	#define b_wid_int_upper b_widget.w_intdest_upper_addr
82	#define b_wid_int_lower b_widget.w_intdest_lower_addr
83	#define b_wid_err_cmdword b_widget.w_err_cmd_word
84	#define b_wid_llp b_widget.w_llp_cfg
85	#define b_wid_tflush b_widget.w_tflush
86
87	/* bridge-specific widget configuration 0x000058-0x00007F */
88	bridgereg_t _pad_000058;
89	bridgereg_t b_wid_aux_err; /* 0x00005C */
90	bridgereg_t _pad_000060;
91	bridgereg_t b_wid_resp_upper; /* 0x000064 */
92	bridgereg_t _pad_000068;
93	bridgereg_t b_wid_resp_lower; /* 0x00006C */
94	bridgereg_t _pad_000070;
95	bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
96	bridgereg_t _pad_000078[2];
97
98	/* PMU & Map 0x000080-0x00008F */
99	bridgereg_t _pad_000080;
100	bridgereg_t b_dir_map; /* 0x000084 */
101	bridgereg_t _pad_000088[2];
102
103	/* SSRAM 0x000090-0x00009F */
104	bridgereg_t _pad_000090;
105	bridgereg_t b_ram_perr; /* 0x000094 */
106	bridgereg_t _pad_000098[2];
107
108	/* Arbitration 0x0000A0-0x0000AF */
109	bridgereg_t _pad_0000A0;
110	bridgereg_t b_arb; /* 0x0000A4 */
111	bridgereg_t _pad_0000A8[2];
112
113	/* Number In A Can 0x0000B0-0x0000BF */
114	bridgereg_t _pad_0000B0;
115	bridgereg_t b_nic; /* 0x0000B4 */
116	bridgereg_t _pad_0000B8[2];
117
118	/* PCI/GIO 0x0000C0-0x0000FF */
119	bridgereg_t _pad_0000C0;
120	bridgereg_t b_bus_timeout; /* 0x0000C4 */
121	#define b_pci_bus_timeout b_bus_timeout
122
123	bridgereg_t _pad_0000C8;
124	bridgereg_t b_pci_cfg; /* 0x0000CC */
125	bridgereg_t _pad_0000D0;
126	bridgereg_t b_pci_err_upper; /* 0x0000D4 */
127	bridgereg_t _pad_0000D8;
128	bridgereg_t b_pci_err_lower; /* 0x0000DC */
129	bridgereg_t _pad_0000E0[8];
130	#define b_gio_err_lower b_pci_err_lower
131	#define b_gio_err_upper b_pci_err_upper
132
133	/* Interrupt 0x000100-0x0001FF */
134	bridgereg_t _pad_000100;
135	bridgereg_t b_int_status; /* 0x000104 */
136	bridgereg_t _pad_000108;
137	bridgereg_t b_int_enable; /* 0x00010C */
138	bridgereg_t _pad_000110;
139	bridgereg_t b_int_rst_stat; /* 0x000114 */
140	bridgereg_t _pad_000118;
141	bridgereg_t b_int_mode; /* 0x00011C */
142	bridgereg_t _pad_000120;
143	bridgereg_t b_int_device; /* 0x000124 */
144	bridgereg_t _pad_000128;
145	bridgereg_t b_int_host_err; /* 0x00012C */
146
147	struct {
148	bridgereg_t __pad; /* 0x0001{30,,,68} */
149	bridgereg_t addr; /* 0x0001{34,,,6C} */
150	} b_int_addr[8]; /* 0x000130 */
151
152	bridgereg_t _pad_000170[36];
153
154	/* Device 0x000200-0x0003FF */
155	struct {
156	bridgereg_t __pad; /* 0x0002{00,,,38} */
157	bridgereg_t reg; /* 0x0002{04,,,3C} */
158	} b_device[8]; /* 0x000200 */
159
160	struct {
161	bridgereg_t __pad; /* 0x0002{40,,,78} */
162	bridgereg_t reg; /* 0x0002{44,,,7C} */
163	} b_wr_req_buf[8]; /* 0x000240 */
164
165	struct {
166	bridgereg_t __pad; /* 0x0002{80,,,88} */
167	bridgereg_t reg; /* 0x0002{84,,,8C} */
168	} b_rrb_map[2]; /* 0x000280 */
169	#define b_even_resp b_rrb_map[0].reg /* 0x000284 */
170	#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
171
172	bridgereg_t _pad_000290;
173	bridgereg_t b_resp_status; /* 0x000294 */
174	bridgereg_t _pad_000298;
175	bridgereg_t b_resp_clear; /* 0x00029C */
176
177	bridgereg_t _pad_0002A0[24];
178
179	char _pad_000300[0x10000 - 0x000300];
180
181	/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
182	union {
183	bridge_ate_t wr; /* write-only */
184	struct {
185	bridgereg_t _p_pad;
186	bridgereg_t rd; /* read-only */
187	} hi;
188	} b_int_ate_ram[128];
189
190	char _pad_010400[0x11000 - 0x010400];
191
192	/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
193	struct {
194	bridgereg_t _p_pad;
195	bridgereg_t rd; /* read-only */
196	} b_int_ate_ram_lo[128];
197
198	char _pad_011400[0x20000 - 0x011400];
199
200	/* PCI Device Configuration Spaces 0x020000-0x027FFF */
201	union { /* make all access sizes available. */
202	__u8 c[0x1000 / 1];
203	__u16 s[0x1000 / 2];
204	__u32 l[0x1000 / 4];
205	__u64 d[0x1000 / 8];
206	union {
207	__u8 c[0x100 / 1];
208	__u16 s[0x100 / 2];
209	__u32 l[0x100 / 4];
210	__u64 d[0x100 / 8];
211	} f[8];
212	} b_type0_cfg_dev[8]; /* 0x020000 */
213
214	/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
215	union { /* make all access sizes available. */
216	__u8 c[0x1000 / 1];
217	__u16 s[0x1000 / 2];
218	__u32 l[0x1000 / 4];
219	__u64 d[0x1000 / 8];
220	} b_type1_cfg; /* 0x028000-0x029000 */
221
222	char _pad_029000[0x007000]; /* 0x029000-0x030000 */
223
224	/* PCI Interrupt Acknowledge Cycle 0x030000 */
225	union {
226	__u8 c[8 / 1];
227	__u16 s[8 / 2];
228	__u32 l[8 / 4];
229	__u64 d[8 / 8];
230	} b_pci_iack; /* 0x030000 */
231
232	__u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
233
234	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
235	bridge_ate_t b_ext_ate_ram[0x10000];
236
237	/* Reserved 0x100000-0x1FFFFF */
238	char _pad_100000[0x200000-0x100000];
239
240	/* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
241	union { /* make all access sizes available. */
242	__u8 c[0x100000 / 1];
243	__u16 s[0x100000 / 2];
244	__u32 l[0x100000 / 4];
245	__u64 d[0x100000 / 8];
246	} b_devio_raw[10]; /* 0x200000 */
247
248	/* b_devio macro is a bit strange; it reflects the
249	* fact that the Bridge ASIC provides 2M for the
250	* first two DevIO windows and 1M for the other six.
251	*/
252	#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
253
254	/* External Flash Proms 1,0 0xC00000-0xFFFFFF */
255	union { /* make all access sizes available. */
256	__u8 c[0x400000 / 1]; /* read-only */
257	__u16 s[0x400000 / 2]; /* read-write */
258	__u32 l[0x400000 / 4]; /* read-only */
259	__u64 d[0x400000 / 8]; /* read-only */
260	} b_external_flash; /* 0xC00000 */
261	} bridge_t;
262
263	/*
264	* Field formats for Error Command Word and Auxillary Error Command Word
265	* of bridge.
266	*/
267	typedef struct bridge_err_cmdword_s {
268	union {
269	__u32 cmd_word;
270	struct {
271	__u32 didn:4, /* Destination ID */
272	sidn:4, /* Source ID */
273	pactyp:4, /* Packet type */
274	tnum:5, /* Trans Number */
275	coh:1, /* Coh Transacti */
276	ds:2, /* Data size */
277	gbr:1, /* GBR enable */
278	vbpm:1, /* VBPM message */
279	error:1, /* Error occurred */
280	barr:1, /* Barrier op */
281	rsvd:8;
282	} berr_st;
283	} berr_un;
284	} bridge_err_cmdword_t;
285
286	#define berr_field berr_un.berr_st
287	#endif /* !__ASSEMBLY__ */
288
289	/*
290	* The values of these macros can and should be crosschecked
291	* regularly against the offsets of the like-named fields
292	* within the "bridge_t" structure above.
293	*/
294
295	/* Byte offset macros for Bridge internal registers */
296
297	#define BRIDGE_WID_ID WIDGET_ID
298	#define BRIDGE_WID_STAT WIDGET_STATUS
299	#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
300	#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
301	#define BRIDGE_WID_CONTROL WIDGET_CONTROL
302	#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
303	#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
304	#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
305	#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
306	#define BRIDGE_WID_LLP WIDGET_LLP_CFG
307	#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
308
309	#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */
310	#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */
311	#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */
312	#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */
313
314	#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */
315
316	#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */
317
318	#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */
319
320	#define BRIDGE_NIC 0x0000B4 /* Number In A Can */
321
322	#define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */
323	#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
324	#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */
325	#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */
326	#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */
327
328	#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
329	#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
330	#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */
331	#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
332	#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
333	#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */
334
335	#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */
336	#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */
337	#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
338
339	#define BRIDGE_DEVICE0 0x000204 /* Device 0 */
340	#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */
341	#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
342
343	#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */
344	#define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */
345	#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
346
347	#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */
348	#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */
349
350	#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */
351	#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */
352
353	/* Byte offset macros for Bridge I/O space */
354
355	#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
356
357	#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */
358	#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */
359	#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
360	#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
361	(s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
362	#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\
363	(s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
364	(f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
365
366	#define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */
367
368	#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
369	#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */
370
371	/* Byte offset macros for Bridge device IO spaces */
372
373	#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */
374	#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */
375	#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */
376	#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */
377	#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */
378
379	#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */
380	#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */
381
382	#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)BRIDGE_DEVIO_1MB)
383
384	#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
385
386	/* ========================================================================
387	* Bridge register bit field definitions
388	*/
389
390	/* Widget part number of bridge */
391	#define BRIDGE_WIDGET_PART_NUM 0xc002
392	#define XBRIDGE_WIDGET_PART_NUM 0xd002
393
394	/* Manufacturer of bridge */
395	#define BRIDGE_WIDGET_MFGR_NUM 0x036
396	#define XBRIDGE_WIDGET_MFGR_NUM 0x024
397
398	/* Revision numbers for known Bridge revisions */
399	#define BRIDGE_REV_A 0x1
400	#define BRIDGE_REV_B 0x2
401	#define BRIDGE_REV_C 0x3
402	#define BRIDGE_REV_D 0x4
403
404	/* Bridge widget status register bits definition */
405
406	#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
407	#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
408	#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
409	#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
410	#define BRIDGE_STAT_PENDING (0x1F << 0)
411
412	/* Bridge widget control register bits definition */
413	#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
414	#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
415	#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
416	#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
417	#define BRIDGE_CTRL_RST(n) ((n) << 24)
418	#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
419	#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
420	#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
421	#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
422	#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
423	#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
424	#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
425	#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
426	#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
427	#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
428	#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
429	#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
430	#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
431	#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
432	#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
433	#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
434	#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
435	#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
436	#define BRIDGE_CTRL_SYS_END (0x1 << 9)
437	#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
438	#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
439	#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
440	#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
441
442	/* Bridge Response buffer Error Upper Register bit fields definition */
443	#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
444	#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
445	#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
446	#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
447	#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
448
449	#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
450	(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
451	BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
452
453	#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
454	(((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
455	BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
456
457	/* Bridge direct mapping register bits definition */
458	#define BRIDGE_DIRMAP_W_ID_SHFT 20
459	#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
460	#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
461	#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
462	#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
463	#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
464
465	/* Bridge Arbitration register bits definition */
466	#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
467	#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
468	#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
469	#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
470	#define BRIDGE_ARB_FREEZE_GNT (1 << 6)
471	#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
472	#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
473	#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
474	#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
475	#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
476	#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
477
478	/* Bridge Bus time-out register bits definition */
479	#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
480	#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
481	#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
482	#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
483	#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
484
485	/* Bridge interrupt status register bits definition */
486	#define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
487	#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
488	#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
489	#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
490	#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
491	#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
492	#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
493	#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
494	#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
495	#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
496	#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
497	#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
498	#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
499	#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
500	#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
501	#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
502	#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
503	#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
504	#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
505	#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
506	#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
507	#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
508	#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
509	#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
510	#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
511	#define BRIDGE_ISR_INT_MSK (0xff << 0)
512	#define BRIDGE_ISR_INT(x) (0x1 << (x))
513
514	#define BRIDGE_ISR_LINK_ERROR \
515	(BRIDGE_ISR_LLP_REC_SNERR\|BRIDGE_ISR_LLP_REC_CBERR\| \
516	BRIDGE_ISR_LLP_RCTY\|BRIDGE_ISR_LLP_TX_RETRY\| \
517	BRIDGE_ISR_LLP_TCTY)
518
519	#define BRIDGE_ISR_PCIBUS_PIOERR \
520	(BRIDGE_ISR_PCI_MST_TIMEOUT\|BRIDGE_ISR_PCI_ABORT)
521
522	#define BRIDGE_ISR_PCIBUS_ERROR \
523	(BRIDGE_ISR_PCIBUS_PIOERR\|BRIDGE_ISR_PCI_PERR\| \
524	BRIDGE_ISR_PCI_SERR\|BRIDGE_ISR_PCI_RETRY_CNT\| \
525	BRIDGE_ISR_PCI_PARITY)
526
527	#define BRIDGE_ISR_XTALK_ERROR \
528	(BRIDGE_ISR_XREAD_REQ_TIMEOUT\|BRIDGE_ISR_XREQ_FIFO_OFLOW\|\
529	BRIDGE_ISR_UNSUPPORTED_XOP\|BRIDGE_ISR_INVLD_ADDR\| \
530	BRIDGE_ISR_REQ_XTLK_ERR\|BRIDGE_ISR_RESP_XTLK_ERR\| \
531	BRIDGE_ISR_BAD_XREQ_PKT\|BRIDGE_ISR_BAD_XRESP_PKT\| \
532	BRIDGE_ISR_UNEXP_RESP)
533
534	#define BRIDGE_ISR_ERRORS \
535	(BRIDGE_ISR_LINK_ERROR\|BRIDGE_ISR_PCIBUS_ERROR\| \
536	BRIDGE_ISR_XTALK_ERROR\|BRIDGE_ISR_SSRAM_PERR\| \
537	BRIDGE_ISR_PMU_ESIZE_FAULT)
538
539	/*
540	* List of Errors which are fatal and kill the sytem
541	*/
542	#define BRIDGE_ISR_ERROR_FATAL \
543	((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)\|\
544	BRIDGE_ISR_PCI_SERR\|BRIDGE_ISR_PCI_PARITY )
545
546	#define BRIDGE_ISR_ERROR_DUMP \
547	(BRIDGE_ISR_PCIBUS_ERROR\|BRIDGE_ISR_PMU_ESIZE_FAULT\| \
548	BRIDGE_ISR_XTALK_ERROR\|BRIDGE_ISR_SSRAM_PERR)
549
550	/* Bridge interrupt enable register bits definition */
551	#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
552	#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
553	#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
554	#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
555	#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
556	#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
557	#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
558	#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
559	#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
560	#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
561	#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
562	#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
563	#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
564	#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
565	#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
566	#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
567	#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
568	#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
569	#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
570	#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
571	#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
572	#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
573	#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
574	#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
575	#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
576	#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
577
578	/* Bridge interrupt reset register bits definition */
579	#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
580	#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
581	#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
582	#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
583	#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
584	#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
585	#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
586	#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
587	#define BRIDGE_IRR_ALL_CLR 0x7f
588
589	#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP \| \
590	BRIDGE_ISR_XREQ_FIFO_OFLOW)
591	#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT \| \
592	BRIDGE_ISR_RESP_XTLK_ERR \| \
593	BRIDGE_ISR_XREAD_REQ_TIMEOUT)
594	#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP \| \
595	BRIDGE_ISR_BAD_XREQ_PKT \| \
596	BRIDGE_ISR_REQ_XTLK_ERR \| \
597	BRIDGE_ISR_INVLD_ADDR)
598	#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR \| \
599	BRIDGE_ISR_LLP_REC_CBERR \| \
600	BRIDGE_ISR_LLP_RCTY \| \
601	BRIDGE_ISR_LLP_TX_RETRY \| \
602	BRIDGE_ISR_LLP_TCTY)
603	#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR \| \
604	BRIDGE_ISR_PMU_ESIZE_FAULT)
605	#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT \| \
606	BRIDGE_ISR_PCI_PARITY \| \
607	BRIDGE_ISR_PCI_SERR \| \
608	BRIDGE_ISR_PCI_PERR \| \
609	BRIDGE_ISR_PCI_MST_TIMEOUT \| \
610	BRIDGE_ISR_PCI_RETRY_CNT)
611
612	#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR \| \
613	BRIDGE_ISR_GIO_MST_TIMEOUT)
614
615	/* Bridge INT_DEV register bits definition */
616	#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
617	#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
618	#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
619
620	/* Bridge interrupt(x) register bits definition */
621	#define BRIDGE_INT_ADDR_HOST 0x0003FF00
622	#define BRIDGE_INT_ADDR_FLD 0x000000FF
623
624	#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
625	#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
626	#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
627
628	#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
629
630	/*
631	* The NASID should be shifted by this amount and stored into the
632	* interrupt(x) register.
633	*/
634	#define BRIDGE_INT_ADDR_NASID_SHFT 8
635
636	/*
637	* The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
638	* memory.
639	*/
640	#define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
641	#define BRIDGE_INT_ADDR_DEST_MEM 0
642	#define BRIDGE_INT_ADDR_MASK (1 << 17)
643
644	/* Bridge device(x) register bits definition */
645	#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
646	#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
647	#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
648	#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
649	#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
650	#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
651	#define BRIDGE_DEV_DEV_SIZE 0x00400000
652	#define BRIDGE_DEV_RT 0x00200000
653	#define BRIDGE_DEV_SWAP_PMU 0x00100000
654	#define BRIDGE_DEV_SWAP_DIR 0x00080000
655	#define BRIDGE_DEV_PREF 0x00040000
656	#define BRIDGE_DEV_PRECISE 0x00020000
657	#define BRIDGE_DEV_COH 0x00010000
658	#define BRIDGE_DEV_BARRIER 0x00008000
659	#define BRIDGE_DEV_GBR 0x00004000
660	#define BRIDGE_DEV_DEV_SWAP 0x00002000
661	#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
662	#define BRIDGE_DEV_OFF_MASK 0x00000fff
663	#define BRIDGE_DEV_OFF_ADDR_SHFT 20
664
665	#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN \| \
666	BRIDGE_DEV_SWAP_PMU)
667	#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN \| \
668	BRIDGE_DEV_SWAP_DIR \| \
669	BRIDGE_DEV_PREF \| \
670	BRIDGE_DEV_PRECISE \| \
671	BRIDGE_DEV_COH \| \
672	BRIDGE_DEV_BARRIER)
673	#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN \| \
674	BRIDGE_DEV_SWAP_DIR \| \
675	BRIDGE_DEV_COH \| \
676	BRIDGE_DEV_BARRIER)
677
678	/* Bridge Error Upper register bit field definition */
679	#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
680	#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
681	#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
682	#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
683	#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
684	#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
685
686	/* Bridge interrupt mode register bits definition */
687	#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
688
689	/* this should be written to the xbow's link_control(x) register */
690	#define BRIDGE_CREDIT 3
691
692	/* RRB assignment register */
693	#define BRIDGE_RRB_EN 0x8 /* after shifting down */
694	#define BRIDGE_RRB_DEV 0x7 /* after shifting down */
695	#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
696	#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
697
698	/* RRB status register */
699	#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
700	#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
701
702	/* RRB clear register */
703	#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
704
705	/* xbox system controller declarations */
706	#define XBOX_BRIDGE_WID 8
707	#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */
708	#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */
709	#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */
710
711	/* ========================================================================
712	*/
713	/*
714	* Macros for Xtalk to Bridge bus (PCI/GIO) PIO
715	* refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
716	*/
717	/* XTALK addresses that map into Bridge Bus addr space */
718	#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
719	#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
720	#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
721	#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
722	#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
723	#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
724
725	/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
726	#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
727	#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
728	#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */
729	#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
730
731	/* XTALK addresses that map into PCI addresses */
732	#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
733	#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
734	#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
735	#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
736	#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
737	#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
738
739	/*
740	* Macros for Bridge bus (PCI/GIO) to Xtalk DMA
741	*/
742	/* Bridge Bus DMA addresses */
743	#define BRIDGE_LOCAL_BASE 0
744	#define BRIDGE_DMA_MAPPED_BASE 0x40000000
745	#define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */
746	#define BRIDGE_DMA_DIRECT_BASE 0x80000000
747	#define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */
748
749	#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
750
751	/* PCI addresses of regions decoded by Bridge for DMA */
752	#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
753	#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
754
755	#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
756	#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \
757	(ulong_t)(x) >= PCI32_MAPPED_BASE)
758	#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
759	#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
760
761	/*
762	* The GIO address space.
763	*/
764	/* Xtalk to GIO PIO */
765	#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
766	#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
767
768	#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
769
770	/* GIO addresses of regions decoded by Bridge for DMA */
771	#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
772	#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
773
774	#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
775	#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \
776	(ulong_t)(x) >= GIO_MAPPED_BASE)
777	#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
778
779	/* PCI to xtalk mapping */
780
781	/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
782	* which xtalk address is accessed
783	*/
784	#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
785	#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
786	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
787	((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
788
789	/* 64-bit address attribute masks */
790	#define PCI64_ATTR_TARG_MASK 0xf000000000000000
791	#define PCI64_ATTR_TARG_SHFT 60
792	#define PCI64_ATTR_PREF 0x0800000000000000
793	#define PCI64_ATTR_PREC 0x0400000000000000
794	#define PCI64_ATTR_VIRTUAL 0x0200000000000000
795	#define PCI64_ATTR_BAR 0x0100000000000000
796	#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
797	#define PCI64_ATTR_RMF_SHFT 48
798
799	#ifndef __ASSEMBLY__
800	/* Address translation entry for mapped pci32 accesses */
801	typedef union ate_u {
802	__u64 ent;
803	struct ate_s {
804	__u64 rmf:16;
805	__u64 addr:36;
806	__u64 targ:4;
807	__u64 reserved:3;
808	__u64 barrier:1;
809	__u64 prefetch:1;
810	__u64 precise:1;
811	__u64 coherent:1;
812	__u64 valid:1;
813	} field;
814	} ate_t;
815	#endif /* !__ASSEMBLY__ */
816
817	#define ATE_V 0x01
818	#define ATE_CO 0x02
819	#define ATE_PREC 0x04
820	#define ATE_PREF 0x08
821	#define ATE_BAR 0x10
822
823	#define ATE_PFNSHIFT 12
824	#define ATE_TIDSHIFT 8
825	#define ATE_RMFSHIFT 48
826
827	#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) \| \
828	((xid)<<ATE_TIDSHIFT) \| \
829	(attr)
830
831	#define BRIDGE_INTERNAL_ATES 128
832
833	struct bridge_controller {
834	struct pci_controller pc;
835	struct resource mem;
836	struct resource io;
837	bridge_t *base;
838	nasid_t nasid;
839	unsigned int widget_id;
840	unsigned int irq_cpu;
841	dma64_addr_t baddr;
842	unsigned int pci_int[8];
843	};
844
845	#define BRIDGE_CONTROLLER(bus) \
846	((struct bridge_controller *)((bus)->sysdata))
847
848	extern void register_bridge_irq(unsigned int irq);
849	extern int request_bridge_irq(struct bridge_controller *bc);
850
851	#endif /* _ASM_PCI_BRIDGE_H */

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source: svn/newcon3bcm2_21bu/toolchain/mipsel-linux-uclibc/include/asm/pci/bridge.h @ 74

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