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HDMI_TX_DRV.c

Last change on this file was 76, checked in by megakiss, 10 years ago
1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
File size: 208.8 KB

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1	// ANALOGIX Company
2	// HDMI_TX Demo Firmware on SST
3
4	#include <stdio.h>
5
6	#include "dsthalcommon.h"
7	#include "dsthalsys.h"
8	#include "ANX8560.h"
9	#include "HDMI_TX_DRV.h"
10	#include "HDMI_TX_System_Config.h"
11	#if USE_HDMI_RX
12	# include "thdmi_8775.h"
13	#endif
14
15	extern DHL_DISP_CONFIG g_DispConfig;
16	extern DHL_RESULT DD_DISP_VideoMute(DS_BOOL uMute);
17	#if USE_HDMI_RX
18	extern int DD_SYS_IsANX8775Exist(void);
19	#endif
20
21	const struct Video_Timing _861_Video_Timing[] = {
22	//h_total h_act v_total v_act h_fp h_wid h_bp v_fp v_wid v_bp h_pol v_pol I_P mode
23	{800, 640, 525, 480, 16, 96, 48, 10, 2, 33, 1, 1, 0, 0},//640x480p@60 0
24	// {1650, 1280, 750, 720, 147, 40, 183, 5, 5, 20, 0, 0, 0, 1},//1280x720p@60 1
25	{1650, 1280, 750, 720, 110, 40, 220, 5, 5, 20, 0, 0, 0, 1},//1280x720p@60 1
26	{2200, 1920, 1125, 1080, 88, 44, 148, 2, 5, 15, 0, 0, 1, 2},//1920x1080i@60 2
27	// {2200, 1920, 1125, 1080, 40, 11, 229, 2, 5, 15, 0, 0, 1, 2},//1920x1080i@60 2
28	// {858, 720, 525, 480, 16, 62, 60, 9, 6, 30, 1, 1, 0, 0},//720x480p@60 3
29	{858, 720, 525, 480, 16, 60, 62, 9, 6, 30, 1, 1, 0, 0},//720x480p@60 3
30	{858, 720, 525, 480, 19, 62, 57, 4, 3, 15, 1, 1, 1, 1},//720x480i@60 4
31	{2200, 1920, 1125, 1080, 88, 44, 148, 4, 5, 36, 0, 0, 0, 0},//1920x1080p@60 5
32	// {2200, 1920, 1125, 1080, 32, 32, 216, 10, 4, 31, 0, 0, 0, 0},//1920x1080p@60 5
33	{2640, 1920, 1125, 1080, 528, 44, 148, 4, 5, 36, 0, 0, 0, 1},//1920x1080p@50 6
34	{1980, 1280, 750, 720, 440, 40, 220, 5, 5, 20, 0, 0, 0, 2},//1280x720p@50 7
35	{2640, 1920, 1125, 1080, 528, 44, 148, 2, 5, 15, 0, 0, 1, 0},//1920x1080i@50 8
36	{864, 720, 625, 576, 12, 64, 68, 5, 5, 39, 1, 1, 0, 1},//720x576p@50 9
37	{864, 720, 625, 576, 12, 63, 69, 2, 3, 19, 1, 1, 1, 2},//720x576i@50 10
38	};
39	WORD hdmi_tx_h_total;
40	WORD hdmi_tx_h_active;
41	WORD hdmi_tx_v_total;
42	WORD hdmi_tx_v_active;
43	WORD hdmi_tx_h_fp;
44	WORD hdmi_tx_hsync_width;
45	WORD hdmi_tx_h_bp;
46	BYTE hdmi_tx_v_fp;
47	BYTE hdmi_tx_vsync_width;
48	BYTE hdmi_tx_v_bp;
49	BYTE hdmi_tx_hsync_polarity;
50	BYTE hdmi_tx_vsync_polarity;
51	BYTE hdmi_tx_type_I_P;
52
53	int hdmi_tx_audio_input=HDMI_TX_AUD_HW_INTERFACE;
54	int hdmi_tx_freq_mclk=HDMI_TX_MCLK_Fs_RELATION;
55
56	extern BIT restart_system;
57	BYTE hdmi_tx_avi_data[19];
58	BYTE HDMI_TX_system_state;
59	BYTE spdif_error_cnt = 0x00;
60	BYTE misc_reset_needed;
61	BYTE hdmi_tx_stdaddr,hdmi_tx_stdreg,hdmi_tx_ext_block_num;
62	BYTE hdmi_tx_svd_length,hdmi_tx_sau_length;
63	BYTE hdmi_tx_edid_dtd[18];
64	WORD hdmi_tx_edid_length;
65	hdmi_tx_edid_result_4_system hdmi_tx_edid_result;
66
67	BIT hdmi_tx_ddc_fifo_full;
68	BIT hdmi_tx_ddc_progress;
69	BIT hdmi_tx_hdcp_auth_en;
70	BIT hdmi_tx_HDCP_enable;
71	BIT hdmi_tx_ksv_srm_pass;
72	int hdmi_tx_hdcp_auth_fail_cnt = 0;
73	BYTE hdmi_tx_hdcp_bcaps;
74	BYTE hdmi_tx_hdcp_bstatus[2];
75	BYTE hdmi_BKSV[5];
76	BYTE hdmi_BKSV_bkp[5];
77	BIT hdmi_tx_srm_checked;
78	BIT hdmi_tx_hdcp_auth_pass;
79	BIT hdmi_tx_hdcp_auth_done;
80	BIT hdmi_tx_avmute_enable;
81	BIT hdmi_tx_send_blue_screen;
82	BIT hdmi_tx_hdcp_encryption;
83	BIT hdmi_tx_hdcp_init_done;
84	BIT hdmi_tx_hdcp_wait_100ms_needed;
85	BIT hdmi_tx_parse_edid_done;
86	BYTE hdmi_tx_hdcp_auth_fail_counter ;
87	int g_SPDIFRX_Enable = 1;
88
89	BYTE hdmi_tx_video_format_config;
90	BIT hdmi_tx_emb_sync_mode,hdmi_tx_de_gen_en,hdmi_tx_demux_yc_en,hdmi_tx_ddr_bus_mode;
91	BIT hdmi_tx_ddr_edge;
92	BYTE hdmi_tx_ycmux_BIT_sel;
93	BIT hdmi_tx_system_config_video_done,hdmi_tx_system_config_audio_done;
94	BYTE hdmi_tx_RGBorYCbCr;
95	BYTE hdmi_tx_input_csc;
96	BYTE hdmi_tx_in_pix_rpt,hdmi_tx_tx_pix_rpt;
97	BYTE hdmi_tx_in_pix_rpt_bkp,hdmi_tx_tx_pix_rpt_bkp;
98	BYTE hdmi_tx_video_timing_id, saved_hdmi_tx_video_timing_id;
99	BIT hdmi_tx_pix_rpt_set_by_sys;
100	BYTE hdmi_tx_video_timing_parameter[18];
101	BYTE switch_value_sw_backup,switch_value_pc_backup;
102	BYTE switch_value,bist_switch_value_pc;
103	BIT hdmi_tx_new_csc,hdmi_tx_new_vid_id,hdmi_tx_new_HW_interface;
104
105	audio_config_struct s_hdmi_tx_audio_config;
106	config_packets s_hdmi_tx_packet_config;
107
108	BYTE FREQ_MCLK; //0X72:0X50 bit2:0
109	//000b:Fm = 128*Fs
110	//001b:Fm = 256*Fs
111	//010b:Fm = 384*Fs
112	//011b:Fm = 512*Fs
113	BIT hdmi_tx_app_hold_video_config,hdmi_tx_app_hold_audio_config;
114	BIT hdmi_tx_shutdown;
115	BYTE hdmi_tx_edid_buf[HDMI_TX_EDID_BUF_SIZE];
116	BYTE valid_hdmi_tx_edid;
117	BYTE bExtSwing = 1;
118
119	static HDMI_TX_TMDS_AMP tmds_d0_amp_ls = HDMI_TX_TMDS_AMP_500, tmds_d1_amp_ls = HDMI_TX_TMDS_AMP_500,
120	tmds_d2_amp_ls = HDMI_TX_TMDS_AMP_500, tmds_clk_amp_ls = HDMI_TX_TMDS_AMP_460;
121
122	static HDMI_TX_TMDS_AMP tmds_d0_amp_hs = HDMI_TX_TMDS_AMP_620, tmds_d1_amp_hs = HDMI_TX_TMDS_AMP_620,
123	tmds_d2_amp_hs = HDMI_TX_TMDS_AMP_580, tmds_clk_amp_hs = HDMI_TX_TMDS_AMP_620;
124
125	static HDMI_TX_TMDS_EMP tmds_d0_emp_ls = HDMI_TX_TMDS_EMP_0, tmds_d1_emp_ls = HDMI_TX_TMDS_EMP_0,
126	tmds_d2_emp_ls = HDMI_TX_TMDS_EMP_0, tmds_clk_emp_ls = HDMI_TX_TMDS_EMP_0,
127	tmds_d0_emp_hs = HDMI_TX_TMDS_EMP_0, tmds_d1_emp_hs = HDMI_TX_TMDS_EMP_0,
128	tmds_d2_emp_hs = HDMI_TX_TMDS_EMP_0, tmds_clk_emp_hs = HDMI_TX_TMDS_EMP_0;
129
130	typedef void (*HPDCallback)(void);
131	static HPDCallback cb_HPDCallback = (HPDCallback)0;
132	static FILE *LogFile = NULL;
133
134	#define TT() ;//HDMI_TX_PrintTimeLog(__FUNCTION__, __LINE__)
135	void HDMI_TX_Set_TMDS_Emp_Internal(void);
136	void HDMI_TX_Set_TMDS_Amp_Internal(void);
137
138	void HDMI_TX_OpenTimeLog(void)
139	{
140	if (LogFile == NULL)
141	{
142	#if 0
143	LogFile = fopen("time_log.txt", "w+");
144	if (LogFile == NULL)
145	{
146	printf("\|%s\| Cannot open log file.\n", __FUNCTION__);
147	}
148	#else
149	LogFile = stdout;
150	#endif
151	}
152	}
153
154	void HDMI_TX_CloseTimeLog(void)
155	{
156	if (LogFile != NULL)
157	{
158	fclose(LogFile);
159	LogFile = stdout;
160	}
161	}
162
163	void HDMI_TX_PrintTimeLog(const char *func, int line)
164	{
165	static unsigned long SavedTick = 0;
166	unsigned long Tick;
167
168	if (LogFile == NULL)
169	{
170	HDMI_TX_OpenTimeLog();
171	}
172	Tick = OS_GetTickCount();
173	if (LogFile != NULL)
174	{
175	fprintf(LogFile, "\|%s, %d\| <<%ld>>\n", func, line, Tick - SavedTick);
176	}
177	SavedTick = Tick;
178	}
179
180	void HDMI_TX_SetHPDCallback(HPDCallback callback)
181	{
182	cb_HPDCallback = callback;
183	}
184
185	DS_BOOL HDMI_TX_GetCorrectMuteState(DS_BOOL mute)
186	{
187	if(!hdmi_tx_HDCP_enable){ // HDCP °¡ ENABLE µÇ¾î ÀÖÁö ¾ÊÀ¸¸é ÇöÀç Mute »óÅÂ ±×´ë·Î Àû¿ë.
188	return mute;
189	}
190
191	if(!hdmi_tx_hdcp_auth_pass){ // HDCP ON, AUTHENTICATION PASSÇÏÁö ¾ÊÀº °æ¿ì Ç×»ó MuteÇÏµµ·Ï.
192	return 1;
193	}
194	return mute;
195	}
196
197	void HDMI_TX_Task()
198	{
199	HDMI_TX_Interrupt_Process();
200	HDMI_TX_Timer_Process ();
201	}
202
203	void HDMI_TX_BIST_Task(void)
204	{
205	HDMI_TX_Interrupt_Process();
206	#if BIST_MODE_USED
207	HDMI_TX_BIST();
208	#endif
209	}
210
211	void HDMI_TX_Timer_Slot1()
212	{
213	BYTE c;
214
215	if(HDMI_TX_system_state == HDMI_TX_INITIAL \|\| HDMI_TX_system_state == HDMI_TX_WAIT_HOTPLUG)
216	{
217	return;
218	}
219
220	if(HDMI_TX_system_state == HDMI_TX_READ_PARSE_EDID)
221	{
222	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
223	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c &(~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
224	hdmi_tx_hdcp_auth_en = 0;
225	hdmi_tx_hdcp_auth_fail_cnt = 0;
226
227	HDMI_TX_RST_DDCChannel();
228
229	HDMI_TX_Parse_EDID();
230	hdmi_tx_parse_edid_done = 1;
231	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
232	}
233	}
234
235	void HDMI_TX_Timer_Slot2(void)
236	{
237	if(HDMI_TX_system_state == HDMI_TX_CONFIG_VIDEO)
238	{
239	HDMI_TX_Config_Video();
240	}
241
242	if(HDMI_TX_system_state == HDMI_TX_HDCP_AUTHENTICATION)
243	{
244	HDMI_TX_HDCP_Process();
245	}
246	}
247
248	void HDMI_TX_Timer_Slot3(void)
249	{
250	if(HDMI_TX_system_state == HDMI_TX_CONFIG_AUDIO)
251	{
252	HDMI_TX_Config_Audio();
253	}
254
255	if(HDMI_TX_system_state == HDMI_TX_PLAY_BACK)
256	{
257	HDMI_TX_PLAYBACK_Process();
258	}
259	}
260
261	void HDMI_TX_Timer_Slot4()
262	{
263	;
264	}
265
266	void HDMI_TX_Variable_Initial()
267	{
268	TT();
269	hdmi_tx_hdcp_auth_en = 0;
270	hdmi_tx_hdcp_auth_fail_cnt = 0;
271	hdmi_tx_ksv_srm_pass =0;
272	hdmi_tx_srm_checked = 0;
273	hdmi_tx_hdcp_auth_pass = 0;
274	hdmi_tx_hdcp_auth_done=0;
275	hdmi_tx_avmute_enable = 1;
276	hdmi_tx_hdcp_auth_fail_counter =0 ;
277	hdmi_tx_hdcp_encryption = 0;
278	hdmi_tx_send_blue_screen = 0;
279	hdmi_tx_hdcp_init_done = 0;
280	hdmi_tx_hdcp_wait_100ms_needed = 1;
281	//******************for video config************
282	hdmi_tx_video_timing_id = 0;
283	hdmi_tx_in_pix_rpt = 0;
284	hdmi_tx_tx_pix_rpt = 0;
285	hdmi_tx_new_csc = 0;
286	hdmi_tx_new_vid_id = 0;
287	hdmi_tx_new_HW_interface = 0;
288	//******************end of video config*******
289
290	s_hdmi_tx_packet_config.packets_need_config = 0x03; //new avi infoframe
291	s_hdmi_tx_packet_config.avi_info.type = 0x82;
292	s_hdmi_tx_packet_config.avi_info.version = 0x02;
293	s_hdmi_tx_packet_config.avi_info.length = 0x0d;
294	s_hdmi_tx_packet_config.avi_info.pb_byte[1] = 0x21;//YCbCr422
295	s_hdmi_tx_packet_config.avi_info.pb_byte[2] = 0x08;
296	s_hdmi_tx_packet_config.avi_info.pb_byte[3] = 0x00;
297	s_hdmi_tx_packet_config.avi_info.pb_byte[4] = 0x00;
298	s_hdmi_tx_packet_config.avi_info.pb_byte[5] = 0x00;
299	s_hdmi_tx_packet_config.avi_info.pb_byte[6] = 0x00;
300	s_hdmi_tx_packet_config.avi_info.pb_byte[7] = 0x00;
301	s_hdmi_tx_packet_config.avi_info.pb_byte[8] = 0x00;
302	s_hdmi_tx_packet_config.avi_info.pb_byte[9] = 0x00;
303	s_hdmi_tx_packet_config.avi_info.pb_byte[10] = 0x00;
304	s_hdmi_tx_packet_config.avi_info.pb_byte[11] = 0x00;
305	s_hdmi_tx_packet_config.avi_info.pb_byte[12] = 0x00;
306	s_hdmi_tx_packet_config.avi_info.pb_byte[13] = 0x00;
307
308	// audio infoframe
309	s_hdmi_tx_packet_config.audio_info.type = 0x84;
310	s_hdmi_tx_packet_config.audio_info.version = 0x01;
311	s_hdmi_tx_packet_config.audio_info.length = 0x0a;
312	s_hdmi_tx_packet_config.audio_info.pb_byte[1] = 0x00;
313	s_hdmi_tx_packet_config.audio_info.pb_byte[2] = 0x00;
314	s_hdmi_tx_packet_config.audio_info.pb_byte[3] = 0x00;
315	s_hdmi_tx_packet_config.audio_info.pb_byte[4] = 0x00;
316	s_hdmi_tx_packet_config.audio_info.pb_byte[5] = 0x00;
317	s_hdmi_tx_packet_config.audio_info.pb_byte[6] = 0x00;
318	s_hdmi_tx_packet_config.audio_info.pb_byte[7] = 0x00;
319	s_hdmi_tx_packet_config.audio_info.pb_byte[8] = 0x00;
320	s_hdmi_tx_packet_config.audio_info.pb_byte[9] = 0x00;
321	s_hdmi_tx_packet_config.audio_info.pb_byte[10] = 0x00;
322
323	HDMI_TX_Reset_AVI();
324
325	}
326
327
328	void HDMI_TX_PresetAudioInput(int AudioInput)
329	{
330	hdmi_tx_audio_input = AudioInput;
331	if ( AudioInput == 0x01 /I2S/ ) {
332	hdmi_tx_freq_mclk = 0x00;
333	} else {
334	hdmi_tx_freq_mclk = 0x01;
335	}
336	}
337
338	void HDMI_TX_HW_Interface_Variable_Initial()
339	{
340	BYTE c,i;
341	TT();
342	hdmi_tx_video_format_config = HDMI_TX_VID_HW_INTERFACE;
343	hdmi_tx_input_csc = HDMI_TX_YCbCr444;
344	hdmi_tx_ddr_edge = HDMI_TX_IDCK_EDGE_DDR;
345
346	c = 0;
347	c = (HDMI_TX_I2S_CH0_ENABLE << 2) \| (HDMI_TX_I2S_CH1_ENABLE << 3) \|
348	(HDMI_TX_I2S_CH2_ENABLE << 4) \| (HDMI_TX_I2S_CH3_ENABLE << 5);
349	s_hdmi_tx_audio_config.audio_type = hdmi_tx_audio_input;//HDMI_TX_AUD_HW_INTERFACE; // input I2S
350	s_hdmi_tx_audio_config.down_sample = 0x00;
351	s_hdmi_tx_audio_config.i2s_config.audio_channel = c;//0x04;
352	s_hdmi_tx_audio_config.i2s_config.Channel_status1 =0x00;
353	s_hdmi_tx_audio_config.i2s_config.Channel_status1 = 0x00;
354	s_hdmi_tx_audio_config.i2s_config.Channel_status2 = 0x00;
355	s_hdmi_tx_audio_config.i2s_config.Channel_status3 = 0x00;
356	s_hdmi_tx_audio_config.i2s_config.Channel_status4 = HDMI_TX_AUD_Fs;//0x02;//48k
357	s_hdmi_tx_audio_config.i2s_config.Channel_status5 = HDMI_TX_I2S_WORD_LENGTH;//0x0b;
358
359	c = (HDMI_TX_I2S_SHIFT_CTRL << 3) \| (HDMI_TX_I2S_DIR_CTRL << 2) \|
360	(HDMI_TX_I2S_WS_POL << 1) \| HDMI_TX_I2S_JUST_CTRL;
361	s_hdmi_tx_audio_config.i2s_config.i2s_format = c;
362
363	FREQ_MCLK = hdmi_tx_freq_mclk;//HDMI_TX_MCLK_Fs_RELATION;//set the relation of MCLK and WS
364	for(c = 0; c < 5; c ++)
365	{
366	hdmi_BKSV_bkp[c] = 0;
367	hdmi_BKSV[c] = 0;
368	}
369
370	//******************for edid parse*********
371	hdmi_tx_edid_result.is_HDMI = 0;
372	hdmi_tx_edid_result.ycbcr422_supported = 0;
373	hdmi_tx_edid_result.ycbcr444_supported = 0;
374	hdmi_tx_edid_result.supported_720p_60Hz = 0;
375	hdmi_tx_edid_result.supported_720p_50Hz = 0;
376	hdmi_tx_edid_result.supported_576p_50Hz = 0;
377	hdmi_tx_edid_result.supported_576i_50Hz = 0;
378	hdmi_tx_edid_result.supported_1080i_60Hz = 0;
379	hdmi_tx_edid_result.supported_1080i_50Hz = 0;
380	hdmi_tx_edid_result.supported_640x480p_60Hz = 0;
381	hdmi_tx_edid_result.supported_720x480p_60Hz = 0;
382	hdmi_tx_edid_result.supported_720x480i_60Hz = 0;
383	hdmi_tx_edid_result.edid_errcode = 0;
384	hdmi_tx_edid_result.SpeakerFormat = 0;
385	for(i = 0; i < 8; i ++)
386	{
387	hdmi_tx_edid_result.AudioChannel[i] = 0;
388	hdmi_tx_edid_result.AudioFormat[i] = 0;
389	hdmi_tx_edid_result.AudioFs[i] = 0;
390	hdmi_tx_edid_result.AudioLength[i] = 0;
391	}
392	hdmi_tx_edid_result.RGB30bit = 0;
393	hdmi_tx_edid_result.RGB36bit = 0;
394	hdmi_tx_edid_result.RGB48bit = 0;
395	hdmi_tx_edid_result.DC_Y444 = 0;
396
397
398	//******************end of edid************
399
400	}
401
402	void HDMI_TX_Hotplug_Change_Interrupt(void)
403	{
404	BYTE c/,i/;
405	TT();
406	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
407	if (c & HDMI_TX_SYS_STATE_HP)
408	{
409	printf("\|HDMI-Tx Start\| Tick = %lx\n", OS_GetTickCount());
410
411	//disable audio & video & hdcp & TMDS and init begin
412	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
413	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
414
415	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
416	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, c & (~HDMI_TX_VID_CTRL_IN_EN));
417	HDMI_TX_MuteTMDS_CLK();
418	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
419	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
420
421	HDMI_TX_Variable_Initial();
422	HDMI_TX_HW_Interface_Variable_Initial();
423	HDMI_RPT_Set_BCAPS_Repeater(1);
424	//disable video & audio & hdcp & TMDS and init end
425
426	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);//suppose bksv is the same, set to config video
427	//Power on chip and select DVI mode
428	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
429	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c \| 0x01);
430	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
431	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c & 0xfd);
432	HDMI_TX_RST_DDCChannel();
433
434	//check BKSV to decide to set to which state
435	#if 0
436	//ÀÏ´Ü BKSV Ã¼Å© ·çÆ¾ »èÁ¦.
437	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x00, 0x05, 0x00);
438	OS_mDelay(15);
439	for(i = 0; i < 5; i ++)
440	{
441	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_BKSV[i]);
442	//HDMI_TX_DebugPrintf("BKSV[%.2x] = %.2x\n", (WORD)i,(WORD)hdmi_BKSV[i]);
443
444	// below 'if' code is not good when sink changing in same DTV board!!!
445	// for refreshing CEC phy addr, it always read edid.
446	// if(hdmi_BKSV[i] != hdmi_BKSV_bkp[i])// bksv different, means sink change, need to set to parse edid
447	#endif
448	HDMI_TX_Set_System_State(HDMI_TX_READ_PARSE_EDID);
449	#if 0
450	hdmi_BKSV_bkp[i] = hdmi_BKSV[i];
451	}
452	#endif
453	}
454	else
455	{
456	//Power down chip
457	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
458	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c & 0xfe);
459
460	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
461	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c & (~HDMI_TX_VID_MODE_LINKVID_EN) );
462	fprintf(stderr, "\|%s:%d\| HDMI_TX_VID_MODE_REG = 0x00\n", __FUNCTION__, __LINE__);
463
464	HDMI_TX_Set_System_State(HDMI_TX_WAIT_HOTPLUG);
465	hdmi_tx_hdcp_wait_100ms_needed = 1;
466	valid_hdmi_tx_edid = 0;
467
468
469	HDMI_TX_Variable_Initial(); //simon
470	HDMI_TX_HW_Interface_Variable_Initial(); //simon
471	HDMI_TX_Hardware_Initial(); //simon
472	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, 0x00); //simon
473	// anx9030_hdcp_wait_100ms_needed = 1;
474	hdmi_tx_hdcp_auth_pass = 0;
475
476	#if USE_HDMI_RX
477	if( DD_SYS_IsANX8775Exist() ){
478	//for repeater
479	HDMI_RPT_Set_BCAPS_Repeater(0);
480	HDMI_RPT_Set_BCAPS_Ready(0);
481	if ( DHL_CAP_GetVideoSrc(0) >= DHL_CAP_HDMI0_VIDEO && DHL_CAP_GetVideoSrc(0) <= DHL_CAP_HDMI3_VIDEO )
482	HDMI_RX_Set_HPD(0, 500);
483	}
484	#endif
485	}
486	// clear hdmi_tx_parse_edid_done & hdmi_tx_system_config_video_done
487	hdmi_tx_parse_edid_done = 0;
488	hdmi_tx_system_config_video_done = 0;
489	hdmi_tx_system_config_audio_done = 0;
490	hdmi_tx_srm_checked = 0;
491	hdmi_tx_ksv_srm_pass=0;
492	hdmi_tx_hdcp_init_done=0;
493
494	}
495
496
497
498	void HDMI_TX_Video_Clock_Change_Interrupt(void)
499	{
500	BYTE c;
501
502	if (HDMI_TX_IsFormatChange() == 0 && ((HDMI_TX_system_state != HDMI_TX_INITIAL) && (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
503	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID)))
504	return;
505
506	TT();
507	if((HDMI_TX_system_state != HDMI_TX_INITIAL) && (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
508	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID))
509	{
510	HDMI_TX_MuteTMDS_CLK();
511	HDMI_TX_Set_AVMute();
512	//stop HDCP and reset DDC
513	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
514	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
515	HDMI_TX_RST_DDCChannel();
516	HDMI_TX_DebugPrintf("after video clock change int \n");
517	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
518	}
519	//when clock change, clear this reg to avoid error in package config
520	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
521	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c & ~HDMI_TX_INFO_PKTCTRL1_AVI_EN);
522	fprintf(stderr, "\|%s:%d\| HDMI_TX_INFO_PKTCTRL1_REG = %x\n", __FUNCTION__, __LINE__, c & ~HDMI_TX_INFO_PKTCTRL1_AVI_EN);
523
524	hdmi_tx_system_config_video_done = 0;
525	}
526
527	void HDMI_TX_Video_Format_Change_Interrupt(void)
528	{
529	BYTE c;
530	TT();
531
532	if (HDMI_TX_IsFormatChange() == 0 && ((HDMI_TX_system_state != HDMI_TX_INITIAL)
533	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
534	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID)))
535	return;
536
537	if((HDMI_TX_system_state != HDMI_TX_INITIAL)
538	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
539	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID))
540	{
541	HDMI_TX_DebugPrintf("after video format change int \n");
542	HDMI_TX_MuteTMDS_CLK();
543	HDMI_TX_Set_AVMute();
544	//stop HDCP and reset DDC
545	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
546	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
547	HDMI_TX_RST_DDCChannel();
548	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
549	}
550	//when format change, clear this reg to avoid error in package config
551	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
552	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c & ~HDMI_TX_INFO_PKTCTRL1_AVI_EN);
553	fprintf(stderr, "\|%s:%d\| HDMI_TX_INFO_PKTCTRL1_REG = %x\n", __FUNCTION__, __LINE__, c & ~HDMI_TX_INFO_PKTCTRL1_AVI_EN);
554
555	hdmi_tx_system_config_video_done = 0;
556	}
557
558	void HDMI_TX_Audio_CLK_Change_Interrupt(void)
559	{
560	TT();
561	/*
562	BYTE c;
563	if((HDMI_TX_system_state != HDMI_TX_INITIAL)
564	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
565	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID)
566	&& (HDMI_TX_system_state != HDMI_TX_CONFIG_VIDEO))
567	{
568	HDMI_TX_DebugPrintf("HDMI_TX: audio clock changed interrupt,disable audio.\n");
569	// disable audio
570	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG,&c);
571	c &= ~HDMI_TX_HDMI_AUDCTRL1_IN_EN;
572	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG,c);
573	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_AUDIO);
574	}
575	//when format change, clear this reg to avoid error in package config
576	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
577	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c & ~HDMI_TX_INFO_PKTCTRL2_AIF_EN);
578	hdmi_tx_system_config_audio_done = 0;*/
579	}
580
581	static void HDMI_TX_Calib_GenCtrlPacket(void)
582	{
583	BYTE c1, c2;
584
585	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c1);
586	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c2);
587	printf("\|%s, %d\| Gen Ctrl Packet = %#04x\n", __FUNCTION__, __LINE__, c2);
588	if ((c2 & 0x3c) == 0x00 \|\| (c2 & 0x3c) == 0x10 \|\| (c2 & 0x3c) == 0x14 \|\| (c2 & 0x3c) == 0x18)
589	{
590	printf("\|%s, %d\| Pass!!!\n", __FUNCTION__, __LINE__);
591	}
592	else
593	{
594	printf("\|%s, %d\| Fail!!!\n", __FUNCTION__, __LINE__);
595	switch (c1 & 0x60)
596	{
597	case 0x00:
598	c2 = (c2 & ~0x3c) \| 0x10;
599	break;
600	case 0x20:
601	c2 = (c2 & ~0x3c) \| 0x14;
602	break;
603	case 0x40:
604	c2 = (c2 & ~0x3c) \| 0x18;
605	break;
606	}
607	printf("\|%s, %d\| Calib to %#04x!!!\n", __FUNCTION__, __LINE__, c2);
608	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, c2);
609	}
610	}
611
612
613	void HDMI_TX_Set_AVMute(void)
614	{
615	BYTE c;
616	TT();
617	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
618	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0xfd) \| 0x01));
619	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
620	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, (c \| 0x0c));
621	hdmi_tx_avmute_enable = 1;
622	HDMI_TX_DebugPrintf("Set AVMute\n");
623	HDMI_TX_Calib_GenCtrlPacket();
624	}
625
626	void HDMI_TX_Clear_AVMute(void)
627	{
628	BYTE c;
629	TT();
630	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
631	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0xfe) \| 0x02));
632	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
633	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, (c \| 0x0c));
634	hdmi_tx_avmute_enable = 0;
635	HDMI_TX_DebugPrintf("Clear AVMute\n");
636	HDMI_TX_Calib_GenCtrlPacket();
637	}
638
639
640	void HDMI_TX_Set_AudioMute(void)
641	{
642	BYTE c;
643	TT();
644	if (HDMI_TX_IsExistDevice() == 1)
645	{
646	if (HDMI_TX_system_state == HDMI_TX_PLAY_BACK)
647	{
648	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
649	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, c \| HDMI_TX_SYS_CTRL4_AUD_MUTE);
650	HDMI_TX_DebugPrintf("Set Audio Mute\n");
651	}
652	else
653	{
654	HDMI_TX_DebugPrintf("Cannot Set Audio Mute\n");
655	}
656	}
657	}
658
659	void HDMI_TX_Clear_AudioMute(void)
660	{
661	BYTE c;
662	TT();
663	if (HDMI_TX_IsExistDevice() == 1)
664	{
665	if (HDMI_TX_system_state == HDMI_TX_PLAY_BACK)
666	{
667	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
668	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, c & ~HDMI_TX_SYS_CTRL4_AUD_MUTE);
669	HDMI_TX_DebugPrintf("Clear Audio Mute\n");
670	}
671	else
672	{
673	HDMI_TX_DebugPrintf("Cannot Clear Audio Mute\n");
674	}
675	}
676	}
677	#if 0
678	void HDMI_TX_Auth_Done_Interrupt()
679	{
680	BYTE c;
681	TT();
682	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_STATUS_REG, &c);
683	if(c & HDMI_TX_HDCP_STATUS_AUTH_PASS)
684	{
685	HDMI_TX_DebugPrintf("HDMI_TX_Authentication pass in Auth_Done\n");
686	HDMI_TX_Blue_Screen_Disable();
687	hdmi_tx_hdcp_auth_pass = 1;
688	hdmi_tx_hdcp_auth_fail_counter = 0;
689	}
690	else
691	{
692	HDMI_TX_DebugPrintf("HDMI_TX_Authentication failed\n");
693	hdmi_tx_hdcp_wait_100ms_needed = 1;
694	hdmi_tx_hdcp_auth_pass = 0;
695	hdmi_tx_hdcp_auth_done=0;
696	hdmi_tx_hdcp_auth_fail_counter ++;
697	if(hdmi_tx_hdcp_auth_fail_counter >= HDMI_TX_HDCP_FAIL_THRESHOLD)
698	{
699	hdmi_tx_hdcp_auth_en = 0;
700	hdmi_tx_hdcp_auth_fail_cnt = 0;
701	hdmi_tx_hdcp_auth_pass = 0;
702	hdmi_tx_hdcp_auth_done=0;
703	hdmi_tx_hdcp_auth_fail_counter =0 ;
704	hdmi_tx_hdcp_encryption = 0;
705	hdmi_tx_send_blue_screen = 0;
706	//Disable hardware HDCP
707	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
708	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
709	HDMI_TX_Blue_Screen_Enable();
710	HDMI_TX_HDCP_Encryption_Disable();
711	//disable audio
712	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
713	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
714	}
715	}
716	}
717
718	void HDMI_TX_Auth_Change_Interrupt()
719	{
720	BYTE c;
721	TT();
722	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_STATUS_REG, &c);
723	if(c & HDMI_TX_HDCP_STATUS_AUTH_PASS)
724	{
725	hdmi_tx_hdcp_auth_pass = 1;
726	HDMI_TX_DebugPrintf("HDMI_TX_Authentication pass in Auth_Change************************\n");
727	}
728	else
729	{
730	HDMI_TX_Set_AVMute();
731	HDMI_TX_DebugPrintf("HDMI_TX_Authentication failed_by_Auth_change\n");
732	hdmi_tx_hdcp_auth_pass = 0;
733	hdmi_tx_hdcp_auth_done=0;
734	hdmi_tx_hdcp_wait_100ms_needed = 1;
735	HDMI_TX_HDCP_Encryption_Disable();
736	if(HDMI_TX_system_state > HDMI_TX_HDCP_AUTHENTICATION)
737	{
738	//HDMI_TX_Clean_HDCP();
739	//
740	// ´Ù½Ã HDCP initÀ» ÇØÁÖÀÚ. (Junku/080527)
741	//
742	hdmi_tx_hdcp_init_done = 0;
743
744	HDMI_TX_Set_System_State(HDMI_TX_HDCP_AUTHENTICATION);
745	//disable audio
746	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
747	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
748	}
749	}
750	}
751	#endif
752	void HDMI_TX_Auth_Done_Interrupt()
753	{
754	BYTE c;
755	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_STATUS_REG, &c);
756	if(c & HDMI_TX_HDCP_STATUS_AUTH_PASS)
757	{
758	HDMI_TX_DebugPrintf("HDMI_TX_ISR: HDCP_STATUS_AUTH_PASS OK");
759	if(hdmi_tx_send_blue_screen)
760	{
761	HDMI_TX_Blue_Screen_Disable();
762	}
763	if(hdmi_tx_avmute_enable)
764	{
765	HDMI_TX_Clear_AVMute();
766	}
767	//enable audio SY.
768	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
769	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
770	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c);
771
772	hdmi_tx_hdcp_auth_pass = 1;
773	hdmi_tx_hdcp_auth_fail_counter = 0;
774	}
775	else
776	{
777	HDMI_TX_DebugPrintf("HDMI_TX_ISR: HDCP_STATUS_AUTH_PASS failed");
778	hdmi_tx_hdcp_wait_100ms_needed = 1;
779	hdmi_tx_hdcp_auth_pass = 0;
780	hdmi_tx_hdcp_auth_fail_counter ++;
781	if(hdmi_tx_hdcp_auth_fail_counter >= HDMI_TX_HDCP_FAIL_THRESHOLD)//10 times
782	{
783	HDMI_TX_DebugPrintf("HDMI_TX_ISR: HDCP_FAIL_THRESHOLD reached. ");
784	hdmi_tx_hdcp_auth_fail_counter = 0;
785	// TODO: Reset link;
786	if(!hdmi_tx_send_blue_screen)
787	{
788	HDMI_TX_Blue_Screen_Enable();
789	}
790	if(hdmi_tx_avmute_enable)
791	{
792	HDMI_TX_Clear_AVMute();
793	}
794	HDMI_TX_HDCP_Encryption_Disable();//may be unnecessary. still in 1st part of authentication. SY.
795	//disable audio
796	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
797	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
798	}
799	}
800	}
801
802	void HDMI_TX_Auth_Change_Interrupt()
803	{
804	BYTE c;
805	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_STATUS_REG, &c);
806	if(c & HDMI_TX_HDCP_STATUS_AUTH_PASS)
807	{
808	HDMI_TX_DebugPrintf("HDMI_TX_ISR: HDCP_STATUS_AUTH_PASS OK");
809	if(hdmi_tx_send_blue_screen)
810	{
811	HDMI_TX_Blue_Screen_Disable();
812	}
813	if(hdmi_tx_avmute_enable)
814	{
815	HDMI_TX_Clear_AVMute();
816	}
817	//enable audio SY.
818	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
819	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
820	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c);
821	hdmi_tx_hdcp_auth_pass = 1;
822	}
823	else
824	{
825	HDMI_TX_DebugPrintf("HDMI_TX_ISR: HDCP_STATUS_AUTH failed");
826
827	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //disable HDCP, jh
828	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_SYS_CTRL1_HDCPMODE)));
829
830	if(!hdmi_tx_send_blue_screen)
831	{
832	HDMI_TX_Blue_Screen_Enable();
833	}
834	if(hdmi_tx_avmute_enable)
835	{
836	HDMI_TX_Clear_AVMute();
837	}
838	//disable audio
839	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
840	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
841
842	hdmi_tx_hdcp_auth_pass = 0;
843	hdmi_tx_hdcp_init_done=0;
844	hdmi_tx_hdcp_auth_en=0;
845	hdmi_tx_hdcp_auth_fail_cnt = 0;
846	hdmi_tx_hdcp_wait_100ms_needed = 1;
847	HDMI_TX_HDCP_Encryption_Disable();
848	if(HDMI_TX_system_state == HDMI_TX_PLAY_BACK)
849	{
850	HDMI_TX_Set_System_State(HDMI_TX_HDCP_AUTHENTICATION);//to re-start again
851	}
852	}
853	}
854
855
856	void HDMI_TX_AFIFO_Overrun_Interrupt(void)
857	{
858	BYTE c;
859	TT();
860	if(HDMI_TX_system_state != HDMI_TX_INITIAL
861	&& HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG
862	&& HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID
863	&& HDMI_TX_system_state != HDMI_TX_CONFIG_VIDEO)
864	{
865	HDMI_TX_DebugPrintf("HDMI_TX: AFIFO overrun interrupt,disable audio.\n");
866	// disable audio
867	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG,&c);
868	c &= ~HDMI_TX_HDMI_AUDCTRL1_IN_EN;
869	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG,c);
870	if(HDMI_TX_system_state == HDMI_TX_PLAY_BACK){
871	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_AUDIO);
872	}
873	}
874	}
875
876	void HDMI_TX_PllLock_Interrupt()
877	{
878	BYTE c;
879	TT();
880	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG,&c);
881	printf("\|%s\| HDMI_TX_SYS_STATE_REG: 0x%02X\n", __FUNCTION__, c);
882
883	if(!(c & HDMI_TX_SYS_STATE_TXPLL_MISC_LOCK))
884	{
885	if((HDMI_TX_system_state != HDMI_TX_INITIAL)
886	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
887	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID))
888	{
889	HDMI_TX_MuteTMDS_CLK();
890	HDMI_TX_Set_AVMute();
891	HDMI_TX_DebugPrintf("HDMI_TX: PLL unlock interrupt,disable audio.\n");
892	// disable audio & video
893	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG,&c);
894	c &= ~HDMI_TX_HDMI_AUDCTRL1_IN_EN;
895	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG,c);
896
897	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG,&c);
898	c &= ~HDMI_TX_VID_CTRL_IN_EN;
899	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,c);
900	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
901	}
902	}
903	}
904
905	void HDMI_TX_SPDIF_Error_Interrupt(BYTE int1, BYTE int3)
906	{
907	TT();
908	if((HDMI_TX_system_state == HDMI_TX_CONFIG_AUDIO
909	\|\| HDMI_TX_system_state == HDMI_TX_CONFIG_PACKETS
910	\|\| HDMI_TX_system_state == HDMI_TX_HDCP_AUTHENTICATION
911	\|\| HDMI_TX_system_state == HDMI_TX_PLAY_BACK )
912	&& (int3 & 0x81))
913	{
914	//HDMI_TX_DebugPrintf("SPDIF BI Phase or Unstable error.\n");
915	spdif_error_cnt += 0x03;
916	}
917	if((HDMI_TX_system_state == HDMI_TX_CONFIG_AUDIO
918	\|\| HDMI_TX_system_state == HDMI_TX_CONFIG_PACKETS
919	\|\| HDMI_TX_system_state == HDMI_TX_HDCP_AUTHENTICATION
920	\|\| HDMI_TX_system_state == HDMI_TX_PLAY_BACK )
921	&& (int1 & HDMI_TX_INTR1_STATUS_SPDIF_ERR))
922	{
923	//HDMI_TX_DebugPrintf("SPDIF Parity error.\n");
924	spdif_error_cnt += 0x01;
925	}
926
927	// adjust spdif phase
928	if(spdif_error_cnt >= spdif_error_th && hdmi_tx_audio_input == 0x02)
929	{
930	BYTE freq_mclk,c1,c;
931	spdif_error_cnt = 0x00;
932	//HDMI_TX_DebugPrintf("adjust mclk phase!\n");
933	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
934	DHL_SYS_ANXRead(0, HDMI_TX_I2S_CTRL_REG, &c1);
935
936	freq_mclk = c & 0x07;
937	switch(freq_mclk)
938	{
939	case HDMI_TX_mclk_128_Fs: //invert 0x50[3]
940	//HDMI_TX_DebugPrintf("adjust mclk phase when 128*Fs!\n");
941	if( c & 0x08 ) c &= 0xf7;
942	else c \|= 0x08;
943	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, c);
944	break;
945
946	case HDMI_TX_mclk_256_Fs:
947	case HDMI_TX_mclk_384_Fs:
948	//HDMI_TX_DebugPrintf("adjust mclk phase when 256Fs or 384Fs!\n");
949	if( c1 & 0x60 ) c1 &= 0x9f;
950	else c1 \|= 0x20;
951	DHL_SYS_ANXWrite(0, HDMI_TX_I2S_CTRL_REG, c1);
952	break;
953
954	case HDMI_TX_mclk_512_Fs:
955	//HDMI_TX_DebugPrintf("adjust mclk phase when 512*Fs!\n");
956	if( c1 & 0x60 ) c1 &= 0x9f;
957	else c1 \|= 0x40;
958	DHL_SYS_ANXWrite(0, HDMI_TX_I2S_CTRL_REG, c1);
959	break;
960	default:
961	break;
962
963	}
964	}
965	}
966	/*
967	void HDMI_TX_Rx_Sense_Interrupt(void)
968	{
969	BYTE c;
970
971	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG,&c);
972
973	if( c & HDMI_TX_SYS_STATE_RSV_DET)
974	{
975	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
976	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c \| 0x01);
977	}
978	else
979	{
980	// Rx is not active
981	if((HDMI_TX_system_state != HDMI_TX_INITIAL)
982	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
983	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID))
984	{
985	HDMI_TX_Set_System_State(HDMI_TX_WAIT_RX_SENSE);
986	//stop HDCP and reset DDC when lost Rx sense
987	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
988	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
989	HDMI_TX_RST_DDCChannel();
990	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
991	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c & 0xfd);
992	// mute TMDS link
993	HDMI_TX_MuteTMDS_CLK();
994	}
995	//Power down chip
996	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
997	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c & 0xfe);
998	}
999	}
1000	*/
1001
1002
1003	void HDMI_TX_Blue_Screen_Format_Config(void)
1004	{
1005	TT();
1006	switch (hdmi_tx_RGBorYCbCr)
1007	{
1008	case HDMI_TX_RGB: //select RGB mode
1009	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN0_REG, 0x00);
1010	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN1_REG, 0x00);
1011	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN2_REG, 0x00);
1012	break;
1013	case HDMI_TX_YCbCr422: //select YCbCr4:2:2 mode
1014	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN0_REG, 0x80);
1015	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN1_REG, 0x00);
1016	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN2_REG, 0x80);
1017	break;
1018	case HDMI_TX_YCbCr444: //select YCbCr4:4:4 mode
1019	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN0_REG, 0x80);
1020	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN1_REG, 0x00);
1021	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN2_REG, 0x80);
1022	break;
1023	default:
1024	break;
1025	}
1026	}
1027
1028	void HDMI_TX_Blue_Screen_Enable(void)
1029	{
1030	BYTE c;
1031	TT();
1032	HDMI_TX_Blue_Screen_Format_Config();
1033	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL1_REG, &c);
1034	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL1_REG, c \| HDMI_TX_HDCP_CTRL1_BLUE_SCREEN_EN);
1035	hdmi_tx_send_blue_screen = 1;
1036	}
1037
1038	void HDMI_TX_Blue_Screen_Disable(void)
1039	{
1040	BYTE c;
1041	TT();
1042	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL1_REG, &c);
1043	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL1_REG, (c & 0xfb));
1044	hdmi_tx_send_blue_screen = 0;
1045	}
1046
1047	void HDMI_TX_HDCP_Encryption_Enable(void)
1048	{
1049	BYTE c;
1050	TT();
1051	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
1052	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c \| HDMI_TX_HDCP_CTRL0_ENC_EN));
1053	hdmi_tx_hdcp_encryption = 1;
1054	DD_DISP_VideoMute(g_DispConfig.bVideoMute[0]); // mute »óÅÂ update
1055	}
1056
1057	void HDMI_TX_HDCP_Encryption_Disable(void)
1058	{
1059	BYTE c;
1060	TT();
1061	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
1062	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & 0xfb));
1063	hdmi_tx_hdcp_encryption = 0;
1064	DD_DISP_VideoMute(g_DispConfig.bVideoMute[0]);
1065	}
1066
1067	static unsigned long HDMI_TX_Get_TMDS_Clk(void)
1068	{
1069	//
1070	// Warning : please use this function after CONFIG_VIDEO
1071	//
1072	unsigned char c;
1073	unsigned int h_res, v_res, vid_type, c_depth;
1074	unsigned long tmds_clk;
1075
1076	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HRESH_REG, &c);
1077	h_res = c;
1078	h_res = h_res << 8;
1079	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HRESL_REG, &c);
1080	h_res = h_res + c;
1081	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VRESH_REG, &c);
1082	v_res = c;
1083	v_res = v_res << 8;
1084	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VRESL_REG, &c);
1085	v_res = v_res + c;
1086	DHL_SYS_ANXRead(0, HDMI_TX_VID_STATUS_REG, &c);
1087	if((c & HDMI_TX_VID_STATUS_TYPE) == 0x04)
1088	vid_type = 30;
1089	else
1090	vid_type = 60;
1091	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
1092	c = c & 0x60;
1093	if(c == 0x00)
1094	c_depth = 8;
1095	else if(c == 0x20)
1096	c_depth = 10;
1097	else if(c == 0x40)
1098	c_depth = 12;
1099
1100	tmds_clk = h_res * v_res * vid_type * c_depth / 8;
1101	fprintf(stderr, "\|%s, %d\| TMDS Clk = %ld\n", __FUNCTION__, __LINE__, tmds_clk);
1102
1103	return tmds_clk;
1104	}
1105
1106	void HDMI_TX_Do_Config_Video()
1107	{
1108	if( (HDMI_TX_system_state != HDMI_TX_INITIAL) && (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
1109	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID) && (hdmi_tx_system_config_video_done == 0))
1110	{
1111	//system should config all the parameters here
1112	HDMI_TX_DebugPrintf("******** system config video & packet here.\n");
1113	HDMI_TX_API_Video_Config(saved_hdmi_tx_video_timing_id,input_pixel_clk_1x_repeatition);
1114	HDMI_TX_API_Packets_Config(HDMI_TX_avi_sel);
1115	HDMI_TX_API_AVI_Config(YCbCr444,source_ratio,null,null,null,null,null,null,null,null,null,null,null);
1116
1117	switch (hdmi_tx_video_timing_id) {
1118	case hdmi_tx_V1920x1080i_60Hz:
1119	HDMI_TX_Config_Manual_Video_Format(2);
1120	HDMI_TX_Config_Auto_Video_Format();
1121	break;
1122	case hdmi_tx_V720x480p_60Hz_16x9:
1123	HDMI_TX_Config_Manual_Video_Format(3);
1124	HDMI_TX_Config_Auto_Video_Format();
1125	break;
1126	case hdmi_tx_V1280x720p_60Hz:
1127	HDMI_TX_Config_Manual_Video_Format(1);
1128	HDMI_TX_Config_Auto_Video_Format();
1129	break;
1130	case hdmi_tx_V1920x1080p_60Hz:
1131	HDMI_TX_Config_Manual_Video_Format(5);
1132	HDMI_TX_Config_Auto_Video_Format();
1133	break;
1134	default:
1135	HDMI_TX_Config_Auto_Video_Format();
1136	}
1137
1138	hdmi_tx_system_config_video_done = 1;
1139	}
1140	}
1141
1142	void HDMI_TX_Config_Video()
1143	{
1144	BYTE c;
1145	TT();
1146	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
1147	if(!(c & 0x02))
1148	{
1149	HDMI_TX_DebugPrintf("No clock detected !\n");
1150	return;
1151	}
1152
1153	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
1154	if(!(c & 0x40))
1155	{
1156	HDMI_TX_DebugPrintf("PLL not lock !\n");
1157	return;
1158	}
1159
1160	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
1161	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, c & 0xc3 );
1162	//set 24 bit mode
1163	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
1164	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, ((c & 0x9f) \| 0x00));
1165
1166	HDMI_TX_Do_Config_Video();
1167	HDMI_TX_Clean_HDCP();
1168
1169	if(hdmi_tx_de_gen_en)
1170	{
1171	HDMI_TX_DebugPrintf("hdmi_tx_de_gen_en!\n");
1172	HDMI_TX_DE_Generator();
1173	}
1174	if(hdmi_tx_emb_sync_mode)
1175	{
1176	HDMI_TX_DebugPrintf("HDMI_TX_Embed_Sync_Decode!\n");
1177	HDMI_TX_Embed_Sync_Decode();
1178	}
1179
1180	HDMI_TX_RepeatTimes_Setting();
1181
1182	//enable video input
1183	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
1184	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, c \| HDMI_TX_VID_CTRL_IN_EN);
1185
1186	DHL_SYS_ANXRead(0, HDMI_TX_VID_STATUS_REG, &c);
1187	if(!(c & HDMI_TX_VID_STATUS_VID_STABLE))
1188	{
1189	extern void DD_DISP_ResetOutput(void);
1190	HDMI_TX_DebugPrintf("Video not stable!\n");
1191	/*
1192	* Do reset here.
1193	*/
1194	DD_DISP_ResetOutput();
1195
1196	//extern void reset_crtc(void);
1197	//reset_crtc(); // ÀÓ½Ã·Î ¸¸µë, ÇØ´ç »óÈ²¿¡¼ P5_B8 register¸¦ 1 -> 0 -> 1ÇØÁÜ.
1198	//HDMI_TX_Show_Video_Parameter();
1199	return;
1200	}
1201
1202	HDMI_TX_CSCandColorDepth_Setting();
1203
1204	//Enable video CLK,Format change after config video.
1205	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c);
1206	DHL_SYS_ANXWrite(0,HDMI_TX_INTR1_MASK_REG, c \|0x01);//3
1207	DHL_SYS_ANXRead(0, HDMI_TX_INTR3_MASK_REG, &c);
1208	DHL_SYS_ANXWrite(0,HDMI_TX_INTR3_MASK_REG, c \| 0x40);
1209
1210
1211	if(hdmi_tx_edid_result.is_HDMI)
1212	{
1213	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c); //72:07.1=1 hdmi mode
1214	DHL_SYS_ANXWrite(0,HDMI_TX_SYS_CTRL1_REG, c \| 0x02);
1215	HDMI_TX_Config_Packet();
1216	OS_mDelay(4); //delay for RX to recover from DVI to HDMI
1217	}
1218
1219	//reset TMDS link to align 4 channels
1220	DHL_SYS_ANXRead(0, HDMI_TX_SRST_REG, &c); //toggle 72:05.6
1221	DHL_SYS_ANXWrite(0,HDMI_TX_SRST_REG, (c \| HDMI_TX_TMDS_CHNL_ALIGN));
1222	DHL_SYS_ANXWrite(0,HDMI_TX_SRST_REG, (c & (~HDMI_TX_TMDS_CHNL_ALIGN)));
1223
1224	#if 0
1225	//Enable TMDS clock output
1226	if (HDMI_TX_Get_TMDS_Clk() > 165000000)
1227	{
1228	HDMI_TX_Set_TMDS_Amp_HS(HDMI_TX_TMDS_AMP_620, HDMI_TX_TMDS_AMP_580, HDMI_TX_TMDS_AMP_580, HDMI_TX_TMDS_AMP_620);
1229	}
1230	else
1231	{
1232	HDMI_TX_Set_TMDS_Amp_LS(HDMI_TX_TMDS_AMP_500, HDMI_TX_TMDS_AMP_500, HDMI_TX_TMDS_AMP_500, HDMI_TX_TMDS_AMP_460);
1233	}
1234	#endif
1235	HDMI_TX_Set_TMDS_Amp_Internal();
1236	HDMI_TX_Set_TMDS_Emp_Internal();
1237
1238	if ( bExtSwing == 1 )
1239	DHL_SYS_ANXWrite(0, HDMI_TX_ANA_BLK_CTRL0_REG, HDMI_TX_ANA_BLK_CTRL0_ST_EN \| 0x05); // for video blinking problem...
1240	else
1241	DHL_SYS_ANXWrite(0, HDMI_TX_ANA_BLK_CTRL0_REG, HDMI_TX_ANA_BLK_CTRL0_ST_EN \| 0x01); // for video blinking problem...
1242
1243	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, &c);//72:99.7
1244	DHL_SYS_ANXWrite(0,HDMI_TX_TMDS_CLKCH_CONFIG_REG, (c \| HDMI_TX_TMDS_CLKCH_MUTE));
1245	DHL_SYS_ANXRead(0,HDMI_TX_GNRL_CTRL_PKT_REG, &c); //72:cc, hdcp required jh 07/24/07
1246	DHL_SYS_ANXWrite(0,HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0xfe) \| 0x02));
1247	//mute video so video will drive out but not showing on screen as required on HDCP
1248	DHL_SYS_ANXRead(0,HDMI_TX_GNRL_CTRL_PKT_REG, &c); //7A:cc.0 jh 01/22/08 jh
1249	DHL_SYS_ANXWrite(0,HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0xfd) \| 0x01)); //av_mute on
1250
1251	OS_mDelay(400); //will fit into exactly 500ms time delay for rx to switch from dvi to hdmi; jh 07/24/07 hdcp
1252	//HDMI_TX_Clean_HDCP();
1253	HDMI_TX_Set_System_State(HDMI_TX_HDCP_AUTHENTICATION);
1254	}
1255
1256	void HDMI_TX_Parse_Video_Format(void)
1257	{
1258	TT();
1259	switch(hdmi_tx_video_format_config)
1260	{
1261	case hdmi_tx_RGB_YCrCb444_SepSync:
1262	hdmi_tx_emb_sync_mode = 0;
1263	hdmi_tx_demux_yc_en = 0;
1264	hdmi_tx_ddr_bus_mode = 0;
1265	hdmi_tx_de_gen_en = 0;
1266	break;
1267	case hdmi_tx_YCrCb422_SepSync:
1268	hdmi_tx_emb_sync_mode = 0;
1269	hdmi_tx_demux_yc_en = 0;
1270	hdmi_tx_ddr_bus_mode = 0;
1271	hdmi_tx_de_gen_en = 0;
1272	break;
1273	case hdmi_tx_YCrCb422_EmbSync:
1274	hdmi_tx_demux_yc_en = 0;
1275	hdmi_tx_ddr_bus_mode = 0;
1276	hdmi_tx_de_gen_en = 0;
1277	hdmi_tx_emb_sync_mode = 1;
1278	//HDMI_TX_Get_Video_Timing();
1279	break;
1280	case hdmi_tx_YCMux422_SepSync_Mode1:
1281	hdmi_tx_emb_sync_mode = 0;
1282	hdmi_tx_ddr_bus_mode = 0;
1283	hdmi_tx_de_gen_en = 0;
1284	hdmi_tx_ycmux_BIT_sel = 0;
1285	hdmi_tx_demux_yc_en = 1;
1286	break;
1287	case hdmi_tx_YCMux422_SepSync_Mode2:
1288	hdmi_tx_emb_sync_mode = 0;
1289	hdmi_tx_ddr_bus_mode = 0;
1290	hdmi_tx_de_gen_en = 0;
1291	hdmi_tx_ycmux_BIT_sel = 1;
1292	hdmi_tx_demux_yc_en = 1;
1293	break;
1294	case hdmi_tx_YCMux422_SepSync_Mode3:
1295	hdmi_tx_emb_sync_mode = 0;
1296	hdmi_tx_ddr_bus_mode = 0;
1297	hdmi_tx_de_gen_en = 0;
1298	hdmi_tx_ycmux_BIT_sel = 2;
1299	hdmi_tx_demux_yc_en = 1;
1300	break;
1301	case hdmi_tx_YCMux422_EmbSync_Mode1:
1302	hdmi_tx_ddr_bus_mode = 0;
1303	hdmi_tx_de_gen_en = 0;
1304	hdmi_tx_emb_sync_mode = 1;
1305	hdmi_tx_ycmux_BIT_sel = 0;
1306	hdmi_tx_demux_yc_en = 1;
1307	//HDMI_TX_Get_Video_Timing();
1308	break;
1309	case hdmi_tx_YCMux422_EmbSync_Mode2:
1310	hdmi_tx_ddr_bus_mode = 0;
1311	hdmi_tx_de_gen_en = 0;
1312	hdmi_tx_emb_sync_mode = 1;
1313	hdmi_tx_ycmux_BIT_sel = 1;
1314	hdmi_tx_demux_yc_en = 1;
1315	//HDMI_TX_Get_Video_Timing();
1316	break;
1317	case hdmi_tx_YCMux422_EmbSync_Mode3:
1318	hdmi_tx_ddr_bus_mode = 0;
1319	hdmi_tx_de_gen_en = 0;
1320	hdmi_tx_emb_sync_mode = 1;
1321	hdmi_tx_ycmux_BIT_sel = 2;
1322	hdmi_tx_demux_yc_en = 1;
1323	//HDMI_TX_Get_Video_Timing();
1324	break;
1325	case hdmi_tx_RGB_YCrCb444_DDR_SepSync:
1326	hdmi_tx_emb_sync_mode = 0;
1327	hdmi_tx_demux_yc_en = 0;
1328	hdmi_tx_de_gen_en = 0;
1329	hdmi_tx_ddr_bus_mode = 1;
1330	break;
1331	case hdmi_tx_RGB_YCrCb444_DDR_EmbSync:
1332	hdmi_tx_demux_yc_en = 0;
1333	hdmi_tx_de_gen_en = 0;
1334	hdmi_tx_emb_sync_mode = 1;
1335	hdmi_tx_ddr_bus_mode = 1;
1336	//HDMI_TX_Get_Video_Timing();
1337	break;
1338	case hdmi_tx_RGB_YCrCb444_SepSync_No_DE:
1339	hdmi_tx_emb_sync_mode = 0;
1340	hdmi_tx_demux_yc_en = 0;
1341	hdmi_tx_ddr_bus_mode = 0;
1342	hdmi_tx_de_gen_en = 1;
1343	//HDMI_TX_Get_Video_Timing();
1344	break;
1345	case hdmi_tx_YCrCb422_SepSync_No_DE:
1346	hdmi_tx_emb_sync_mode = 0;
1347	hdmi_tx_demux_yc_en = 0;
1348	hdmi_tx_ddr_bus_mode = 0;
1349	hdmi_tx_de_gen_en = 1;
1350	//HDMI_TX_Get_Video_Timing();
1351	break;
1352	default:
1353	break;
1354	}
1355	}
1356
1357	void HDMI_TX_Get_Video_Timing()
1358	{
1359	BYTE i;
1360	TT();
1361	switch(hdmi_tx_video_timing_id)
1362	{
1363	case hdmi_tx_V640x480p_60Hz:
1364	i = 0;
1365	break;
1366	case hdmi_tx_V1280x720p_60Hz:
1367	i = 1;
1368	break;
1369	case hdmi_tx_V1920x1080i_60Hz:
1370	i = 2;
1371	break;
1372	case hdmi_tx_V720x480p_60Hz_4x3:
1373	case hdmi_tx_V720x480p_60Hz_16x9:
1374	i = 3;
1375	break;
1376	case hdmi_tx_V720x480i_60Hz_4x3:
1377	case hdmi_tx_V720x480i_60Hz_16x9:
1378	i = 4;
1379	break;
1380	case hdmi_tx_V1920x1080p_60Hz:
1381	i = 5;
1382	break;
1383	case hdmi_tx_V1920x1080p_50Hz:
1384	i = 6;
1385	break;
1386	case hdmi_tx_V1280x720p_50Hz:
1387	i = 7;
1388	break;
1389	case hdmi_tx_V1920x1080i_50Hz:
1390	i = 8;
1391	break;
1392	case hdmi_tx_V720x576p_50Hz_4x3:
1393	case hdmi_tx_V720x576p_50Hz_16x9:
1394	i = 9;
1395	break;
1396	case hdmi_tx_V720x576i_50Hz_4x3:
1397	case hdmi_tx_V720x576i_50Hz_16x9:
1398	i = 10;
1399	break;
1400	default:
1401	break;
1402	}
1403	hdmi_tx_h_total = _861_Video_Timing[i].h_total_length;
1404	hdmi_tx_h_active = _861_Video_Timing[i].h_active_length;
1405	hdmi_tx_v_total = _861_Video_Timing[i].v_total_length;
1406	hdmi_tx_v_active = _861_Video_Timing[i].v_active_length;
1407	hdmi_tx_h_fp = _861_Video_Timing[i].h_front_porch;
1408	hdmi_tx_hsync_width = _861_Video_Timing[i].h_sync_width;
1409	hdmi_tx_h_bp = _861_Video_Timing[i].h_back_porch;
1410	hdmi_tx_v_fp = _861_Video_Timing[i].v_front_porch;
1411	hdmi_tx_vsync_width = _861_Video_Timing[i].v_sync_width;
1412	hdmi_tx_v_bp = _861_Video_Timing[i].v_back_porch;
1413	hdmi_tx_hsync_polarity = _861_Video_Timing[i].h_sync_polarity;
1414	hdmi_tx_vsync_polarity = _861_Video_Timing[i].v_sync_polarity;
1415	hdmi_tx_type_I_P = _861_Video_Timing[i].is_interlaced;
1416	}
1417
1418	void HDMI_TX_DE_Generator()
1419	{
1420	BYTE c;
1421	TT();
1422	HDMI_TX_Get_Video_Timing();
1423
1424	if(hdmi_tx_demux_yc_en)
1425	{
1426	hdmi_tx_hsync_width = 2 * hdmi_tx_hsync_width;
1427	hdmi_tx_h_active = 2 * hdmi_tx_h_active;
1428	hdmi_tx_h_total = 2 * hdmi_tx_h_total;
1429	hdmi_tx_h_bp = 2 * hdmi_tx_h_bp;
1430	}
1431
1432	HDMI_TX_DebugPrintf("Output Mode > %s (%d)\n", hdmi_tx_type_I_P ? "Interlaced" : "Progressive", hdmi_tx_type_I_P);
1433	HDMI_TX_DebugPrintf("Sync Polarity> HSync: %s(%d), VSync: %s(%d)\n", !hdmi_tx_hsync_polarity ? "Positive" : "Negative", !hdmi_tx_hsync_polarity, hdmi_tx_vsync_polarity ? "Positive" : "Negative", hdmi_tx_vsync_polarity);
1434	HDMI_TX_DebugPrintf("Vertical > Total: %4d Active: %4d VSyncWidth: %3d VBporch: %3d\n", hdmi_tx_v_total, hdmi_tx_v_active, hdmi_tx_vsync_width, hdmi_tx_v_bp);
1435	HDMI_TX_DebugPrintf("Horizontal > Total: %4d Active: %4d HSyncWidth: %3d HBporch: %3d\n", hdmi_tx_h_total, hdmi_tx_h_active, hdmi_tx_hsync_width, hdmi_tx_h_bp);
1436
1437	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1438	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xf7) \|hdmi_tx_type_I_P << 3);//set video type //wen
1439	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1440	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xdf) \|hdmi_tx_hsync_polarity << 5);//set HSYNC polarity //wen
1441	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1442	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xbf) \|hdmi_tx_vsync_polarity << 6);//set VSYNC polarity //wen
1443	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEL_REG, hdmi_tx_v_active & 0xff);
1444	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEH_REG, hdmi_tx_v_active >> 8);
1445	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_WID_REG, hdmi_tx_vsync_width);
1446	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_TAIL2VIDLINE_REG, hdmi_tx_v_bp);
1447	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXL_REG, hdmi_tx_h_active & 0xff);
1448	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXH_REG, hdmi_tx_h_active >> 8);
1449	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESL_REG, hdmi_tx_h_total & 0xff);
1450	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESH_REG, hdmi_tx_h_total >> 8);
1451	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, hdmi_tx_hsync_width & 0xff);
1452	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, hdmi_tx_hsync_width >> 8);
1453	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHL_REG, hdmi_tx_h_bp & 0xff);
1454	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHH_REG, hdmi_tx_h_bp >> 8);
1455	}
1456
1457	void HDMI_TX_Show_DE_Gen(void)
1458	{
1459	WORD vTotal, vActive, vSync, vBp;
1460	WORD hTotal, hActive, hSync, hBp;
1461	BYTE hSyncPol, vSyncPol, bProgressive;
1462	BYTE temp;
1463
1464	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &temp);
1465	bProgressive = (temp & 0x08)>>3;
1466	hSyncPol = (temp & 0x20)>>5;
1467	vSyncPol = (temp & 0x40)>>6;
1468
1469	DHL_SYS_ANXRead(0, HDMI_TX_ACT_LINEL_REG, &temp);
1470	vActive = temp;
1471	DHL_SYS_ANXRead(0, HDMI_TX_ACT_LINEH_REG, &temp);
1472	vActive += (temp<<8);
1473	DHL_SYS_ANXRead(0, HDMI_TX_VSYNC_WID_REG, &temp);
1474	vSync = temp;
1475	DHL_SYS_ANXRead(0, HDMI_TX_VSYNC_TAIL2VIDLINE_REG, &temp);
1476	vBp = temp;
1477
1478	DHL_SYS_ANXRead(0, HDMI_TX_VID_PIXL_REG, &temp);
1479	hActive = temp;
1480	DHL_SYS_ANXRead(0, HDMI_TX_VID_PIXH_REG, &temp);
1481	hActive += temp<<8;
1482
1483	DHL_SYS_ANXRead(0, HDMI_TX_H_RESL_REG, &temp);
1484	hTotal = temp;
1485	DHL_SYS_ANXRead(0, HDMI_TX_H_RESH_REG, &temp);
1486	hTotal += temp<<8;
1487
1488	DHL_SYS_ANXRead(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, &temp);
1489	hSync = temp;
1490	DHL_SYS_ANXRead(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, &temp);
1491	hSync += temp<<8;
1492
1493	DHL_SYS_ANXRead(0, HDMI_TX_H_BACKPORCHL_REG, &temp);
1494	hBp = temp;
1495	DHL_SYS_ANXRead(0, HDMI_TX_H_BACKPORCHH_REG, &temp);
1496	hBp += temp<<8;
1497
1498	HDMI_TX_DebugPrintf("Output Mode > %s (%d)\n", bProgressive ? "Interlaced" : "Progressive", bProgressive);
1499	HDMI_TX_DebugPrintf("Sync Polarity> HSync: %s(%d), VSync: %s(%d)\n", !hSyncPol ? "Positive" : "Negative", hSyncPol, !vSyncPol ? "Positive" : "Negative", vSyncPol);
1500	HDMI_TX_DebugPrintf("Vertical > Total: %4d Active: %4d VSyncWidth: %3d VBporch: %3d\n", vTotal, vActive, vSync, vBp);
1501	HDMI_TX_DebugPrintf("Horizontal > Total: %4d Active: %4d HSyncWidth: %3d HBporch: %3d\n", hTotal, hActive, hSync, hBp);
1502	}
1503
1504	void HDMI_TX_Embed_Sync_Decode()
1505	{
1506	BYTE c;
1507	TT();
1508	HDMI_TX_Get_Video_Timing();
1509
1510	if(hdmi_tx_demux_yc_en)
1511	{
1512	HDMI_TX_DebugPrintf("656: double h_fp and hsync_wid for yc_mux!\n");
1513	hdmi_tx_h_fp = 2 * hdmi_tx_h_fp;
1514	hdmi_tx_hsync_width = 2 * hdmi_tx_hsync_width;
1515	}
1516
1517	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1518	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xf7) \|hdmi_tx_type_I_P << 3);//set video type
1519	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1520	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xdf) \|hdmi_tx_hsync_polarity << 5);//set HSYNC polarity
1521	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
1522	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c&0xbf) \|hdmi_tx_vsync_polarity << 6);//set VSYNC polarity
1523	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINE2VSYNC_REG, hdmi_tx_v_fp);
1524	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_WID_REG, hdmi_tx_vsync_width);
1525	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHL_REG, hdmi_tx_h_fp & 0xff);
1526	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHH_REG, hdmi_tx_h_fp >> 8);
1527	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, hdmi_tx_hsync_width & 0xff);
1528	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, hdmi_tx_hsync_width >> 8);
1529	}
1530
1531	void HDMI_TX_Show_Video_Parameter()
1532	{
1533	int h_res,h_act,v_res,v_act,h_fp,hsync_width,h_bp;
1534	BYTE c;
1535	TT();
1536
1537	HDMI_TX_DebugPrintf("*********************************HDMI_TX Info**********************************\n");
1538	if(BIST_EN)
1539	HDMI_TX_DebugPrintf(" HDMI_TX mode = BIST mode\n");
1540	else
1541	{
1542	HDMI_TX_DebugPrintf(" HDMI_TX mode = Normal mode\n");
1543	if((hdmi_tx_demux_yc_en == 1) && (hdmi_tx_emb_sync_mode == 0))
1544	HDMI_TX_DebugPrintf(" Input video format = YC_MUX\n");
1545	if((hdmi_tx_demux_yc_en == 0) && (hdmi_tx_emb_sync_mode == 1))
1546	HDMI_TX_DebugPrintf(" Input video format = 656\n");
1547	if((hdmi_tx_demux_yc_en == 1) && (hdmi_tx_emb_sync_mode == 1))
1548	HDMI_TX_DebugPrintf(" Input video format = YC_MUX + 656\n");
1549	if((hdmi_tx_demux_yc_en == 0) && (hdmi_tx_emb_sync_mode == 0))
1550	HDMI_TX_DebugPrintf(" Input video format = Seperate Sync\n");
1551	if(hdmi_tx_de_gen_en)
1552	HDMI_TX_DebugPrintf(" DE generator = Enable\n");
1553	else
1554	HDMI_TX_DebugPrintf(" DE generator = Disable\n");
1555	if(hdmi_tx_ddr_bus_mode)
1556	HDMI_TX_DebugPrintf(" DDR mode = Enable\n");
1557	else
1558	HDMI_TX_DebugPrintf(" DDR mode = Disable\n");
1559	}
1560	switch(hdmi_tx_input_csc)
1561	{
1562	case HDMI_TX_RGB:
1563	HDMI_TX_DebugPrintf(" Input video color format = RGB\n");
1564	break;
1565	case HDMI_TX_YCbCr422:
1566	HDMI_TX_DebugPrintf(" Input video color format = YCbCr422\n");
1567	break;
1568	case HDMI_TX_YCbCr444:
1569	HDMI_TX_DebugPrintf(" Input video color format = YCbCr444\n");
1570	break;
1571	default:
1572	break;
1573	}
1574	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
1575	c = (c & 0x02);
1576	if(c)
1577	{
1578	HDMI_TX_DebugPrintf(" Output video mode = HDMI\n");
1579	DHL_SYS_ANXRead(1,0x04, &c);
1580	c = (c & 0x60) >> 5;
1581	switch(c)
1582	{
1583	case HDMI_TX_RGB:
1584	HDMI_TX_DebugPrintf(" Output video color format = RGB\n");
1585	break;
1586	case HDMI_TX_YCbCr422:
1587	HDMI_TX_DebugPrintf(" Output video color format = YCbCr422\n");
1588	break;
1589	case HDMI_TX_YCbCr444:
1590	HDMI_TX_DebugPrintf(" Output video color format = YCbCr444\n");
1591	break;
1592	default:
1593	break;
1594	}
1595	}
1596	else
1597	{
1598	HDMI_TX_DebugPrintf(" Output video mode = DVI\n");
1599	HDMI_TX_DebugPrintf(" Output video color format = RGB\n");
1600	}
1601
1602	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
1603	c = c & 0x60;
1604	if(c == 0x00)
1605	HDMI_TX_DebugPrintf(" Output color depth = 24bits\n");
1606	else if(c == 0x20)
1607	HDMI_TX_DebugPrintf(" Output color depth = 30bits\n");
1608	else if(c == 0x40)
1609	HDMI_TX_DebugPrintf(" Output color depth = 36bits\n");
1610	/* BYTE i;
1611	for(i = 0x10; i < 0x25; i ++)
1612	{
1613	DHL_SYS_ANXRead(0, i, &c );
1614	HDMI_TX_DebugPrintf("0x%.2x = 0x%.2x\n",(unsigned int)i,(unsigned int)c);
1615	}*/
1616	DHL_SYS_ANXRead(0, HDMI_TX_VID_STATUS_REG, &c);
1617	if((c & HDMI_TX_VID_STATUS_TYPE) == 0x04)
1618	HDMI_TX_DebugPrintf("Video Type = Interlace\n");
1619	else
1620	HDMI_TX_DebugPrintf("Video Type = Progressive\n");
1621	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HRESH_REG, &c);
1622	h_res = c;
1623	h_res = h_res << 8;
1624	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HRESL_REG, &c);
1625	h_res = h_res + c;
1626	HDMI_TX_DebugPrintf("H_resolution = %u\n",h_res);
1627	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_PIXH_REG, &c);
1628	h_act = c;
1629	h_act = h_act << 8;
1630	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_PIXL_REG, &c);
1631	h_act = h_act + c;
1632	HDMI_TX_DebugPrintf("H_active = %u\n",h_act);
1633
1634	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VRESH_REG, &c);
1635	v_res = c;
1636	v_res = v_res << 8;
1637	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VRESL_REG, &c);
1638	v_res = v_res + c;
1639	HDMI_TX_DebugPrintf("V_resolution = %u\n",v_res);
1640	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_ACTVIDLINEH_REG, &c);
1641	v_act = c;
1642	v_act = v_act << 8;
1643	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_ACTVIDLINEL_REG, &c);
1644	v_act = v_act + c;
1645	HDMI_TX_DebugPrintf("V_active = %u\n",v_act);
1646
1647	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HFORNTPORCHH_REG, &c);
1648	h_fp = c;
1649	h_fp = h_fp << 8;
1650	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HFORNTPORCHL_REG, &c);
1651	h_fp = h_fp + c;
1652	HDMI_TX_DebugPrintf("H_FP = %u\n",h_fp);
1653
1654	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HBACKPORCHH_REG, &c);
1655	h_bp = c;
1656	h_bp = h_bp << 8;
1657	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HBACKPORCHL_REG, &c);
1658	h_bp = h_bp + c;
1659	HDMI_TX_DebugPrintf("H_BP = %u\n",h_bp);
1660
1661	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HSYNCWIDH_REG, &c);
1662	hsync_width = c;
1663	hsync_width = hsync_width << 8;
1664	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_HSYNCWIDL_REG, &c);
1665	hsync_width = hsync_width + c;
1666	HDMI_TX_DebugPrintf("Hsync_width = %u\n",hsync_width);
1667
1668	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_ACTLINE2VSYNC_REG, &c);
1669	HDMI_TX_DebugPrintf("Vsync_FP = %du\n",c);
1670
1671	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VSYNCTAIL2VIDLINE_REG, &c);
1672	HDMI_TX_DebugPrintf("Vsync_BP = %du\n",c);
1673
1674	DHL_SYS_ANXRead(0, HDMI_TX_VIDF_VSYNCWIDLINE_REG, &c);
1675	HDMI_TX_DebugPrintf("Vsync_width = %du\n",c);
1676	HDMI_TX_DebugPrintf("\n");
1677
1678	if(BIST_EN)
1679	{
1680	HDMI_TX_DebugPrintf(" BIST mode output video format is \n");
1681	if(HDMI_TX_CLK_SOURCE)
1682	{
1683	switch(switch_value)
1684	{
1685	case 0:
1686	HDMI_TX_DebugPrintf("640x480p@60, \n");
1687	if(hdmi_tx_edid_result.supported_640x480p_60Hz \|\|hdmi_tx_edid_result.supported_720x480p_60Hz)
1688	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1689	else
1690	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1691	break;
1692	case 1:
1693	HDMI_TX_DebugPrintf("1280x720p@60, \n");
1694	if(hdmi_tx_edid_result.supported_720p_60Hz)
1695	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1696	else
1697	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1698	break;
1699	case 2:
1700	HDMI_TX_DebugPrintf("1920x1080i@60, \n");
1701	if(hdmi_tx_edid_result.supported_1080i_60Hz)
1702	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1703	else
1704	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1705	break;
1706	case 3:
1707	HDMI_TX_DebugPrintf("720x480p@60, \n");
1708	if(hdmi_tx_edid_result.supported_720x480p_60Hz)
1709	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1710	else
1711	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1712	break;
1713	case 4:
1714	HDMI_TX_DebugPrintf("720x480ip@60, \n");
1715	if(hdmi_tx_edid_result.supported_720x480i_60Hz)
1716	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1717	else
1718	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1719	break;
1720	case 5:
1721	HDMI_TX_DebugPrintf("1920x1080p@60, \n");
1722	if(hdmi_tx_edid_result.supported_1080p_60Hz)
1723	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1724	else
1725	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1726	break;
1727	case 6:
1728	HDMI_TX_DebugPrintf("1920x1080p@50, \n");
1729	if(hdmi_tx_edid_result.supported_1080p_50Hz)
1730	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1731	else
1732	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1733	break;
1734	case 7:
1735	HDMI_TX_DebugPrintf("1280x720p@50, \n");
1736	if(hdmi_tx_edid_result.supported_720p_50Hz)
1737	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1738	else
1739	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1740	break;
1741	case 8:
1742	HDMI_TX_DebugPrintf("1920x1080i@50, \n");
1743	if(hdmi_tx_edid_result.supported_1080i_50Hz)
1744	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1745	else
1746	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1747	break;
1748	case 9:
1749	HDMI_TX_DebugPrintf("720x576p@50, \n");
1750	if(hdmi_tx_edid_result.supported_576p_50Hz)
1751	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1752	else
1753	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1754	break;
1755	case 10:
1756	HDMI_TX_DebugPrintf("720x576i@50, \n");
1757	if(hdmi_tx_edid_result.supported_576i_50Hz)
1758	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1759	else
1760	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1761	break;
1762	default:
1763	HDMI_TX_DebugPrintf("unknown.\n");
1764	break;
1765	}
1766	}
1767	else
1768	{
1769	HDMI_TX_DebugPrintf("1280x720p@60, \n");
1770	if(hdmi_tx_edid_result.supported_720p_60Hz)
1771	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1772	else
1773	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1774	}
1775	}
1776	else
1777	{
1778	HDMI_TX_DebugPrintf(" Normal mode output video format is \n");
1779	switch(hdmi_tx_video_timing_id)
1780	{
1781	case hdmi_tx_V720x480p_60Hz_4x3:
1782	case hdmi_tx_V720x480p_60Hz_16x9:
1783	HDMI_TX_DebugPrintf("720x480p@60, \n");
1784	if(hdmi_tx_edid_result.supported_720x480p_60Hz)
1785	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1786	else
1787	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1788	break;
1789	case hdmi_tx_V1280x720p_60Hz:
1790	HDMI_TX_DebugPrintf("1280x720p@60, \n");
1791	if(hdmi_tx_edid_result.supported_720p_60Hz)
1792	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1793	else
1794	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1795	break;
1796	case hdmi_tx_V1920x1080i_60Hz:
1797	HDMI_TX_DebugPrintf("1920x1080i@60, \n");
1798	if(hdmi_tx_edid_result.supported_1080i_60Hz)
1799	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1800	else
1801	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1802	break;
1803	case hdmi_tx_V1920x1080p_60Hz:
1804	HDMI_TX_DebugPrintf("1920x1080p@60, \n");
1805	if(hdmi_tx_edid_result.supported_1080p_60Hz)
1806	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1807	else
1808	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1809	break;
1810	case hdmi_tx_V1920x1080p_50Hz:
1811	HDMI_TX_DebugPrintf("1920x1080p@50, \n");
1812	if(hdmi_tx_edid_result.supported_1080p_50Hz)
1813	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1814	else
1815	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1816	break;
1817	case hdmi_tx_V1280x720p_50Hz:
1818	HDMI_TX_DebugPrintf("1280x720p@50, \n");
1819	if(hdmi_tx_edid_result.supported_720p_50Hz)
1820	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1821	else
1822	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1823	break;
1824	case hdmi_tx_V1920x1080i_50Hz:
1825	HDMI_TX_DebugPrintf("1920x1080i@50, \n");
1826	if(hdmi_tx_edid_result.supported_1080i_50Hz)
1827	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1828	else
1829	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1830	break;
1831	case hdmi_tx_V720x576p_50Hz_4x3:
1832	case hdmi_tx_V720x576p_50Hz_16x9:
1833	HDMI_TX_DebugPrintf("720x576p@50, \n");
1834	if(hdmi_tx_edid_result.supported_576p_50Hz)
1835	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1836	else
1837	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1838	break;
1839	case hdmi_tx_V720x576i_50Hz_4x3:
1840	case hdmi_tx_V720x576i_50Hz_16x9:
1841	HDMI_TX_DebugPrintf("720x576i@50, \n");
1842	if(hdmi_tx_edid_result.supported_576i_50Hz)
1843	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1844	else
1845	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1846	break;
1847	case hdmi_tx_V720x480i_60Hz_4x3:
1848	case hdmi_tx_V720x480i_60Hz_16x9:
1849	HDMI_TX_DebugPrintf("720x480i@60, \n");
1850	if(hdmi_tx_edid_result.supported_720x480i_60Hz)
1851	HDMI_TX_DebugPrintf("and sink supports this format.\n");
1852	else
1853	HDMI_TX_DebugPrintf("but sink does not support this format.\n");
1854	break;
1855	default:
1856	HDMI_TX_DebugPrintf("unknown(video ID is: %.2x).\n",(WORD)hdmi_tx_video_timing_id);
1857	break;
1858	}
1859	}
1860	HDMI_TX_DebugPrintf("********************************HDMI_TX Info***********************************\n");
1861
1862	printf("\|HDMI-Tx End\| Tick = %lx\n", OS_GetTickCount());
1863	}
1864
1865
1866	void HDMI_TX_Do_Config_Audio()
1867	{
1868	if((HDMI_TX_system_state != HDMI_TX_INITIAL) && (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
1869	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID) && (HDMI_TX_system_state != HDMI_TX_CONFIG_VIDEO)
1870	&& (HDMI_TX_system_state != HDMI_TX_HDCP_AUTHENTICATION) && (hdmi_tx_system_config_audio_done == 0))
1871	{
1872	//system should config all the parameters here
1873	HDMI_TX_DebugPrintf("******** system config audio & packet here.\n");
1874	HDMI_TX_API_Packets_Config(HDMI_TX_audio_sel);
1875	if(HDMI_TX_API_GetGamutStatus() == _TRUE_){
1876	fprintf(stderr,"******** if it exist gamut data setup & send here\n");
1877	HDMI_TX_API_Packets_Config(HDMI_TX_audio_sel \| 0x80);
1878	}
1879	HDMI_TX_API_AUD_INFO_Config(null,null,null,null,null,null,null,null,null,null);
1880	HDMI_TX_API_AUD_CHStatus_Config(null,null,null,null,null,null,null,null,null,HDMI_TX_AUD_Fs);
1881	hdmi_tx_system_config_audio_done = 1;
1882
1883	}
1884	}
1885
1886	BYTE HDMI_TX_Config_Audio()
1887	{
1888	BYTE exe_result = 0x00;
1889	BYTE c = 0x00;
1890	BYTE audio_layout = 0x00;
1891	BYTE fs = 0x00;
1892	WORD ACR_N = 0x0000;
1893	TT();
1894	if(!hdmi_tx_system_config_audio_done)
1895	{
1896	//HDMI_TX_DebugPrintf("System has not finished config!\n");
1897	HDMI_TX_Do_Config_Audio();
1898	}
1899
1900	if ( hdmi_tx_audio_input == 0x01 /* I2S*/) {
1901	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
1902	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, (c \| 0x10));
1903	} else {
1904	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
1905	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, (c & 0xef));
1906	}
1907	HDMI_TX_DebugPrintf("audio_type = 0x%.2x\n",(WORD)s_hdmi_tx_audio_config.audio_type);
1908	if (s_hdmi_tx_audio_config.audio_type & HDMI_TX_i2s_input)
1909	{
1910	exe_result \|= HDMI_TX_Config_I2s();
1911	}
1912	else
1913	{
1914	//disable I2S audio input
1915	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
1916	c &= 0xc3;
1917	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
1918	}
1919
1920	if (s_hdmi_tx_audio_config.audio_type & HDMI_TX_spdif_input)
1921	{
1922	exe_result \|= HDMI_TX_Config_Spdif();
1923	}
1924	else
1925	{
1926	//disable SPDIF audio input
1927	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
1928	c &= ~HDMI_TX_HDMI_AUDCTRL1_SPDIFIN_EN;
1929	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
1930
1931	}
1932
1933	if (s_hdmi_tx_audio_config.audio_type & HDMI_TX_super_audio_input)
1934	{
1935	exe_result \|= HDMI_TX_Config_Super_Audio();
1936	}
1937	else
1938	{
1939	//disable super audio output
1940	DHL_SYS_ANXWrite(0, HDMI_TX_ONEBIT_AUD_CTRL_REG, 0x00);
1941	}
1942
1943	if ((s_hdmi_tx_audio_config.audio_type & 0x07) == 0x00)
1944	{
1945	;
1946	}
1947
1948	//audio layout
1949	if (s_hdmi_tx_audio_config.audio_type & HDMI_TX_i2s_input)
1950	{
1951	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
1952	if( c & 0x38) //BIT[5:3]
1953	{
1954	audio_layout = 0x80;
1955	}
1956	}
1957	if (s_hdmi_tx_audio_config.audio_type & HDMI_TX_super_audio_input)
1958	{
1959	DHL_SYS_ANXRead(0, HDMI_TX_ONEBIT_AUD_CTRL_REG, &c);
1960	if( c & 0xfc) //BIT[5:3]
1961	{
1962	audio_layout = 0x80;
1963	}
1964	}
1965
1966	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
1967	c \|= audio_layout;
1968	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, c);
1969
1970	if( (s_hdmi_tx_audio_config.audio_type & 0x07) == exe_result )
1971	{
1972	//Initial N value
1973
1974	DHL_SYS_ANXRead(0, HDMI_TX_I2SCH_STATUS4_REG, &c);
1975	fs = c & 0x0f;
1976	// set default value to N
1977	ACR_N = HDMI_TX_N_48k;
1978	switch(fs)
1979	{
1980	case(0x00)://44.1k
1981	ACR_N = HDMI_TX_N_44k;
1982	break;
1983	case(0x02)://48k
1984	ACR_N = HDMI_TX_N_48k;
1985	break;
1986	case(0x03)://32k
1987	ACR_N = HDMI_TX_N_32k;
1988	break;
1989	case(0x08)://88k
1990	ACR_N = HDMI_TX_N_88k;
1991	break;
1992	case(0x0a)://96k
1993	ACR_N = HDMI_TX_N_96k;
1994	break;
1995	case(0x0c)://176k
1996	ACR_N = HDMI_TX_N_176k;
1997	break;
1998	case(0x0e)://192k
1999	ACR_N = HDMI_TX_N_192k;
2000	break;
2001	default:
2002	break;
2003	}
2004	// write N(ACR) to corresponding regs
2005	c = ACR_N;
2006	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N1_SW_REG, c);
2007	c = ACR_N>>8;
2008	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N2_SW_REG, c);
2009
2010	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N3_SW_REG, 0x00);
2011
2012	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
2013	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, (c & 0xf8) \| FREQ_MCLK);
2014	HDMI_TX_DebugPrintf("Audio MCLK input mode is: %.2x\n",(WORD)FREQ_MCLK);
2015
2016	//Enable control of ACR
2017	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2018	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, (c \| HDMI_TX_INFO_PKTCTRL1_ACR_EN));
2019
2020	//audio enable:
2021	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2022	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
2023	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2024
2025	if (hdmi_tx_audio_input == 0x01) {
2026	DHL_SYS_ANXRead(1, HDMI_TX_ACR_CTS_CTRL_REG, &c);
2027	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_CTS_CTRL_REG, (c \| 0x02));
2028
2029	DHL_SYS_ANXRead(0, HDMI_TX_I2SCH_STATUS4_REG, &c);
2030	c &= 0x0F;
2031	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS4_REG, c\|0x02 );
2032	}
2033	}
2034
2035	HDMI_TX_Config_Packet();
2036
2037	// enable audio // to avoid enable audio in playback state
2038	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2039	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, (c \| HDMI_TX_HDMI_AUDCTRL1_IN_EN));
2040
2041	HDMI_TX_Set_System_State(HDMI_TX_PLAY_BACK);
2042	HDMI_TX_Clear_AVMute();
2043	HDMI_TX_Show_Video_Parameter();
2044	return exe_result;
2045	}
2046
2047	BYTE HDMI_TX_Config_I2s()
2048	{
2049	BYTE exe_result = 0x00;
2050	BYTE c = 0x00;
2051	BYTE c1 = 0x00;
2052	TT();
2053	//select SCK as source
2054	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2055	c &= ~HDMI_TX_HDMI_AUDCTRL1_CLK_SEL0;
2056	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2057	DHL_SYS_ANXRead(0, HDMI_TX_AUD_CTRL2_REG, &c);
2058	c &= ~HDMI_TX_AUD_CTRL2_AUD_CLK_SEL1;
2059	DHL_SYS_ANXWrite(0, HDMI_TX_AUD_CTRL2_REG, c);
2060	//HDMI_TX_DebugPrintf("select SCK as source.\n");
2061
2062	//config i2s channel
2063	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2064	c1 = s_hdmi_tx_audio_config.i2s_config.audio_channel; // need BYTE[5:2]
2065	c1 &= 0x3c;
2066	c &= ~0x3c;
2067	c \|= c1;
2068	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2069	//HDMI_TX_DebugPrintf("config i2s channel, c = 0x%.2x\n",(WORD)c);
2070
2071	//config i2s format
2072	c = s_hdmi_tx_audio_config.i2s_config.i2s_format;
2073	DHL_SYS_ANXWrite(0, HDMI_TX_I2S_CTRL_REG, c);
2074	//HDMI_TX_DebugPrintf("config i2s format, c = 0x%.2x\n",(WORD)c);
2075
2076	//down sample
2077	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
2078	c1 = s_hdmi_tx_audio_config.down_sample;
2079	c1 &= 0x60;
2080	c &= ~0x60;
2081	c \|= c1;
2082	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, c);
2083	//HDMI_TX_DebugPrintf("down sample, c = 0x%.2x\n",(WORD)c);
2084
2085	//config i2s channel status(5 regs)
2086	c = s_hdmi_tx_audio_config.i2s_config.Channel_status1;
2087	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS1_REG, c);
2088	c = s_hdmi_tx_audio_config.i2s_config.Channel_status2;
2089	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS2_REG, c);
2090	c = s_hdmi_tx_audio_config.i2s_config.Channel_status3;
2091	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS3_REG, c);
2092	c = s_hdmi_tx_audio_config.i2s_config.Channel_status4;
2093	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS4_REG, c);
2094	c = s_hdmi_tx_audio_config.i2s_config.Channel_status5;
2095	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS5_REG, c);
2096	//HDMI_TX_DebugPrintf("config i2s channel status, c = 0x%.2x\n",(WORD)c);
2097
2098	exe_result = HDMI_TX_i2s_input;
2099
2100	// open corresponding interrupt
2101	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c);
2102	DHL_SYS_ANXWrite(0, HDMI_TX_INTR1_MASK_REG, (c \| 0x22) );
2103	DHL_SYS_ANXRead(0, HDMI_TX_INTR3_MASK_REG, &c);
2104	DHL_SYS_ANXWrite(0, HDMI_TX_INTR3_MASK_REG, (c \| 0x20) );
2105
2106	return exe_result;
2107	}
2108
2109	void HDMI_TX_EnableSPDIFRx(int En)
2110	{
2111	BYTE c;
2112
2113	g_SPDIFRX_Enable = En;
2114
2115	DHL_SYS_ANXRead(0, HDMI_TX_SRST_REG, &c);
2116
2117	if ( En )
2118	c &= ~HDMI_TX_SRST_AUD_RST;
2119	else
2120	c \|= HDMI_TX_SRST_AUD_RST;
2121
2122	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, c);
2123	}
2124
2125	BYTE HDMI_TX_Config_Spdif()
2126	{
2127	BYTE exe_result = 0x00;
2128	BYTE c = 0x00;
2129	BYTE c1 = 0x00;
2130	// BYTE c2 = 0x00;
2131	// BYTE freq_mclk = 0x00;
2132	TT();
2133	//Select MCLK
2134	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2135	c \|= HDMI_TX_HDMI_AUDCTRL1_CLK_SEL0;
2136	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2137	DHL_SYS_ANXRead(0, HDMI_TX_AUD_CTRL2_REG, &c);
2138	c &= ~ HDMI_TX_AUD_CTRL2_AUD_CLK_SEL1;
2139	DHL_SYS_ANXWrite(0, HDMI_TX_AUD_CTRL2_REG, c);
2140	//Enable SPDIF
2141	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2142	c \|= HDMI_TX_HDMI_AUDCTRL1_SPDIFIN_EN;
2143	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2144
2145	//adjust MCLK phase in interrupt routine
2146
2147	// adjust FS_FREQ //FS_FREQ
2148	c1 = s_hdmi_tx_audio_config.i2s_config.Channel_status4 & 0x0f;
2149	DHL_SYS_ANXRead(0, HDMI_TX_SPDIFCH_STATUS_REG, &c);
2150	c &= HDMI_TX_SPDIFCH_STATUS_FS_FREG;
2151	c = c >> 4;
2152
2153	if( c != c1)
2154	{
2155	DHL_SYS_ANXRead(0, HDMI_TX_I2SCH_STATUS4_REG, &c);
2156	c &= 0xf0;
2157	c \|= c1;
2158	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS4_REG, c);
2159
2160	//enable using FS_FREQ from 0x59
2161	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2162	c \|= 0x02;
2163	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2164	}
2165
2166	// down sample
2167	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
2168	c1 = s_hdmi_tx_audio_config.down_sample;
2169	c1 &= 0x60;
2170	c &= ~0x60;
2171	c \|= c1;
2172	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, c);
2173
2174	if(s_hdmi_tx_audio_config.down_sample)
2175	{
2176	// adjust FS_FREQ by system because down sample
2177
2178	c1 = s_hdmi_tx_audio_config.i2s_config.Channel_status4 & 0x0f;;
2179	DHL_SYS_ANXRead(0, HDMI_TX_I2SCH_STATUS4_REG, &c);
2180	c &= 0xf0;
2181	c \|= c1;
2182	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS4_REG, c);
2183	}
2184
2185
2186	// spdif is stable
2187	exe_result = HDMI_TX_spdif_input;
2188
2189	// open corresponding interrupt
2190	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c);
2191	DHL_SYS_ANXWrite(0, HDMI_TX_INTR1_MASK_REG, (c \| 0x32) );
2192	DHL_SYS_ANXRead(0, HDMI_TX_INTR3_MASK_REG, &c);
2193	DHL_SYS_ANXWrite(0, HDMI_TX_INTR3_MASK_REG, (c \| 0xa1) );
2194
2195	DHL_SYS_ANXWrite(0, HDMI_TX_SPDIF_ERR_THRSHLD_REG, 0x80);
2196	return exe_result;
2197	}
2198
2199	BYTE HDMI_TX_Config_Super_Audio()
2200	{
2201	BYTE exe_result = 0x00;
2202	BYTE c = 0x00;
2203	TT();
2204	//select SCK as source
2205	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2206	c &= ~HDMI_TX_HDMI_AUDCTRL1_CLK_SEL0;
2207	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
2208	DHL_SYS_ANXRead(0, HDMI_TX_AUD_CTRL2_REG, &c);
2209	c &= ~HDMI_TX_AUD_CTRL2_AUD_CLK_SEL1;
2210	DHL_SYS_ANXWrite(0, HDMI_TX_AUD_CTRL2_REG, c);
2211
2212	// Enable stream 0x60
2213	c = s_hdmi_tx_audio_config.super_audio_config.one_BIT_ctrl;
2214	DHL_SYS_ANXWrite(0, HDMI_TX_ONEBIT_AUD_CTRL_REG, c);
2215
2216	exe_result = HDMI_TX_super_audio_input;
2217	return exe_result;
2218
2219	}
2220
2221	void set_format(int i)
2222	{
2223	TT();
2224	hdmi_tx_RGBorYCbCr = i;
2225	}
2226	BYTE HDMI_TX_Load_Packet(packet_type member,
2227	infoframe_struct *p)
2228	{
2229	BYTE exe_result = 0x00;
2230	BYTE address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};
2231	BYTE i;
2232	BYTE c;
2233	TT();
2234	p->pb_byte[0] = HDMI_TX_Checksum(p);
2235
2236	// write infoframe to according regs
2237	DHL_SYS_ANXWrite(1, address[member], p->type);
2238	DHL_SYS_ANXWrite(1, address[member]+1, p->version);
2239	DHL_SYS_ANXWrite(1, address[member]+2, p->length);
2240
2241	for(i=0; i <= 27; i++)
2242	{
2243	DHL_SYS_ANXWrite(1, address[member]+3+i, p->pb_byte[i]);
2244	DHL_SYS_ANXRead(1,address[member]+3+i, &c);
2245	}
2246	return exe_result;
2247	}
2248
2249	BYTE HDMI_TX_Config_Packet()
2250	{
2251	BYTE exe_result = 0x00;
2252	BYTE info_packet_sel;
2253	BYTE c;
2254	int type_sel;
2255	//DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, 0x00);
2256	//DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, 0x00);
2257	TT();
2258	info_packet_sel = s_hdmi_tx_packet_config.packets_need_config;
2259	HDMI_TX_DebugPrintf("info_packet_sel = 0x%.2x\n",(WORD) info_packet_sel);
2260	// New packet?
2261	if( info_packet_sel != 0x00)
2262	{
2263	// avi infoframe
2264	if( info_packet_sel & HDMI_TX_avi_sel )
2265	{
2266	c = s_hdmi_tx_packet_config.avi_info.pb_byte[1]; //color space
2267	c &= 0x9f;
2268	c \|= (hdmi_tx_RGBorYCbCr << 5);
2269	//HDMI_TX_DebugPrintf("In config packet state, color space = %bu\n", hdmi_tx_RGBorYCbCr);
2270	s_hdmi_tx_packet_config.avi_info.pb_byte[1] = c \| 0x10;
2271	c = s_hdmi_tx_packet_config.avi_info.pb_byte[4];// vid ID
2272	c = c & 0x80;
2273	s_hdmi_tx_packet_config.avi_info.pb_byte[4] = c \| hdmi_tx_video_timing_id;
2274	c = s_hdmi_tx_packet_config.avi_info.pb_byte[5]; //repeat times
2275	c = c & 0xf0;
2276	c \|= (hdmi_tx_tx_pix_rpt & 0x0f);
2277	s_hdmi_tx_packet_config.avi_info.pb_byte[5] = c;
2278	HDMI_TX_DebugPrintf("config avi infoframe packet.\n");
2279	// Disable repeater
2280	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2281
2282	c &= ~HDMI_TX_INFO_PKTCTRL1_AVI_RPT;
2283	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c);
2284
2285	// Enable?wait:go
2286	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2287	if(c & HDMI_TX_INFO_PKTCTRL1_AVI_EN)
2288	{
2289	return exe_result;
2290	}
2291
2292	// load packet data to regs
2293	HDMI_TX_Load_Infoframe( HDMI_TX_avi_infoframe,
2294	&(s_hdmi_tx_packet_config.avi_info));
2295	// Enable and repeater
2296	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2297	c \|= 0x30;
2298	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c);
2299	// complete avi packet
2300	s_hdmi_tx_packet_config.packets_need_config &= ~HDMI_TX_avi_sel;
2301	}
2302
2303	// audio infoframe
2304	if( info_packet_sel & HDMI_TX_audio_sel )
2305	{
2306	HDMI_TX_DebugPrintf("config audio infoframe packet.\n");
2307
2308	// Disable repeater
2309	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2310	c &= ~HDMI_TX_INFO_PKTCTRL2_AIF_RPT;
2311	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2312
2313	// Enable?wait:go
2314	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2315	if(c & HDMI_TX_INFO_PKTCTRL2_AIF_EN)
2316	{
2317	return exe_result;
2318	}
2319	// config packet
2320
2321	// load packet data to regs
2322	HDMI_TX_Load_Infoframe( HDMI_TX_audio_infoframe,
2323	&(s_hdmi_tx_packet_config.audio_info));
2324	// Enable and repeater
2325	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2326	c \|= 0x03;
2327	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2328
2329	s_hdmi_tx_packet_config.packets_need_config &= ~HDMI_TX_audio_sel;
2330	}
2331
2332	// config other 4 packets
2333
2334
2335	if( info_packet_sel & 0xfc )
2336	{
2337	HDMI_TX_DebugPrintf("other packets.\n");
2338
2339	//find the current type need config
2340	if(info_packet_sel & HDMI_TX_spd_sel) type_sel = HDMI_TX_spd_sel;
2341	else if(info_packet_sel & HDMI_TX_mpeg_sel) type_sel = HDMI_TX_mpeg_sel;
2342	else if(info_packet_sel & HDMI_TX_acp_sel) type_sel = HDMI_TX_acp_sel;
2343	else if(info_packet_sel & HDMI_TX_isrc1_sel) type_sel = HDMI_TX_isrc1_sel;
2344	else if(info_packet_sel & HDMI_TX_isrc2_sel) type_sel = HDMI_TX_isrc2_sel;
2345	else type_sel = HDMI_TX_vendor_sel;
2346
2347
2348	// Disable repeater
2349	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2350	c &= ~HDMI_TX_INFO_PKTCTRL2_AIF_RPT;
2351	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2352
2353	switch(type_sel)
2354	{
2355	case HDMI_TX_spd_sel:
2356	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2357	c &= ~HDMI_TX_INFO_PKTCTRL1_SPD_RPT;
2358	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c);
2359
2360	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2361	if(c & HDMI_TX_INFO_PKTCTRL1_SPD_EN)
2362	{
2363	HDMI_TX_DebugPrintf("wait disable, config spd infoframe packet.\n");
2364	return exe_result;
2365	}
2366	break;
2367
2368	case HDMI_TX_mpeg_sel:
2369	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2370	c &= ~HDMI_TX_INFO_PKTCTRL2_MPEG_RPT;
2371	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2372
2373	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2374	if(c & HDMI_TX_INFO_PKTCTRL2_MPEG_EN)
2375	{
2376	HDMI_TX_DebugPrintf("wait disable, config mpeg infoframe packet.\n");
2377	return exe_result;
2378	}
2379	break;
2380
2381	case HDMI_TX_acp_sel:
2382	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2383	c &= ~HDMI_TX_INFO_PKTCTRL2_UD0_RPT;
2384	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2385
2386	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2387	if(c & HDMI_TX_INFO_PKTCTRL2_UD0_EN)
2388	{
2389	HDMI_TX_DebugPrintf("wait disable, config mpeg infoframe packet.\n");
2390	return exe_result;
2391	}
2392	break;
2393
2394	case HDMI_TX_isrc1_sel:
2395	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2396	c &= ~HDMI_TX_INFO_PKTCTRL2_UD0_RPT;
2397	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2398	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2399	if(c & HDMI_TX_INFO_PKTCTRL2_UD0_EN)
2400	{
2401	HDMI_TX_DebugPrintf("wait disable, config isrc1 packet.\n");
2402	return exe_result;
2403	}
2404	break;
2405
2406	case HDMI_TX_isrc2_sel:
2407	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2408	c &= ~HDMI_TX_INFO_PKTCTRL2_UD1_RPT;
2409	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2410	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2411	if(c & HDMI_TX_INFO_PKTCTRL2_UD1_EN)
2412	{
2413	HDMI_TX_DebugPrintf("wait disable, config isrc2 packet.\n");
2414	return exe_result;
2415	}
2416	break;
2417
2418	case HDMI_TX_vendor_sel:
2419	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2420	c &= ~HDMI_TX_INFO_PKTCTRL2_UD1_RPT;
2421	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2422	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2423	if(c & HDMI_TX_INFO_PKTCTRL2_UD1_EN)
2424	{
2425	HDMI_TX_DebugPrintf("wait disable, config vendor packet.\n");
2426	return exe_result;
2427	}
2428	break;
2429
2430	default : break;
2431	}
2432
2433
2434	// config packet
2435	// TODO: config packet in top level
2436
2437	// load packet data to regs
2438
2439	switch(type_sel)
2440	{
2441	#if 0
2442	case HDMI_TX_spd_sel:
2443	HDMI_TX_Load_Infoframe( HDMI_TX_spd_infoframe,
2444	&(s_hdmi_tx_packet_config.spd_info));
2445	HDMI_TX_DebugPrintf("config spd done.\n");
2446	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL1_REG, &c);
2447	c \|= 0xc0;
2448	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c);
2449	break;
2450
2451	case HDMI_TX_mpeg_sel:
2452	// HDMI_TX_Load_Infoframe( HDMI_TX_mpeg_infoframe,
2453	// &(s_hdmi_tx_packet_config.mpeg_info));
2454	HDMI_TX_DebugPrintf("config mpeg done.\n");
2455	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2456	c \|= 0x0c;
2457	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2458	break;
2459
2460	case HDMI_TX_acp_sel:
2461	// HDMI_TX_Load_Packet( HDMI_TX_acp_packet,
2462	// &(s_hdmi_tx_packet_config.acp_pkt));
2463	HDMI_TX_DebugPrintf("config acp done.\n");
2464	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2465	c \|= 0x30;
2466	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2467	break;
2468
2469	case HDMI_TX_isrc1_sel:
2470	// HDMI_TX_Load_Packet( HDMI_TX_isrc1_packet,
2471	// &(s_hdmi_tx_packet_config.acp_pkt));
2472	HDMI_TX_DebugPrintf("config isrc1 done.\n");
2473	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2474	c \|= 0x30;
2475	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2476	break;
2477
2478	case HDMI_TX_isrc2_sel:
2479	// HDMI_TX_Load_Packet( HDMI_TX_isrc2_packet,
2480	// &(s_hdmi_tx_packet_config.acp_pkt));
2481	HDMI_TX_DebugPrintf("config isrc2 done.\n");
2482	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2483	c \|= 0xc0;
2484	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2485	break;
2486	#endif
2487	case HDMI_TX_vendor_sel:
2488	HDMI_TX_Load_Packet( HDMI_TX_vendor_infoframe,
2489	&(s_hdmi_tx_packet_config.vendor_info));
2490	HDMI_TX_DebugPrintf("config vendor done.\n");
2491	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2492	c \|= 0xc0;
2493	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2494	break;
2495
2496	default : break;
2497	}
2498
2499	// Enable and repeater
2500	DHL_SYS_ANXRead(1,HDMI_TX_INFO_PKTCTRL2_REG, &c);
2501	c \|= 0x03;
2502	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
2503
2504	// complete config packet
2505	HDMI_TX_DebugPrintf("config other packets done.\n");
2506	s_hdmi_tx_packet_config.packets_need_config &= ~type_sel;
2507
2508	}
2509
2510	}
2511	return exe_result;
2512	}
2513
2514
2515	BYTE HDMI_TX_Load_Infoframe(packet_type member,
2516	infoframe_struct *p)
2517	{
2518	BYTE exe_result = 0x00;
2519	BYTE address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};
2520	BYTE i;
2521	BYTE c;
2522	TT();
2523	p->pb_byte[0] = HDMI_TX_Checksum(p);
2524
2525	// write infoframe to according regs
2526	DHL_SYS_ANXWrite(1, address[member], p->type);
2527	DHL_SYS_ANXWrite(1, address[member]+1, p->version);
2528	DHL_SYS_ANXWrite(1, address[member]+2, p->length);
2529
2530	for(i=0; i <= p->length; i++)
2531	{
2532	DHL_SYS_ANXWrite(1, address[member]+3+i, p->pb_byte[i]);
2533	DHL_SYS_ANXRead(1,address[member]+3+i, &c);
2534	}
2535	return exe_result;
2536	}
2537
2538	BYTE HDMI_TX_Checksum(infoframe_struct *p)
2539	{
2540	BYTE checksum = 0x00;
2541	BYTE i;
2542	TT();
2543	checksum = p->type + p->length + p->version;
2544	for(i=1; i <= p->length; i++)
2545	{
2546	checksum += p->pb_byte[i];
2547	}
2548	checksum = ~checksum;
2549	checksum += 0x01;
2550
2551	return checksum;
2552	}
2553
2554
2555	void HDMI_TX_HDCP_Process(void)
2556	{
2557	BYTE c;
2558	BYTE Bksv_valid=0;
2559	// BYTE ksvlist_ready_count=0;
2560	// BYTE ksvlist_ready=0, ksvlist_valid=0;
2561	//BIT ready;
2562	//BYTE aksv1[5],i;
2563	// HDMI_RX_ReadI2C_RX1(0x08,&c);
2564	//if(!c)
2565	//{return;}
2566	//if(!hdmi_rx_auth_done)
2567	//{return;}
2568	//if(!g_Auth_Start)
2569	//return;
2570
2571	if(hdmi_tx_HDCP_enable) //update once in main.c
2572	{
2573	//if(!hdmi_tx_hdcp_auth_done)
2574	//{
2575
2576	//HDMI_TX_Set_AVMute();//before auth, set_avmute, should not mute video at this time. jh hdcp/simplay
2577	OS_mDelay(10);//let unencrypted video play a while, required by HDCP CTS. SY
2578	HDMI_TX_Set_AVMute(); //must disable any video before hdcp authentication starts. SY.
2579	OS_mDelay(10);
2580	if( !hdmi_tx_hdcp_init_done )
2581	{
2582	DHL_SYS_ANXRead(0,HDMI_TX_SYS_CTRL1_REG, &c); //72:07.2 hdcp on
2583	DHL_SYS_ANXWrite(0,HDMI_TX_SYS_CTRL1_REG, (c \| HDMI_TX_SYS_CTRL1_HDCPMODE));
2584	if(hdmi_tx_edid_result.is_HDMI)
2585	HDMI_TX_Hardware_HDCP_Auth_Init();
2586	else
2587	{ //DVI, disable 1.1 feature and enable HDCP two special point check
2588	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL1_REG, &c);
2589	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL1_REG,
2590	( (c & (~HDMI_TX_HDCP_CTRL1_HDCP11_EN)) \| HDMI_TX_LINK_CHK_12_EN));
2591	}
2592
2593	if(!HDMI_TX_BKSV_SRM())
2594	{
2595	HDMI_TX_Blue_Screen_Enable();
2596	HDMI_TX_Clear_AVMute();
2597	Bksv_valid=0;
2598	return;
2599	}
2600	else //SY.
2601	{
2602	Bksv_valid=1;
2603	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1
2604	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c \| 0x03));//
2605	}
2606
2607	hdmi_tx_hdcp_init_done = 1;
2608
2609	}
2610
2611	if((Bksv_valid) && (!hdmi_tx_hdcp_auth_en))
2612	{
2613	HDMI_TX_DebugPrintf("HW hdcp enabled.");
2614	HDMI_TX_RST_DDCChannel();
2615	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1.3
2616	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c \| HDMI_TX_HDCP_CTRL0_HW_AUTHEN));
2617	hdmi_tx_hdcp_auth_en = 1;
2618	//hdmi_tx_hdcp_auth_fail_cnt=0;
2619	}
2620
2621	if((Bksv_valid) && (hdmi_tx_hdcp_wait_100ms_needed))
2622	{
2623	hdmi_tx_hdcp_wait_100ms_needed = 0;
2624	//disable audio
2625	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2626	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
2627	HDMI_TX_DebugPrintf("++++++++ Anx8560_hdcp_wait_100ms_needed ++++++++\n");
2628	OS_mDelay(100);
2629	return;
2630	}
2631
2632	if(hdmi_tx_hdcp_auth_pass)//can only be set in ISR: HDMI_TX_Auth_Done_Interrupt(), or HDMI_TX_Auth_Change_Interrupt()
2633	{
2634
2635	//Enable HDCP Hardware encryption
2636	if(!hdmi_tx_hdcp_encryption)
2637	{
2638	HDMI_TX_HDCP_Encryption_Enable(); //72:a1.2=1
2639	}
2640	if(hdmi_tx_send_blue_screen)
2641	{
2642	HDMI_TX_Blue_Screen_Disable();
2643	}
2644	if(hdmi_tx_avmute_enable)
2645	{
2646	HDMI_TX_Clear_AVMute();
2647	}
2648	//enable audio SY.
2649	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2650	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
2651	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c);
2652	HDMI_TX_DebugPrintf("@@@ 1st part HDCP Auth PASSED! @@@\n");
2653
2654	if (hdmi_tx_hdcp_bcaps & 0x40) //repeater
2655	{ //when 72:a1.2=1, the hw will take over the bcaps chk, reading KSV list
2656	HDMI_TX_DebugPrintf("Rpt attached!");
2657	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1
2658	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c \| 0x40));//set repeater
2659	//actually it is KSVList check. we can't do SRM check due to the lack of SRM file. SY.
2660	if(!hdmi_tx_srm_checked)
2661	{
2662	while((hdmi_tx_hdcp_bcaps&0x20)!=0x20)
2663	{
2664	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x40, 0x01, 0x00);
2665	OS_mDelay(2);
2666	DHL_SYS_ANXRead(0,HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_tx_hdcp_bcaps);
2667	}
2668
2669	if (!HDMI_TX_IS_KSVList_VLD())//chk bstatus error bits
2670	{
2671	HDMI_TX_DebugPrintf("ksvlist not good. disable encryption");
2672	HDMI_RPT_Set_BCAPS_Ready(0);
2673	HDMI_TX_HDCP_Encryption_Disable();
2674	HDMI_TX_Blue_Screen_Enable();
2675	HDMI_TX_Clear_AVMute();
2676	hdmi_tx_ksv_srm_pass = 0;
2677	HDMI_TX_Clean_HDCP();//SY.
2678	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1
2679	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c & 0xfe));//set ksvlist check valid
2680	//remove below will pass 1b-05/1b-06
2681	//HDMI_TX_Set_System_State(HDMI_TX_WAIT_HOTPLUG);//SY.
2682	return;
2683	}
2684	hdmi_tx_srm_checked=1;
2685	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1.3
2686	HDMI_TX_DebugPrintf("U72:A1 = 0x%.2x\n", (WORD)c); //typical will be 0x44
2687	}
2688	}
2689	else
2690	{
2691	HDMI_TX_DebugPrintf("Receiver attached.");
2692
2693	}
2694	hdmi_tx_ksv_srm_pass=1;
2695	//Clear the SRM_Check_Pass BIT, then when reauthentication occurs, firmware can catch it.
2696	DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1
2697	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c & 0xfc));//into 2nd part of auth
2698
2699	}
2700	else
2701	{
2702	HDMI_TX_DebugPrintf("##### HDCP Auth FAILED! #####\n");
2703	//also need to disable HW AUTHEN
2704	// DHL_SYS_ANXRead(0,HDMI_TX_HDCP_CTRL0_REG, &c); //72:a1.3
2705	// DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_CTRL0_REG, (c &(~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
2706	hdmi_tx_hdcp_auth_fail_cnt++;
2707	if( hdmi_tx_hdcp_auth_fail_cnt > 30 ) {
2708	printf("ERROR: HDCP AUTH FAIL CNT > 30, FORCE SET TO HDMI_TX_READ_PARSE_EDID\n");
2709	HDMI_TX_Set_System_State(HDMI_TX_READ_PARSE_EDID);
2710
2711	}
2712
2713	hdmi_tx_hdcp_auth_en = 0;
2714	hdmi_tx_hdcp_wait_100ms_needed=1;
2715	hdmi_tx_hdcp_init_done=0;
2716	if(hdmi_tx_hdcp_encryption)
2717	{
2718	HDMI_TX_HDCP_Encryption_Disable();
2719	}
2720	if(!hdmi_tx_send_blue_screen)
2721	{
2722	HDMI_TX_Blue_Screen_Enable();
2723	}
2724	if(hdmi_tx_avmute_enable)
2725	{
2726	HDMI_TX_Clear_AVMute();
2727	}
2728	//disable audio
2729	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2730	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
2731	//HDMI_TX_Clean_HDCP();//SY. calling this may cause 1B-03 fail. not wait 5s for ksvlist ready
2732	//HDMI_TX_Set_System_State(HDMI_TX_WAIT_HOTPLUG);//SY. don't call this in here
2733	return;
2734	}
2735	hdmi_tx_hdcp_auth_done = 1;
2736	//}
2737
2738	//HDMI_RPT_SHA_Caculate();
2739
2740	}
2741	else //hdmi_tx_HDCP_enable == 0
2742	{
2743	HDMI_TX_DebugPrintf("HDCP is forced off.");
2744	if(hdmi_tx_send_blue_screen)
2745	{
2746	HDMI_TX_Blue_Screen_Disable();
2747	}
2748	if(hdmi_tx_avmute_enable)
2749	{
2750	HDMI_TX_Clear_AVMute();
2751	}
2752	//enable audio SY.
2753	DHL_SYS_ANXRead(0,HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2754	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
2755	DHL_SYS_ANXWrite(0,HDMI_TX_HDMI_AUDCTRL1_REG, c);
2756	}
2757
2758	DHL_SYS_ANXRead(0,HDMI_TX_SYS_CTRL1_REG, &c); //72:07.1 hdmi or dvi mode
2759	c = c & 0x02;
2760	if(c == 0x02)
2761	{
2762	HDMI_TX_DebugPrintf("end of HDMI_TX_HDCP_Process(): in HDMI mode.");
2763	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_AUDIO);
2764	}
2765	else
2766	{
2767	HDMI_TX_DebugPrintf("end of HDMI_TX_HDCP_Process(): in DVI mode.");
2768	//To-Do: Config to DVI mode.
2769	HDMI_TX_Set_System_State(HDMI_TX_PLAY_BACK);
2770	HDMI_TX_Show_Video_Parameter();
2771	}
2772	}
2773	#if 0
2774	{
2775	BYTE c;
2776	// BYTE aksv1[5],i;
2777
2778	TT();
2779	if(hdmi_tx_HDCP_enable)
2780	{
2781
2782	//HDMI_TX_Set_AVMute();//before auth, set_avmute
2783
2784	if( !hdmi_tx_hdcp_init_done )
2785	{
2786	if(hdmi_tx_edid_result.is_HDMI)
2787	HDMI_TX_Hardware_HDCP_Auth_Init();
2788	else
2789	{ //DVI, disable 1.1 feature and enable HDCP two special point check
2790	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL1_REG, &c);
2791	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL1_REG,
2792	((c & (~HDMI_TX_HDCP_CTRL1_HDCP11_EN)) \| HDMI_TX_LINK_CHK_12_EN));
2793	}
2794	hdmi_tx_hdcp_init_done = 1;
2795	/* if(hdmi_tx_hdcp_bcaps & 0x40)
2796	{
2797	//Write AKSV to Repeater to get repeater KSVFIFO ready
2798	for (i = 0; i < 5; i++)
2799	{
2800	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_AKSV1_REG + i, &aksv1[i]);
2801	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_FIFO_ACC_REG, aksv1[i]);
2802	}
2803	HDMI_TX_InitDDC_Write(0x74, 0x00 ,0x10,5,0);
2804	}*/
2805	}
2806
2807	// set SRM and KSVList valid.
2808	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
2809	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c \| 0x03));
2810
2811
2812	if(!hdmi_tx_hdcp_auth_en)
2813	// enable hardware HDCP
2814	{
2815	HDMI_TX_RST_DDCChannel();
2816	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
2817	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c \| HDMI_TX_HDCP_CTRL0_HW_AUTHEN));
2818	hdmi_tx_hdcp_auth_en = 1;
2819	}
2820
2821	if(hdmi_tx_hdcp_wait_100ms_needed)
2822	{
2823	hdmi_tx_hdcp_wait_100ms_needed = 0;
2824	//disable audio
2825	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2826	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
2827	HDMI_TX_DebugPrintf("++++++++hdmi_tx_hdcp_wait_100ms_needed----------+++++++++\n");
2828	OS_mDelay(100);
2829	return;
2830	}
2831
2832	if(hdmi_tx_hdcp_auth_pass)
2833	{
2834	//Clear the SRM_Check_Pass BIT, then when reauthentication occurs, firmware can catch it.
2835	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
2836	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, c & 0xfc);
2837	//Enable HDCP Hardware encryption
2838	if(!hdmi_tx_hdcp_encryption)
2839	{
2840	HDMI_TX_HDCP_Encryption_Enable();
2841	}
2842	if(hdmi_tx_send_blue_screen)
2843	{
2844	HDMI_TX_Blue_Screen_Disable();
2845	}
2846	HDMI_TX_DebugPrintf("@@@@@@@@@@@@@@@@@@@@@@@hdmi_tx_hdcp_auth_pass@@@@@@@@@@@@@@@@@@@@\n");
2847	}
2848	else
2849	{
2850	if(!hdmi_tx_send_blue_screen)
2851	{
2852	HDMI_TX_DebugPrintf("++++++++++++send blue screen+++++++++++\n");
2853	HDMI_TX_Blue_Screen_Enable();
2854	}
2855	if(hdmi_tx_hdcp_encryption)
2856	{
2857	HDMI_TX_HDCP_Encryption_Disable();
2858	}
2859	if(hdmi_tx_avmute_enable)
2860	{
2861	HDMI_TX_DebugPrintf("----------------------------clear avmute----------------\n");
2862	HDMI_TX_Clear_AVMute();
2863	}
2864	//disable audio
2865	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
2866	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c & (~HDMI_TX_HDMI_AUDCTRL1_IN_EN));
2867	return;
2868	}
2869
2870	//for repeater
2871	//HDMI_RPT_Get_KSV();
2872	if(!hdmi_tx_srm_checked)
2873	{
2874	if(!HDMI_TX_Check_KSV_SRM())
2875	{
2876	hdmi_tx_ksv_srm_pass = 0;
2877	}
2878	else
2879	{
2880	hdmi_tx_ksv_srm_pass = 1;
2881	}
2882	//set srm check already done
2883	hdmi_tx_srm_checked = 1;
2884
2885	#if USE_HDMI_RX
2886	if (DD_SYS_IsANX8775Exist())
2887	{
2888	if((hdmi_tx_HDCP_enable == 1) && (hdmi_rx_chip_id = ANX8775))
2889	{
2890	HDMI_TX_MuteTMDS_CLK();
2891	HDMI_RPT_Set_BCAPS_Repeater(1);
2892	HDMI_RX_Set_HPD(0, 500);
2893	return;
2894	}
2895	}
2896	#endif
2897	}
2898
2899	if(!hdmi_tx_ksv_srm_pass)
2900	{
2901	HDMI_TX_DebugPrintf("KSV SRM fail.\n");
2902	if(!hdmi_tx_send_blue_screen)
2903	{
2904	HDMI_TX_DebugPrintf("++++++++++++send blue screen+++++++++++\n");
2905	HDMI_TX_Blue_Screen_Enable();
2906	}
2907	if(hdmi_tx_hdcp_encryption)
2908	{
2909	HDMI_TX_HDCP_Encryption_Disable();
2910	}
2911	if(hdmi_tx_avmute_enable)
2912	{
2913	HDMI_TX_DebugPrintf("----------------------------clear avmute----------------\n");
2914	HDMI_TX_Clear_AVMute();
2915	}
2916	return;
2917	}
2918	}
2919
2920	HDMI_TX_Clear_AVMute();
2921	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
2922	c = c & 0x02;
2923	if(c == 0x02)
2924	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_AUDIO);
2925	else
2926	{
2927	HDMI_TX_Set_System_State(HDMI_TX_PLAY_BACK);
2928	HDMI_TX_Clear_AVMute();
2929	HDMI_TX_Show_Video_Parameter();
2930	}
2931
2932	}
2933	#endif
2934
2935	void HDMI_TX_PLAYBACK_Process(void)
2936	{
2937	if((s_hdmi_tx_packet_config.packets_need_config != 0x00) && (hdmi_tx_edid_result.is_HDMI == 1))
2938	HDMI_TX_Config_Packet();
2939	}
2940
2941	void HDMI_TX_RST_DDCChannel(void)
2942	{
2943	BYTE c;
2944	//Reset the DDC channel
2945	TT();
2946	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL2_REG, &c);
2947	DHL_SYS_ANXWrite(0,HDMI_TX_SYS_CTRL2_REG, (c \| HDMI_TX_SYS_CTRL2_DDC_RST));
2948	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, (c & (~HDMI_TX_SYS_CTRL2_DDC_RST)));
2949	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x00); //abort current operation
2950	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x06);//reset I2C command
2951	//Clear FIFO
2952	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x05);
2953	}
2954
2955	BYTE HDMI_TX_Check_KSV_SRM(void)
2956	{
2957	TT();
2958	if(!HDMI_TX_BKSV_SRM()) //Check BKSV SRM, fail
2959	{
2960	HDMI_TX_DebugPrintf("BKSV SRM fail.\n");
2961	return 0;
2962	}
2963	else // BKSV SRM pass
2964	{
2965	HDMI_TX_DebugPrintf("BKSV SRM pass.\n");
2966	if(hdmi_tx_hdcp_bcaps & 0x40)//repeater
2967	{
2968	if(!HDMI_TX_IS_KSVList_VLD())//KSVList not valid
2969	{
2970	HDMI_TX_DebugPrintf("Repeater: KSVList not valid.\n");
2971	return 0;
2972	}
2973	else//KSVList valid
2974	{
2975	HDMI_TX_DebugPrintf("Repeater: KSVList valid.\n");
2976	return 1;
2977	}
2978	}
2979	else//not repeater
2980	{
2981	return 1;
2982	}
2983	}
2984	}
2985
2986	/*void HDMI_TX_IS_KSVFIFO_Ready(void)
2987	{
2988	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x40, 0x01, 0x00);
2989	OS_mDelay(5);
2990	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_tx_hdcp_bcaps);
2991	HDMI_TX_DebugPrintf("hdmi_tx_hdcp_bcaps = 0x%.2x\n", (WORD)hdmi_tx_hdcp_bcaps);
2992	}
2993	*/
2994	BYTE HDMI_TX_BKSV_SRM(void)
2995	{
2996	BYTE bksv[5],i,bksv_one,c1;
2997	TT();
2998	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x00, 0x05, 0x00);
2999	OS_mDelay(15);
3000	for(i = 0; i < 5; i ++)
3001	{
3002	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &bksv[i]);
3003	HDMI_TX_DebugPrintf("BKSV[%.2x] = 0x%.2x\n",(WORD)i,(WORD)bksv[i]);
3004	}
3005
3006	bksv_one = 0;
3007	for(i = 0; i < 8; i++)
3008	{
3009	c1 = 0x01 << i;
3010	if(bksv[0] & c1)
3011	bksv_one ++;
3012	if(bksv[1] & c1)
3013	bksv_one ++;
3014	if(bksv[2] & c1)
3015	bksv_one ++;
3016	if(bksv[3] & c1)
3017	bksv_one ++;
3018	if(bksv[4] & c1)
3019	bksv_one ++;
3020	}
3021	if(bksv_one != 20)
3022	{ // insert anx code for repeater
3023	HDMI_TX_DebugPrintf("BKSV check fail");
3024	hdmi_tx_ksv_srm_pass=0;
3025	HDMI_RPT_Set_BCAPS_Ready(0);
3026	return 0;
3027	}
3028
3029	#if USE_HDMI_RX
3030	if(DD_SYS_IsANX8775Exist())
3031	{
3032	//for repeater
3033	HDMI_RPT_Set_BSTATUS1(0x01);
3034	HDMI_RPT_Set_BSTATUS2(0x01);
3035
3036	HDMI_RPT_Set_KSVList_Init(0x00, 0x05);
3037	for(i = 0; i < 5; i ++)
3038	{
3039	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_REPEATER_KSV_FIFO_REG, bksv[i]);
3040	}
3041	}
3042	#endif
3043
3044	return 1;
3045	}
3046	BYTE HDMI_TX_IS_KSVList_VLD(void)
3047	{
3048	BYTE ksvlist,i,c;
3049	WORD Ksv_length;
3050	HDMI_TX_DebugPrintf("KSV verification in progress..");
3051	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x41, 0x02, 0x00); //Bstatus, two bytes
3052	OS_mDelay(5);
3053	DHL_SYS_ANXRead(0,HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_tx_hdcp_bstatus[0]);
3054	DHL_SYS_ANXRead(0,HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_tx_hdcp_bstatus[1]);
3055	if((hdmi_tx_hdcp_bstatus[0] & 0x80) \| (hdmi_tx_hdcp_bstatus[1] & 0x08))
3056	{
3057	HDMI_TX_DebugPrintf("Max dev/cascade exceeded: hdmi_tx_hdcp_bstatus[0]: 0x%x,hdmi_tx_hdcp_bstatus[1]:0x%x\n", (WORD)hdmi_tx_hdcp_bstatus[0],(WORD)hdmi_tx_hdcp_bstatus[1]);
3058	return 0;//HDCP topology error. More than 127 RX are attached or more than seven levels of repeater are cascaded.
3059	}
3060
3061	HDMI_TX_DebugPrintf("hdmi_tx_hdcp_bstatus[0] = 0x%.2x\n",(WORD)hdmi_tx_hdcp_bstatus[0]);
3062	HDMI_TX_DebugPrintf("hdmi_tx_hdcp_bstatus[1] = 0x%.2x\n",(WORD)hdmi_tx_hdcp_bstatus[1]);
3063
3064	#if USE_HDMI_RX
3065	if( DD_SYS_IsANX8775Exist())
3066	{
3067	//for repeater
3068	HDMI_RPT_Set_BSTATUS1(hdmi_tx_hdcp_bstatus[0] + 1);
3069	HDMI_RPT_Set_BSTATUS2(hdmi_tx_hdcp_bstatus[1] + 1);
3070
3071
3072	if((hdmi_tx_hdcp_bstatus[0] & 0x7f)>15)
3073	{
3074	HDMI_RX_ReadI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW1_REG, &c);
3075	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW1_REG, (c\|0x80));
3076	}
3077	if((hdmi_tx_hdcp_bstatus[1] & 0x07)>6)
3078	{
3079	HDMI_RX_ReadI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW2_REG, &c);
3080	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW2_REG, (c\|0x08));
3081	}
3082
3083	Ksv_length = 5 * (hdmi_tx_hdcp_bstatus[0] & 0x7f);
3084
3085	HDMI_TX_DebugPrintf("Ksv_length = %u\n",Ksv_length);
3086
3087	HDMI_TX_DebugPrintf("Read KSVList begins.........\n");
3088	HDMI_TX_InitDDC_Read(0x74,0x00, 0x43, (BYTE)(Ksv_length & 0xff), (BYTE)((Ksv_length >> 8) & 0xff));
3089	// HDMI_TX_DDC_Mass_Read(Ksv_length);
3090
3091	#if (HDMI_TX_USE_NATIVE_CODE)
3092	HDMI_RPT_Set_KSVList_Init(0x05, Ksv_length);
3093	#endif
3094
3095	HDMI_TX_InitDDC_Read(0x74,0x00, 0x43, (BYTE)(Ksv_length & 0xff), (BYTE)((Ksv_length >> 8) & 0xff));
3096	OS_mDelay(3 * Ksv_length);
3097	for(i = 0; i < Ksv_length; i ++)//HDCP device_count = hdmi_tx_hdcp_bstatus[0] & 0x7f
3098	{
3099	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &ksvlist);//read one byte from ddc_fifo
3100	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_REPEATER_KSV_FIFO_REG, ksvlist);
3101	HDMI_TX_DebugPrintf("KSVList[%.2x] = 0x%.2x\n",(WORD)i,(WORD)ksvlist);
3102	}
3103	}
3104	#else
3105	Ksv_length = 0;
3106	c = 0;
3107	i = 0;
3108	ksvlist = 0;
3109	#endif
3110
3111	return 1;
3112	}
3113
3114
3115	void HDMI_TX_Hardware_HDCP_Auth_Init(void)
3116	{
3117	BYTE c;
3118	TT();
3119	// disable hdcp
3120	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
3121	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
3122
3123	// DDC reset
3124	HDMI_TX_RST_DDCChannel();
3125
3126	HDMI_TX_InitDDC_Read(0x74, 0x00, 0x40, 0x01, 0x00);
3127	OS_mDelay(5);
3128	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &hdmi_tx_hdcp_bcaps);
3129	HDMI_TX_DebugPrintf("hdmi_tx_hdcp_bcaps = 0x%.2x\n",
3130	(WORD)hdmi_tx_hdcp_bcaps);
3131
3132	if(hdmi_tx_hdcp_bcaps & 0x02)
3133	{ //enable 1.1 feature
3134	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL1_REG, &c);
3135	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL1_REG, (c \|HDMI_TX_HDCP_CTRL1_HDCP11_EN));
3136	}
3137	else
3138	{ //disable 1.1 feature and enable HDCP two special point check
3139	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL1_REG, &c);
3140	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL1_REG,
3141	((c & (~HDMI_TX_HDCP_CTRL1_HDCP11_EN)) \| HDMI_TX_LINK_CHK_12_EN));
3142	}
3143	HDMI_TX_RST_DDCChannel();
3144	hdmi_tx_hdcp_auth_en = 0;
3145	}
3146
3147
3148	void HDMI_TX_Clean_HDCP(void)
3149	{
3150	BYTE c;
3151	TT();
3152	//mute TMDS link
3153	HDMI_TX_MuteTMDS_CLK();
3154	//Disable hardware HDCP
3155	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
3156	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c & (~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
3157
3158	//Reset HDCP logic
3159	DHL_SYS_ANXRead(0, HDMI_TX_SRST_REG, &c);
3160	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, (c \| HDMI_TX_SRST_HDCP_RST) );
3161	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, (c & (~HDMI_TX_SRST_HDCP_RST)) );
3162
3163	//Set ReAuth
3164	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
3165	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, c \|HDMI_TX_HDCP_CTRL0_RE_AUTH);
3166	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, c & (~HDMI_TX_HDCP_CTRL0_RE_AUTH));
3167	hdmi_tx_hdcp_auth_en = 0;
3168	//hdmi_tx_bksv_ready = 0;
3169	hdmi_tx_hdcp_auth_pass = 0;
3170	hdmi_tx_hdcp_auth_done=0;
3171	hdmi_tx_hdcp_auth_fail_counter =0 ;
3172	hdmi_tx_hdcp_encryption = 0;
3173	hdmi_tx_send_blue_screen = 0;
3174	hdmi_tx_hdcp_init_done = 0;
3175	hdmi_tx_hdcp_wait_100ms_needed = 1;
3176	HDMI_TX_RST_DDCChannel();
3177	}
3178
3179	void HDMI_TX_Hardware_Reset()
3180	{
3181	DHL_SYS_SetGPIO(GPIO_HDMI_TX_RESET, 0);
3182	OS_mDelay(1);
3183	DHL_SYS_SetGPIO(GPIO_HDMI_TX_RESET, 1);
3184	OS_mDelay(1);
3185	}
3186
3187	BYTE HDMI_TX_Get_System_State(void)
3188	{
3189	return HDMI_TX_system_state;
3190	}
3191
3192	void HDMI_TX_Set_System_State(BYTE ss)
3193	{
3194	BYTE c;
3195	TT();
3196	HDMI_TX_system_state = ss;
3197	HDMI_TX_DebugPrintf("HDMI_TX To System State: \n");
3198	switch (ss)
3199	{
3200	case HDMI_TX_INITIAL:
3201	//
3202	// TX°¡ ¾ø´Â °æ¿ì, HDMI-RXÂÊ HPD¸¦ Ç×»ó ³»¸®ÀÚ.
3203	//
3204	DHL_CAP_SetHPDEnable(0);
3205	HDMI_TX_DebugPrintf("HDMI_TX_INITIAL\n");
3206	break;
3207	case HDMI_TX_WAIT_HOTPLUG:
3208	//
3209	// TX°¡ ¾ø´Â °æ¿ì, HDMI-RXÂÊ HPD¸¦ Ç×»ó ³»¸®ÀÚ.
3210	//
3211	DHL_CAP_SetHPDEnable(0);
3212	HDMI_TX_DebugPrintf("HDMI_TX_WAIT_HOTPLUG\n");
3213	break;
3214	case HDMI_TX_READ_PARSE_EDID:
3215	HDMI_TX_DebugPrintf("HDMI_TX_READ_PARSE_EDID\n");
3216	break;
3217	/* case HDMI_TX_WAIT_RX_SENSE:
3218	HDMI_TX_DebugPrintf("HDMI_TX_WAIT_RX_SENSE\n");
3219	break;*/
3220	case HDMI_TX_CONFIG_VIDEO:
3221	HDMI_TX_DebugPrintf("HDMI_TX_CONFIG_VIDEO\n");
3222	break;
3223	case HDMI_TX_CONFIG_AUDIO:
3224	HDMI_TX_DebugPrintf("HDMI_TX_CONFIG_AUDIO\n");
3225	break;
3226	case HDMI_TX_CONFIG_PACKETS:
3227	HDMI_TX_DebugPrintf("HDMI_TX_CONFIG_PACKETS\n");
3228	break;
3229	case HDMI_TX_HDCP_AUTHENTICATION:
3230	HDMI_TX_DebugPrintf("HDMI_TX_HDCP_AUTHENTICATION\n");
3231	break;
3232	////////////////////////////////////////////////
3233	// System HDMI_TX_RESET_LINK is kept for RX clock recovery error case, not used in normal case.
3234	case HDMI_TX_RESET_LINK:
3235	HDMI_TX_DebugPrintf("HDMI_TX_RESET_LINK\n");
3236	break;
3237	////////////////////////////////////////////////
3238	case HDMI_TX_PLAY_BACK:
3239	//
3240	// Disable FSM after Video Config.
3241	//
3242	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
3243	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, (c \| HDMI_TX_VID_MODE_LINKVID_EN));
3244
3245	//
3246	// TX°¡ ¾ø´Â °æ¿ì, HDMI-RXÂÊ HPD¸¦ Ç×»ó ³»¸®ÀÚ.
3247	// => PLAYBACK »óÅÂ°¡ µÇ¾î¾ß¸¸ ¿Ã¸².
3248	//
3249	DHL_CAP_SetHPDEnable(1);
3250	HDMI_TX_DebugPrintf("HDMI_TX_PLAY_BACK\n");
3251	break;
3252	}
3253	}
3254
3255	void HDMI_TX_Set_TMDS_Amp_Internal(void)
3256	{
3257	unsigned char reg_val, c;
3258	HDMI_TX_TMDS_AMP d0_val, d1_val, d2_val, clk_val;
3259
3260	if (HDMI_TX_Get_TMDS_Clk() > 165000000)
3261	{
3262	d0_val = &tmds_d0_amp_hs;
3263	d1_val = &tmds_d1_amp_hs;
3264	d2_val = &tmds_d2_amp_hs;
3265	clk_val = &tmds_clk_amp_hs;
3266	}
3267	else
3268	{
3269	d0_val = &tmds_d0_amp_ls;
3270	d1_val = &tmds_d1_amp_ls;
3271	d2_val = &tmds_d2_amp_ls;
3272	clk_val = &tmds_clk_amp_ls;
3273	}
3274
3275	printf("\|%s\| Set TMDS D0 amplitude : ", __FUNCTION__);
3276	switch (*d0_val)
3277	{
3278	case HDMI_TX_TMDS_AMP_380:
3279	reg_val = 0x00;
3280	printf("380");
3281	break;
3282	case HDMI_TX_TMDS_AMP_420:
3283	reg_val = 0x04;
3284	printf("420");
3285	break;
3286	case HDMI_TX_TMDS_AMP_460:
3287	reg_val = 0x08;
3288	printf("460");
3289	break;
3290	case HDMI_TX_TMDS_AMP_500:
3291	reg_val = 0x0c;
3292	printf("500");
3293	break;
3294	case HDMI_TX_TMDS_AMP_540:
3295	reg_val = 0x10;
3296	printf("540");
3297	break;
3298	case HDMI_TX_TMDS_AMP_580:
3299	reg_val = 0x14;
3300	printf("580");
3301	break;
3302	case HDMI_TX_TMDS_AMP_620:
3303	reg_val = 0x18;
3304	printf("620");
3305	break;
3306	default:
3307	case HDMI_TX_TMDS_AMP_660:
3308	reg_val = 0x1c;
3309	printf("660");
3310	break;
3311	}
3312	printf("mV\n");
3313
3314	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH0_CONFIG_REG, &c);
3315	if ((c & 0x1c) != reg_val)
3316	{
3317	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH0_CONFIG_REG, ((c & ~0x1c) \| reg_val));
3318	}
3319
3320	printf("\|%s\| Set TMDS D1 amplitude : ", __FUNCTION__);
3321	switch (*d1_val)
3322	{
3323	case HDMI_TX_TMDS_AMP_380:
3324	reg_val = 0x00;
3325	printf("380");
3326	break;
3327	case HDMI_TX_TMDS_AMP_420:
3328	reg_val = 0x04;
3329	printf("420");
3330	break;
3331	case HDMI_TX_TMDS_AMP_460:
3332	reg_val = 0x08;
3333	printf("460");
3334	break;
3335	case HDMI_TX_TMDS_AMP_500:
3336	reg_val = 0x0c;
3337	printf("500");
3338	break;
3339	case HDMI_TX_TMDS_AMP_540:
3340	reg_val = 0x10;
3341	printf("540");
3342	break;
3343	case HDMI_TX_TMDS_AMP_580:
3344	reg_val = 0x14;
3345	printf("580");
3346	break;
3347	case HDMI_TX_TMDS_AMP_620:
3348	reg_val = 0x18;
3349	printf("620");
3350	break;
3351	default:
3352	case HDMI_TX_TMDS_AMP_660:
3353	reg_val = 0x1c;
3354	printf("660");
3355	break;
3356	}
3357	printf("mV\n");
3358
3359	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH1_CONFIG_REG, &c);
3360	if ((c & 0x1c) != reg_val)
3361	{
3362	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH1_CONFIG_REG, ((c & ~0x1c) \| reg_val));
3363	}
3364
3365	printf("\|%s\| Set TMDS D2 amplitude : ", __FUNCTION__);
3366	switch (*d2_val)
3367	{
3368	case HDMI_TX_TMDS_AMP_380:
3369	reg_val = 0x00;
3370	printf("380");
3371	break;
3372	case HDMI_TX_TMDS_AMP_420:
3373	reg_val = 0x04;
3374	printf("420");
3375	break;
3376	case HDMI_TX_TMDS_AMP_460:
3377	reg_val = 0x08;
3378	printf("460");
3379	break;
3380	case HDMI_TX_TMDS_AMP_500:
3381	reg_val = 0x0c;
3382	printf("500");
3383	break;
3384	case HDMI_TX_TMDS_AMP_540:
3385	reg_val = 0x10;
3386	printf("540");
3387	break;
3388	case HDMI_TX_TMDS_AMP_580:
3389	reg_val = 0x14;
3390	printf("580");
3391	break;
3392	case HDMI_TX_TMDS_AMP_620:
3393	reg_val = 0x18;
3394	printf("620");
3395	break;
3396	default:
3397	case HDMI_TX_TMDS_AMP_660:
3398	reg_val = 0x1c;
3399	printf("660");
3400	break;
3401	}
3402	printf("mV\n");
3403
3404	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH2_CONFIG_REG, &c);
3405	if ((c & 0x1c) != reg_val)
3406	{
3407	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH2_CONFIG_REG, ((c & ~0x1c) \| reg_val));
3408	}
3409
3410	printf("\|%s\| Set TMDS Clk amplitude : ", __FUNCTION__);
3411	switch (*clk_val)
3412	{
3413	case HDMI_TX_TMDS_AMP_380:
3414	reg_val = 0x00;
3415	printf("380");
3416	break;
3417	case HDMI_TX_TMDS_AMP_420:
3418	reg_val = 0x04;
3419	printf("420");
3420	break;
3421	case HDMI_TX_TMDS_AMP_460:
3422	reg_val = 0x08;
3423	printf("460");
3424	break;
3425	case HDMI_TX_TMDS_AMP_500:
3426	reg_val = 0x0c;
3427	printf("500");
3428	break;
3429	case HDMI_TX_TMDS_AMP_540:
3430	reg_val = 0x10;
3431	printf("540");
3432	break;
3433	case HDMI_TX_TMDS_AMP_580:
3434	reg_val = 0x14;
3435	printf("580");
3436	break;
3437	case HDMI_TX_TMDS_AMP_620:
3438	reg_val = 0x18;
3439	printf("620");
3440	break;
3441	default:
3442	case HDMI_TX_TMDS_AMP_660:
3443	reg_val = 0x1c;
3444	printf("660");
3445	break;
3446	}
3447	printf("mV\n");
3448
3449	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, &c);
3450	if ((c & 0x1c) != reg_val)
3451	{
3452	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, ((c & ~0x1c) \| reg_val));
3453	}
3454	}
3455
3456	void HDMI_TX_Set_TMDS_Amp_LS(HDMI_TX_TMDS_AMP d0_val, HDMI_TX_TMDS_AMP d1_val, HDMI_TX_TMDS_AMP d2_val, HDMI_TX_TMDS_AMP clk_val)
3457	{
3458	tmds_d0_amp_ls = d0_val;
3459	tmds_d1_amp_ls = d1_val;
3460	tmds_d2_amp_ls = d2_val;
3461	tmds_clk_amp_ls = clk_val;
3462
3463	HDMI_TX_Set_TMDS_Amp_Internal();
3464	}
3465
3466	void HDMI_TX_Set_TMDS_Amp_HS(HDMI_TX_TMDS_AMP d0_val, HDMI_TX_TMDS_AMP d1_val, HDMI_TX_TMDS_AMP d2_val, HDMI_TX_TMDS_AMP clk_val)
3467	{
3468	tmds_d0_amp_hs = d0_val;
3469	tmds_d1_amp_hs = d1_val;
3470	tmds_d2_amp_hs = d2_val;
3471	tmds_clk_amp_hs = clk_val;
3472
3473	HDMI_TX_Set_TMDS_Amp_Internal();
3474	}
3475
3476	void HDMI_TX_Set_TMDS_Emp_Internal(void)
3477	{
3478	unsigned char reg_val, c;
3479	HDMI_TX_TMDS_EMP d0_val, d1_val, d2_val, clk_val;
3480
3481	if (HDMI_TX_Get_TMDS_Clk() > 165000000)
3482	{
3483	d0_val = &tmds_d0_emp_hs;
3484	d1_val = &tmds_d1_emp_hs;
3485	d2_val = &tmds_d2_emp_hs;
3486	clk_val = &tmds_clk_emp_hs;
3487	}
3488	else
3489	{
3490	d0_val = &tmds_d0_emp_ls;
3491	d1_val = &tmds_d1_emp_ls;
3492	d2_val = &tmds_d2_emp_ls;
3493	clk_val = &tmds_clk_emp_ls;
3494	}
3495
3496	printf("\|%s\| Set TMDS D0 pre-emphasis : ", __FUNCTION__);
3497	switch (*d0_val)
3498	{
3499	case HDMI_TX_TMDS_EMP_150:
3500	reg_val = 0x03;
3501	printf("150");
3502	break;
3503	case HDMI_TX_TMDS_EMP_100:
3504	reg_val = 0x02;
3505	printf("100");
3506	break;
3507	case HDMI_TX_TMDS_EMP_50:
3508	reg_val = 0x01;
3509	printf("50");
3510	break;
3511	default:
3512	case HDMI_TX_TMDS_EMP_0:
3513	reg_val = 0x00;
3514	printf("0");
3515	break;
3516	}
3517	printf("mV\n");
3518
3519	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH0_CONFIG_REG, &c);
3520	if ((c & 0x03) != reg_val)
3521	{
3522	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH0_CONFIG_REG, ((c & ~0x03) \| reg_val));
3523	}
3524
3525	printf("\|%s\| Set TMDS D1 pre-emphasis : ", __FUNCTION__);
3526	switch (*d1_val)
3527	{
3528	case HDMI_TX_TMDS_EMP_150:
3529	reg_val = 0x03;
3530	printf("150");
3531	break;
3532	case HDMI_TX_TMDS_EMP_100:
3533	reg_val = 0x02;
3534	printf("100");
3535	break;
3536	case HDMI_TX_TMDS_EMP_50:
3537	reg_val = 0x01;
3538	printf("50");
3539	break;
3540	default:
3541	case HDMI_TX_TMDS_EMP_0:
3542	reg_val = 0x00;
3543	printf("0");
3544	break;
3545	}
3546	printf("mV\n");
3547
3548	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH1_CONFIG_REG, &c);
3549	if ((c & 0x03) != reg_val)
3550	{
3551	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH1_CONFIG_REG, ((c & ~0x03) \| reg_val));
3552	}
3553
3554	printf("\|%s\| Set TMDS D2 pre-emphasis : ", __FUNCTION__);
3555	switch (*d2_val)
3556	{
3557	case HDMI_TX_TMDS_EMP_150:
3558	reg_val = 0x03;
3559	printf("150");
3560	break;
3561	case HDMI_TX_TMDS_EMP_100:
3562	reg_val = 0x02;
3563	printf("100");
3564	break;
3565	case HDMI_TX_TMDS_EMP_50:
3566	reg_val = 0x01;
3567	printf("50");
3568	break;
3569	default:
3570	case HDMI_TX_TMDS_EMP_0:
3571	reg_val = 0x00;
3572	printf("0");
3573	break;
3574	}
3575	printf("mV\n");
3576
3577	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CH2_CONFIG_REG, &c);
3578	if ((c & 0x03) != reg_val)
3579	{
3580	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CH2_CONFIG_REG, ((c & ~0x03) \| reg_val));
3581	}
3582
3583	printf("\|%s\| Set TMDS Clk pre-emphasis : ", __FUNCTION__);
3584	switch (*clk_val)
3585	{
3586	case HDMI_TX_TMDS_EMP_150:
3587	reg_val = 0x03;
3588	printf("150");
3589	break;
3590	case HDMI_TX_TMDS_EMP_100:
3591	reg_val = 0x02;
3592	printf("100");
3593	break;
3594	case HDMI_TX_TMDS_EMP_50:
3595	reg_val = 0x01;
3596	printf("50");
3597	break;
3598	default:
3599	case HDMI_TX_TMDS_EMP_0:
3600	reg_val = 0x00;
3601	printf("0");
3602	break;
3603	}
3604	printf("mV\n");
3605
3606	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, &c);
3607	if ((c & 0x03) != reg_val)
3608	{
3609	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, ((c & ~0x03) \| reg_val));
3610	}
3611	}
3612
3613	void HDMI_TX_Set_TMDS_Emp_LS(HDMI_TX_TMDS_EMP d0_val, HDMI_TX_TMDS_EMP d1_val, HDMI_TX_TMDS_EMP d2_val, HDMI_TX_TMDS_EMP clk_val)
3614	{
3615	tmds_d0_emp_ls = d0_val;
3616	tmds_d1_emp_ls = d1_val;
3617	tmds_d2_emp_ls = d2_val;
3618	tmds_clk_emp_ls = clk_val;
3619
3620	HDMI_TX_Set_TMDS_Emp_Internal();
3621	}
3622
3623	void HDMI_TX_Set_TMDS_Emp_HS(HDMI_TX_TMDS_EMP d0_val, HDMI_TX_TMDS_EMP d1_val, HDMI_TX_TMDS_EMP d2_val, HDMI_TX_TMDS_EMP clk_val)
3624	{
3625	tmds_d0_emp_hs = d0_val;
3626	tmds_d1_emp_hs = d1_val;
3627	tmds_d2_emp_hs = d2_val;
3628	tmds_clk_emp_hs = clk_val;
3629
3630	HDMI_TX_Set_TMDS_Emp_Internal();
3631	}
3632
3633	HDMI_TX_TMDS_CD HDMI_TX_Get_TMDS_ColorDepth(void)
3634	{
3635	HDMI_TX_TMDS_CD color_depth;
3636	unsigned char c;
3637
3638	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
3639	c = c & 0x60;
3640	switch (c)
3641	{
3642	case 0x20:
3643	color_depth = HDMI_TX_TMDS_CD_30BIT;
3644	break;
3645	case 0x40:
3646	color_depth = HDMI_TX_TMDS_CD_36BIT;
3647	break;
3648	case 0x00:
3649	default:
3650	color_depth = HDMI_TX_TMDS_CD_24BIT;
3651	break;
3652	}
3653
3654	return color_depth;
3655	}
3656
3657	HDMI_TX_TMDS_CS HDMI_TX_Get_TMDS_ColorSpace(void)
3658	{
3659	HDMI_TX_TMDS_CS color_space;
3660	unsigned char c;
3661
3662	DHL_SYS_ANXRead(1,0x04, &c);
3663	c = (c & 0x60) >> 5;
3664	switch(c)
3665	{
3666	case HDMI_TX_YCbCr422:
3667	color_space = HDMI_TX_TMDS_CS_YCC422;
3668	break;
3669	case HDMI_TX_YCbCr444:
3670	color_space = HDMI_TX_TMDS_CS_YCC444;
3671	break;
3672	case HDMI_TX_RGB:
3673	default:
3674	color_space = HDMI_TX_TMDS_CS_RGB;
3675	break;
3676	}
3677
3678	return color_space;
3679	}
3680	int HDMI_TX_Is_Set_DCY444(void)
3681	{
3682	return hdmi_tx_edid_result.DC_Y444;
3683	}
3684
3685	void HDMI_TX_Hardware_Initial()
3686	{
3687	BYTE c;
3688	TT();
3689	HDMI_TX_Hardware_Reset();
3690	//Power on I2C
3691	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL3_REG, &c);
3692	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL3_REG, (c \| HDMI_TX_SYS_CTRL3_I2C_PWON));
3693
3694	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, 0x00);
3695	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, 0x00);
3696	//clear HDCP_HPD_RST
3697	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
3698	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c & 0xbf);
3699	//Power on Audio capture and Video capture module clock
3700	DHL_SYS_ANXRead(0, HDMI_TX_SYS_PD_REG, &c);
3701	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_PD_REG, (c \| 0x06));
3702	//Initial Interrupt
3703	// disable video/audio CLK,Format change and before config video.
3704	DHL_SYS_ANXWrite(0, HDMI_TX_INTR1_MASK_REG, 0x0c);//3
3705	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c);
3706	DHL_SYS_ANXWrite(0, HDMI_TX_INTR2_MASK_REG, 0x9f);
3707	DHL_SYS_ANXWrite(0, HDMI_TX_INTR3_MASK_REG, 0x1a);
3708
3709	//Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field
3710	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN0_REG, 0x10);
3711	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN1_REG, 0xeb);
3712	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_BLUESCREEN2_REG, 0x10);
3713
3714	//Set registers of PLL loop bit and swing when using R_BIAS(680 Ohm)
3715	HDMI_TX_Set_TMDS_Amp_Internal();
3716	HDMI_TX_Set_TMDS_Emp_Internal();
3717
3718	DHL_SYS_ANXWrite(0, HDMI_TX_PLLF_CTRL2_REG, 0x19);
3719	DHL_SYS_ANXWrite(0, HDMI_TX_TX_PLL_CTRL2_REG, 0xd9);
3720	//For worse input pixel clock
3721	DHL_SYS_ANXRead(0, HDMI_TX_PLL_MISC_CTRL1_REG, &c);
3722	DHL_SYS_ANXWrite(0, HDMI_TX_PLL_MISC_CTRL1_REG, (c \| 0x20));
3723
3724	DHL_SYS_ANXRead(0, HDMI_TX_PLL_MISC_CTRL0_REG, &c);
3725	DHL_SYS_ANXWrite(0, HDMI_TX_PLL_MISC_CTRL0_REG, (c & ~0x20));
3726
3727	DHL_SYS_ANXRead(0, HDMI_TX_PLL_MISC_CTRL0_REG, &c);
3728	DHL_SYS_ANXWrite(0, HDMI_TX_PLL_MISC_CTRL0_REG, (c \| HDMI_TX_PLL_MISC_CTRL0_FORCE_PLLF_LOCK));
3729
3730
3731	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAP_CTRL3_REG, 0x0F );
3732	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL2_REG, 0x5f );
3733
3734	//72:e2
3735	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_REPEATER_READY_WAIT_TIMER_REG, 0xbb);//wait 5s for KSVFIFO ready. 4.2s==0x83==>5s==0x9c. SY.
3736	//72:e0, 120ms delay in between sending AN and read R0
3737	DHL_SYS_ANXWrite(0,HDMI_TX_HDCP_WAIT_R0_TIMING_REG, 0xb4);//~120 ms, wait a bit longer. original 100 ms may cause failure when testing HDCP with QDI 882CA. SY.
3738
3739	#if 0
3740	if(!BIST_EN)//not BIST mode
3741	#endif
3742	{
3743	HDMI_TX_HW_Vid_Testing();
3744	}
3745
3746	//Config the embeded blue screen format according to output video format.
3747	HDMI_TX_Blue_Screen_Format_Config();
3748
3749	HDMI_TX_Parse_Video_Format();
3750
3751	HDMI_TX_Video_Interface_HW_Setting();
3752
3753	HDMI_TX_Set_System_State(HDMI_TX_WAIT_HOTPLUG);
3754	}
3755
3756	void HDMI_TX_API_Initial()
3757	{
3758	TT();
3759	HDMI_TX_DebugPrintf("HDMI_TX SingleCPU FirmWare version: %.2f\n",HDMI_TX_FW_VER);
3760	HDMI_TX_Set_System_State(HDMI_TX_INITIAL);
3761	HDMI_TX_Variable_Initial();
3762	HDMI_TX_HW_Interface_Variable_Initial();
3763	HDMI_TX_Hardware_Initial();
3764	}
3765
3766	void HDMI_TX_Interrupt_Information(BYTE c, BYTE n)
3767	{
3768	BYTE TX_is_HDMI,c1;
3769	TT();
3770	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c1);
3771	TX_is_HDMI = c1 & 0x02;
3772
3773	switch (n)
3774	{
3775	case 1:
3776	if (c & HDMI_TX_INTR1_STATUS_CLK_CHG)
3777	HDMI_TX_DebugPrintf("HDMI_TX_Int: Video input clock change detected.\n");
3778	if ((c & HDMI_TX_INTR1_STATUS_CTS_OVRWR) && (TX_is_HDMI == 0x02))
3779	HDMI_TX_DebugPrintf("HDMI_TX_Int: Audio CTS is overwrite before sending by ACR packer.\n");
3780	if (c & HDMI_TX_INTR1_STATUS_HP_CHG)
3781	HDMI_TX_DebugPrintf("HDMI_TX_Int: Hotplug change detected.\n");
3782	if (c & HDMI_TX_INTR1_STATUS_SW_INT)
3783	HDMI_TX_DebugPrintf("HDMI_TX_Int: Software induced interrupt.\n");
3784	if ((c & HDMI_TX_INTR1_STATUS_SPDIF_ERR)&& (TX_is_HDMI == 0x02))
3785	HDMI_TX_DebugPrintf("HDMI_TX_Int: S/PDIF parity errors.\n");
3786	if ((c & HDMI_TX_INTR1_STATUS_AFIFO_OVER)&& (TX_is_HDMI == 0x02))
3787	HDMI_TX_DebugPrintf("HDMI_TX_Int: Audio FIFO is overrun.\n");
3788	if ((c & HDMI_TX_INTR1_STATUS_AFIFO_UNDER)&& (TX_is_HDMI == 0x02))
3789	HDMI_TX_DebugPrintf("HDMI_TX_Int: Audio FIFO is underrun.\n");
3790	if ((c & HDMI_TX_INTR1_STATUS_CTS_CHG)&& (TX_is_HDMI == 0x02))
3791	HDMI_TX_DebugPrintf("HDMI_TX_Int: Audio CTS changed.\n");
3792	break;
3793	case 2:
3794	if (c & HDMI_TX_INTR2_STATUS_AUTH_DONE)
3795	HDMI_TX_DebugPrintf("HDMI_TX_Int: HDCP authentication ended.\n");
3796	if (c & HDMI_TX_INTR2_STATUS_AUTH_CHG)
3797	HDMI_TX_DebugPrintf("HDMI_TX_Int: Hardware HDCP authentication state changed.\n");
3798	if (c & HDMI_TX_INTR2_STATUS_SHA_DONE)
3799	HDMI_TX_DebugPrintf("HDMI_TX_Int: Hardware HDCP computing V ended.\n");
3800	if (c & HDMI_TX_INTR2_STATUS_PLLLOCK_CHG)
3801	HDMI_TX_DebugPrintf("HDMI_TX_Int: PLL clock state changed.\n");
3802	if (c & HDMI_TX_INTR2_STATUS_BKSV_RDY)
3803	HDMI_TX_DebugPrintf("HDMI_TX_Int: BKSV ready for check.\n");
3804	if (c & HDMI_TX_INTR2_STATUS_HDCPENHC_CHK)
3805	HDMI_TX_DebugPrintf("HDMI_TX_Int: Enhanced link verification is need.\n");
3806	if (c & HDMI_TX_INTR2_STATUS_HDCPLINK_CHK)
3807	HDMI_TX_DebugPrintf("HDMI_TX_Int: Link integrity check is need.\n");
3808	if (c & HDMI_TX_INTR2_STATUS_ENCEN_CHG)
3809	HDMI_TX_DebugPrintf("HDMI_TX_Int: ENC_EN changed detected.\n");
3810	//DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
3811	//DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, c \| (HDMI_TX_HDCP_CTRL0_RX_REP));
3812	if(hdmi_tx_HDCP_enable){
3813	;//DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, 0x40);
3814	}
3815	break;
3816	case 3:
3817	if ((c & HDMI_TX_INTR3_STATUS_SPDIF_UNSTBL)&& (TX_is_HDMI == 0x02))
3818	;//HDMI_TX_DebugPrintf("HDMI_TX_Int: Not find expected preamble for SPDIF input.\n");
3819	if (c & HDMI_TX_INTR3_STATUS_RXSEN_CHG)
3820	HDMI_TX_DebugPrintf("HDMI_TX_Int: Receiver active sense changed.\n");
3821	if (c & HDMI_TX_INTR3_STATUS_VSYNC_DET)
3822	HDMI_TX_DebugPrintf("HDMI_TX_Int: VSYNC active edge detected.\n");
3823	if (c & HDMI_TX_INTR3_STATUS_DDC_NOACK)
3824	HDMI_TX_DebugPrintf("HDMI_TX_Int: DDC master not detected any ACK.\n");
3825	if (c & HDMI_TX_INTR3_STATUS_DDCACC_ERR)
3826	HDMI_TX_DebugPrintf("HDMI_TX_Int: DDC channel access error.\n");
3827	if ((c & HDMI_TX_INTR3_STATUS_AUDCLK_CHG)&& (TX_is_HDMI == 0x02))
3828	HDMI_TX_DebugPrintf("HDMI_TX_Int: Audio input clock changed.\n");
3829	if (c & HDMI_TX_INTR3_STATUS_VIDF_CHG)
3830	HDMI_TX_DebugPrintf("HDMI_TX_Int: Video input format changed.\n");
3831	if ((c & HDMI_TX_INTR3_STATUS_SPDIFBI_ERR )&& (TX_is_HDMI == 0x02))
3832	HDMI_TX_DebugPrintf("HDMI_TX_Int: SPDIF bi-phase error.\n");
3833	break;
3834	}
3835	}
3836
3837	void HDMI_TX_Interrupt_Process()
3838	{
3839	BYTE c,c1;
3840	BYTE s1, s2, s3;
3841	TT();
3842	//monitor if hdmi_tx has been reset wrongly.
3843	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c);
3844	if(c == 0)
3845	restart_system = 1;
3846
3847	if(HDMI_TX_system_state == HDMI_TX_INITIAL)
3848	return;
3849	if(HDMI_TX_system_state == HDMI_TX_WAIT_HOTPLUG)
3850	{
3851	BYTE s4;
3852
3853	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_STATUS_REG, &s1);
3854	DHL_SYS_ANXWrite(0, HDMI_TX_INTR1_STATUS_REG, s1);
3855	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &s4);
3856	if((s1 & HDMI_TX_INTR1_STATUS_HP_CHG) \|\| (s4 & HDMI_TX_SYS_STATE_HP))
3857	HDMI_TX_Hotplug_Change_Interrupt();
3858	}
3859	else
3860	{
3861	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_STATUS_REG, &s1);
3862	DHL_SYS_ANXWrite(0, HDMI_TX_INTR1_STATUS_REG, s1);
3863	DHL_SYS_ANXRead(0, HDMI_TX_INTR1_MASK_REG, &c1);
3864	HDMI_TX_Interrupt_Information((s1 & c1), 1);
3865
3866	DHL_SYS_ANXRead(0, HDMI_TX_INTR2_STATUS_REG, &s2);
3867	DHL_SYS_ANXWrite(0, HDMI_TX_INTR2_STATUS_REG, s2);
3868	DHL_SYS_ANXRead(0, HDMI_TX_INTR2_MASK_REG, &c1);
3869	HDMI_TX_Interrupt_Information((s2 & c1), 2);
3870
3871	DHL_SYS_ANXRead(0, HDMI_TX_INTR3_STATUS_REG, &s3);
3872	DHL_SYS_ANXWrite(0, HDMI_TX_INTR3_STATUS_REG, s3);
3873	DHL_SYS_ANXRead(0, HDMI_TX_INTR3_MASK_REG, &c1);
3874	HDMI_TX_Interrupt_Information((s3 & c1), 3);
3875
3876	if(s1 & HDMI_TX_INTR1_STATUS_HP_CHG)
3877	HDMI_TX_Hotplug_Change_Interrupt();
3878
3879	if(s1 & HDMI_TX_INTR1_STATUS_CLK_CHG)
3880	HDMI_TX_Video_Clock_Change_Interrupt();
3881
3882	if(s3 & HDMI_TX_INTR3_STATUS_VIDF_CHG)
3883	HDMI_TX_Video_Format_Change_Interrupt();
3884	if(s2 & HDMI_TX_INTR2_STATUS_AUTH_DONE)
3885	HDMI_TX_Auth_Done_Interrupt();
3886
3887	if(s2 & HDMI_TX_INTR2_STATUS_AUTH_CHG)
3888	HDMI_TX_Auth_Change_Interrupt();
3889
3890	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
3891	c = c & 0x02; // HDMI mode
3892	if(c == 0x02)
3893	{
3894	if(s3 & HDMI_TX_INTR3_STATUS_AUDCLK_CHG)
3895	HDMI_TX_Audio_CLK_Change_Interrupt();
3896	if(s1 & HDMI_TX_INTR1_STATUS_AFIFO_OVER)
3897	HDMI_TX_AFIFO_Overrun_Interrupt();
3898
3899	// SPDIF error
3900	if((s3 & 0x81) \|\| (s1 & HDMI_TX_INTR1_STATUS_SPDIF_ERR))
3901	{
3902	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c1);
3903	if( c1 & HDMI_TX_HDMI_AUDCTRL1_SPDIFIN_EN)
3904	{
3905	HDMI_TX_SPDIF_Error_Interrupt(s1,s3);
3906	}
3907	}
3908	else
3909	{
3910	if(spdif_error_cnt > 0 && HDMI_TX_system_state == HDMI_TX_PLAY_BACK) spdif_error_cnt --;
3911	if(spdif_error_cnt > 0 && HDMI_TX_system_state < HDMI_TX_CONFIG_AUDIO) spdif_error_cnt = 0x00;
3912	}
3913	}
3914
3915	if(s2 & HDMI_TX_INTR2_STATUS_PLLLOCK_CHG)
3916	HDMI_TX_PllLock_Interrupt();
3917	/*
3918	if(s3 & HDMI_TX_INTR3_STATUS_RXSEN_CHG)
3919	{
3920	HDMI_TX_Rx_Sense_Interrupt();
3921	}
3922	*/
3923	}
3924	//}
3925	}
3926
3927	BYTE HDMI_TX_Parse_EDID(void)
3928	{
3929	TT();
3930	//BYTE c,c1,j;
3931
3932	HDMI_TX_GetEDIDLength();
3933
3934	HDMI_TX_DebugPrintf("EDIDLength is %d\n", hdmi_tx_edid_length);
3935
3936	HDMI_TX_Read_EDID();
3937
3938	if(!(HDMI_TX_Parse_EDIDHeader()))
3939	{
3940	HDMI_TX_DebugPrintf("BAD EDID Header, Stop parsing \n");
3941	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_BadHeader;
3942	return hdmi_tx_edid_result.edid_errcode;
3943	}
3944
3945	if(!(HDMI_TX_Parse_EDIDVersion()))
3946	{
3947	HDMI_TX_DebugPrintf("EDID does not support 861B, Stop parsing\n");
3948	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_861B_not_supported;
3949	return hdmi_tx_edid_result.edid_errcode;
3950	}
3951
3952	if(HDMI_TX_EDID_Checksum(0) == 0)
3953	{
3954	HDMI_TX_DebugPrintf("EDID Block one check sum error, Stop parsing\n");
3955	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_CheckSum_ERR;
3956	return hdmi_tx_edid_result.edid_errcode;
3957	}
3958
3959	HDMI_TX_Parse_DTDinBlockONE();
3960
3961	if(HDMI_TX_Read_EDID_BYTE(0, 0x7e) == 0)
3962	{
3963	HDMI_TX_DebugPrintf("No EDID extension blocks.\n");
3964	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_No_ExtBlock;
3965	return hdmi_tx_edid_result.edid_errcode;
3966	}
3967
3968	HDMI_TX_Parse_NativeFormat();
3969	HDMI_TX_Parse_ExtBlock();
3970
3971	if(hdmi_tx_edid_result.edid_errcode == 0x05)
3972	return hdmi_tx_edid_result.edid_errcode;
3973
3974	if(hdmi_tx_edid_result.edid_errcode == 0x03)
3975	return hdmi_tx_edid_result.edid_errcode;
3976
3977	HDMI_TX_DebugPrintf("EDID parsing finished!\n");
3978	HDMI_TX_EDID_Parsing_Result();
3979
3980	return 0;
3981	}
3982
3983	void HDMI_TX_GetEDIDLength()
3984	{
3985	BYTE edid_data_length;
3986	TT();
3987	HDMI_TX_RST_DDCChannel();
3988
3989	edid_data_length = HDMI_TX_Read_RealEDID_BYTE(0x00, 0x7e);
3990
3991	hdmi_tx_edid_length = edid_data_length * 128 + 128;
3992
3993	}
3994	void HDMI_TX_Read_EDID(void)
3995	{
3996	BYTE edid_segment,segmentpointer,k;
3997	TT();
3998	HDMI_TX_RST_DDCChannel();
3999
4000	edid_segment = hdmi_tx_edid_length / 256;
4001	if(edid_segment==0)
4002	segmentpointer =0;
4003	else
4004	segmentpointer = edid_segment - 1;
4005
4006	for(k = 0; k <= segmentpointer; k ++)
4007	{
4008	HDMI_TX_InitDDC_Read(0xa0, k, 0x00, 0x80, 0x00);
4009	HDMI_TX_DDC_Mass_Read(128, hdmi_tx_edid_buf);
4010	HDMI_TX_InitDDC_Read(0xa0, k, 0x80, 0x80, 0x00);
4011	HDMI_TX_DDC_Mass_Read(128, &hdmi_tx_edid_buf[128]);
4012	}
4013
4014	if((hdmi_tx_edid_length - 256 * edid_segment) == 0)
4015	HDMI_TX_DebugPrintf("Finish reading EDID\n");
4016	else
4017	{
4018	HDMI_TX_DebugPrintf("Read one more block(128 bytes).........\n");
4019	HDMI_TX_InitDDC_Read(0xa0, segmentpointer + 1, 0x00, 0x80, 0x00);
4020	HDMI_TX_DDC_Mass_Read(128, &hdmi_tx_edid_buf[256]);
4021	HDMI_TX_DebugPrintf("Finish reading EDID\n");
4022	}
4023
4024	valid_hdmi_tx_edid = 1;
4025	if (cb_HPDCallback)
4026	{
4027	(cb_HPDCallback)();
4028	}
4029	}
4030
4031	void HDMI_TX_DDC_Mass_Read(WORD length, BYTE *buf)
4032	{
4033	WORD i, j;
4034	BYTE c, c1,ddc_empty_cnt;
4035	TT();
4036	i = length;
4037	while (i > 0)
4038	{
4039	//check DDC FIFO statue
4040	DHL_SYS_ANXRead(0, HDMI_TX_DDC_CHSTATUS_REG, &c);
4041	if(c & HDMI_TX_DDC_CHSTATUS_DDC_OCCUPY)
4042	{
4043	//HDMI_TX_DebugPrintf("HDMI_TX DDC channel is accessed by an external device, break!.\n");
4044	break;
4045	}
4046	if(c & HDMI_TX_DDC_CHSTATUS_FIFO_FULL)
4047	hdmi_tx_ddc_fifo_full = 1;
4048	else
4049	hdmi_tx_ddc_fifo_full = 0;
4050	if(c & HDMI_TX_DDC_CHSTATUS_INPRO)
4051	hdmi_tx_ddc_progress = 1;
4052	else
4053	hdmi_tx_ddc_progress = 0;
4054	if(hdmi_tx_ddc_fifo_full)
4055	{
4056	//HDMI_TX_DebugPrintf("DDC FIFO is full during edid reading\n");
4057	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFOCNT_REG, &c);
4058	//HDMI_TX_DebugPrintf("FIFO counter is %.2x\n", (WORD) c);
4059	i = i - c;
4060	for(j=0; j<c; j++)
4061	{
4062	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &c1);
4063	if(HDMI_TX_system_state == HDMI_TX_READ_PARSE_EDID);
4064	// HDMI_TX_DebugPrintf("DDC_data[%u]=0x%.2x\n", (length -(i+c-j)), (WORD) c1);
4065	// if ((length -(i+c-j)) < HDMI_TX_EDID_BUF_SIZE)
4066	// {
4067	buf[length -(i+c-j)] = c1;
4068	// }
4069	hdmi_tx_ddc_fifo_full = 0;
4070	}
4071	//HDMI_TX_DebugPrintf("\n");
4072	}
4073	else if(!hdmi_tx_ddc_progress)
4074	{
4075	//HDMI_TX_DebugPrintf("HDMI_TX DDC FIFO access finished.\n");
4076	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFOCNT_REG, &c);
4077	//HDMI_TX_DebugPrintf("FIFO counter is %.2x\n", (WORD) c);
4078	if(!c)
4079	{
4080	i =0;
4081	break;
4082	}
4083	i = i - c;
4084	for(j=0; j<c; j++)
4085	{
4086	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &c1);
4087	if(HDMI_TX_system_state == HDMI_TX_READ_PARSE_EDID) ;
4088	// HDMI_TX_DebugPrintf("DDC_data[%u]=0x%.2x\n", (length-(i+c-j)), (WORD) c1);
4089	// if ((length -(i+c-j)) < HDMI_TX_EDID_BUF_SIZE)
4090	// {
4091	buf[length -(i+c-j)] = c1;
4092	// }
4093	}
4094	//HDMI_TX_DebugPrintf("\ni=%d\n", i);
4095	}
4096	else
4097	{
4098	ddc_empty_cnt = 0x00;
4099	for(c1=0; c1<0x0a; c1++)
4100	{
4101	DHL_SYS_ANXRead(0, HDMI_TX_DDC_CHSTATUS_REG, &c);
4102	//HDMI_TX_DebugPrintf("DDC FIFO access is progressing.\n");
4103	//HDMI_TX_DebugPrintf("DDC Channel status is 0x%.2x\n",(WORD)c);
4104	if(c & HDMI_TX_DDC_CHSTATUS_FIFO_EMPT)
4105	ddc_empty_cnt++;
4106	OS_mDelay(5);
4107	//HDMI_TX_DebugPrintf("ddc_empty_cnt = 0x%.2x\n",(WORD)ddc_empty_cnt);
4108	}
4109	if(ddc_empty_cnt >= 0x0a)
4110	i = 0;
4111	}
4112	}
4113	}
4114
4115
4116	BYTE HDMI_TX_Parse_EDIDHeader(void)
4117	{
4118	BYTE i,temp;
4119	TT();
4120	temp = 0;
4121	// the EDID header should begin with 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00
4122	if((HDMI_TX_Read_EDID_BYTE(0, 0) == 0x00) && (HDMI_TX_Read_EDID_BYTE(0, 7) == 0x00))
4123	{
4124	for(i = 1; i < 7; i++)
4125	{
4126	if(HDMI_TX_Read_EDID_BYTE(0, i) != 0xff)
4127	{
4128	HDMI_TX_DebugPrintf("i = %d\n", i);
4129	temp = 0x01;
4130	break;
4131	}
4132	}
4133	}
4134	else
4135	{
4136	temp = 0x01;
4137	}
4138	if(temp == 0x01)
4139	{
4140	return 0;
4141	}
4142	else
4143	{
4144	return 1;
4145	}
4146	}
4147
4148	BYTE HDMI_TX_Parse_EDIDVersion(void)
4149	{
4150	TT();
4151	if(!((HDMI_TX_Read_EDID_BYTE(0, 0x12) == 1) && (HDMI_TX_Read_EDID_BYTE(0, 0x13) >= 3) ))
4152	{
4153	return 0;
4154	}
4155	else
4156	{
4157	return 1;
4158	}
4159	}
4160
4161	BYTE HDMI_TX_Parse_ExtBlock()
4162	{
4163	BYTE i,c;
4164	TT();
4165	for(i = 0; i < HDMI_TX_Read_EDID_BYTE(0, 0x7e); i++) //read in blocks
4166	{
4167	c = HDMI_TX_Read_EDID_BYTE(i/2, 0x80 + (0x80 * i));
4168	if( c == 0x02)
4169	{
4170	hdmi_tx_ext_block_num = i + 1;
4171	HDMI_TX_Parse_DTDinExtBlock();
4172	HDMI_TX_Parse_STD();
4173	if(!(HDMI_TX_EDID_Checksum(hdmi_tx_ext_block_num)))
4174	{
4175	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_CheckSum_ERR;
4176	return hdmi_tx_edid_result.edid_errcode;
4177	}
4178	}
4179	else
4180	{
4181	hdmi_tx_edid_result.edid_errcode = HDMI_TX_EDID_ExtBlock_NotFor_861B;
4182	return hdmi_tx_edid_result.edid_errcode;
4183	}
4184	}
4185
4186	return 0;
4187	}
4188
4189	void HDMI_TX_Parse_DTDinBlockONE()
4190	{
4191	BYTE i;
4192	TT();
4193	for(i = 0; i < 18; i++)
4194	{
4195	hdmi_tx_edid_dtd[i] = HDMI_TX_Read_EDID_BYTE(0, (i + 0x36));
4196	}
4197	//HDMI_TX_DebugPrintf("Parse the first DTD in Block one:\n");
4198	HDMI_TX_Parse_DTD();
4199
4200	if((HDMI_TX_Read_EDID_BYTE(0, 0x48) == 0)
4201	&& (HDMI_TX_Read_EDID_BYTE(0, 0x49) == 0)
4202	&& (HDMI_TX_Read_EDID_BYTE(0, 0x4a) == 0))
4203	{
4204	;//HDMI_TX_DebugPrintf("the second DTD in Block one is not used to descript video timing.\n");
4205	}
4206	else
4207	{
4208	for(i = 0; i < 18; i++)
4209	{
4210	hdmi_tx_edid_dtd[i] = HDMI_TX_Read_EDID_BYTE(0, (i + 0x48));
4211	}
4212	HDMI_TX_Parse_DTD();
4213	}
4214
4215	if((HDMI_TX_Read_EDID_BYTE(0,0x5a) == 0)
4216	&& (HDMI_TX_Read_EDID_BYTE(0,0x5b) == 0)
4217	&& (HDMI_TX_Read_EDID_BYTE(0,0x5c) == 0))
4218	{
4219	;//HDMI_TX_DebugPrintf("the third DTD in Block one is not used to descript video timing.\n");
4220	}
4221	else
4222	{
4223	for(i = 0; i < 18; i++)
4224	{
4225	hdmi_tx_edid_dtd[i] = HDMI_TX_Read_EDID_BYTE(0, (i + 0x5a));
4226	}
4227	HDMI_TX_Parse_DTD();
4228	}
4229
4230	if((HDMI_TX_Read_EDID_BYTE(0,0x6c) == 0)
4231	&& (HDMI_TX_Read_EDID_BYTE(0,0x6d) == 0)
4232	&& (HDMI_TX_Read_EDID_BYTE(0,0x6e) == 0))
4233	{
4234	;//HDMI_TX_DebugPrintf("the fourth DTD in Block one is not used to descript video timing.\n");
4235	}
4236	else
4237	{
4238	for(i = 0; i < 18; i++)
4239	{
4240	hdmi_tx_edid_dtd[i] = HDMI_TX_Read_EDID_BYTE(0,(i + 0x6c));
4241	}
4242	HDMI_TX_Parse_DTD();
4243	}
4244	}
4245
4246	void HDMI_TX_Parse_DTDinExtBlock()
4247	{
4248	BYTE i,DTDbeginAddr;
4249	TT();
4250	DTDbeginAddr = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2, (0x02 + 0x80 * hdmi_tx_ext_block_num))
4251	+ 0x80 * hdmi_tx_ext_block_num;
4252	while(DTDbeginAddr < (0x6c + 0x80 * hdmi_tx_ext_block_num))
4253	{
4254	if((HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,DTDbeginAddr) == 0)
4255	&& (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(DTDbeginAddr + 1)) == 0)
4256	&& (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(DTDbeginAddr + 2)) == 0))
4257	{
4258	;//HDMI_TX_DebugPrintf("this DTD in Extension Block is not used to descript video timing.\n");
4259	}
4260	else
4261	{
4262	for(i = 0; i < 18; i++)
4263	{
4264	hdmi_tx_edid_dtd[i] = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(i + DTDbeginAddr));
4265	}
4266	//HDMI_TX_DebugPrintf("Parse the DTD in Extension Block :\n");
4267	HDMI_TX_Parse_DTD();
4268	}
4269	DTDbeginAddr = DTDbeginAddr + 18;
4270	}
4271	}
4272
4273	void HDMI_TX_Parse_DTD()
4274	{
4275	WORD temp;
4276	unsigned long temp1,temp2;
4277	WORD Hresolution,Vresolution,Hblanking,Vblanking;
4278	WORD PixelCLK,Vtotal,H_image_size,V_image_size;
4279	BYTE Hz;
4280	//float Ratio;
4281	TT();
4282	temp = hdmi_tx_edid_dtd[1];
4283	temp = temp << 8;
4284	PixelCLK = temp + hdmi_tx_edid_dtd[0];
4285	// HDMI_TX_DebugPrintf("Pixel clock is 10000 * %u\n", temp);
4286
4287	temp = hdmi_tx_edid_dtd[4];
4288	temp = (temp << 4) & 0x0f00;
4289	Hresolution = temp + hdmi_tx_edid_dtd[2];
4290	//HDMI_TX_DebugPrintf("Horizontal Active is %u\n", Hresolution);
4291
4292	temp = hdmi_tx_edid_dtd[4];
4293	temp = (temp << 8) & 0x0f00;
4294	Hblanking = temp + hdmi_tx_edid_dtd[3];
4295	//HDMI_TX_DebugPrintf("Horizontal Blanking is %u\n", temp);
4296
4297	temp = hdmi_tx_edid_dtd[7];
4298	temp = (temp << 4) & 0x0f00;
4299	Vresolution = temp + hdmi_tx_edid_dtd[5];
4300	//HDMI_TX_DebugPrintf("Vertical Active is %u\n", Vresolution);
4301
4302	temp = hdmi_tx_edid_dtd[7];
4303	temp = (temp << 8) & 0x0f00;
4304	Vblanking = temp + hdmi_tx_edid_dtd[6];
4305	//HDMI_TX_DebugPrintf("Vertical Blanking is %u\n", temp);
4306
4307	temp = hdmi_tx_edid_dtd[11];
4308	temp = (temp << 2) & 0x0300;
4309	temp = temp + hdmi_tx_edid_dtd[8];
4310	//HDMI_TX_DebugPrintf("Horizontal Sync Offset is %u\n", temp);
4311
4312	temp = hdmi_tx_edid_dtd[11];
4313	temp = (temp << 4) & 0x0300;
4314	temp = temp + hdmi_tx_edid_dtd[9];
4315	//HDMI_TX_DebugPrintf("Horizontal Sync Pulse is %u\n", temp);
4316
4317	temp = hdmi_tx_edid_dtd[11];
4318	temp = (temp << 2) & 0x0030;
4319	temp = temp + (hdmi_tx_edid_dtd[10] >> 4);
4320	//HDMI_TX_DebugPrintf("Vertical Sync Offset is %u\n", temp);
4321
4322	temp = hdmi_tx_edid_dtd[11];
4323	temp = (temp << 4) & 0x0030;
4324	temp = temp + (hdmi_tx_edid_dtd[8] & 0x0f);
4325	//HDMI_TX_DebugPrintf("Vertical Sync Pulse is %u\n", temp);
4326
4327	temp = hdmi_tx_edid_dtd[14];
4328	temp = (temp << 4) & 0x0f00;
4329	H_image_size = temp + hdmi_tx_edid_dtd[12];
4330	//HDMI_TX_DebugPrintf("Horizontal Image size is %u\n", temp);
4331
4332	temp = hdmi_tx_edid_dtd[14];
4333	temp = (temp << 8) & 0x0f00;
4334	V_image_size = temp + hdmi_tx_edid_dtd[13];
4335	//HDMI_TX_DebugPrintf("Vertical Image size is %u\n", temp);
4336
4337	//HDMI_TX_DebugPrintf("Horizontal Border is %bu\n", hdmi_tx_edid_dtd[15]);
4338
4339	//HDMI_TX_DebugPrintf("Vertical Border is %bu\n", hdmi_tx_edid_dtd[16]);
4340	/*
4341	if(hdmi_tx_edid_dtd[17] & 0x80)
4342	//HDMI_TX_DebugPrintf(" Interlaced\n");
4343	else
4344	//HDMI_TX_DebugPrintf("Non-interlaced\n \n");
4345	if(hdmi_tx_edid_dtd[17] & 0x60)
4346	//HDMI_TX_DebugPrintf("Table 3.17 for defenition\n \n");
4347	else
4348	//HDMI_TX_DebugPrintf("Normal Display\n \n");
4349	if(hdmi_tx_edid_dtd[17] & 0x10)
4350	//HDMI_TX_DebugPrintf(" Digital\n");
4351	else
4352	//HDMI_TX_DebugPrintf(" Analog\n");*/
4353	temp1 = Hresolution + Hblanking;
4354	Vtotal = Vresolution + Vblanking;
4355	temp1 = temp1 * Vtotal;
4356	temp2 = PixelCLK;
4357	temp2 = temp2 * 10000;
4358	if (temp1 == 0)
4359	Hz=0;
4360	else
4361	Hz = temp2 / temp1;
4362
4363	if((Hz == 59) \|\| (Hz == 60))
4364	{
4365	Hz = 60;
4366	//HDMI_TX_DebugPrintf("_______________Vertical Active is %u\n", Vresolution);
4367	if(Vresolution == 540)
4368	hdmi_tx_edid_result.supported_1080i_60Hz = 1;
4369	if(Vresolution == 1080)
4370	hdmi_tx_edid_result.supported_1080p_60Hz = 1;
4371	if(Vresolution == 720)
4372	hdmi_tx_edid_result.supported_720p_60Hz = 1;
4373	if((Hresolution == 640) && (Vresolution == 480))
4374	hdmi_tx_edid_result.supported_640x480p_60Hz = 1;
4375	if((Hresolution == 720) && (Vresolution == 480))
4376	hdmi_tx_edid_result.supported_720x480p_60Hz = 1;
4377	if((Hresolution == 720) && (Vresolution == 240))
4378	hdmi_tx_edid_result.supported_720x480i_60Hz = 1;
4379	}
4380	if(Hz == 50)
4381	{
4382	//HDMI_TX_DebugPrintf("+++++++++++++++Vertical Active is %u\n", Vresolution);
4383	if(Vresolution == 540)
4384	hdmi_tx_edid_result.supported_1080i_50Hz = 1;
4385	if(Vresolution == 1080)
4386	hdmi_tx_edid_result.supported_1080p_50Hz = 1;
4387	if(Vresolution == 720)
4388	hdmi_tx_edid_result.supported_720p_50Hz = 1;
4389	if(Vresolution == 576)
4390	hdmi_tx_edid_result.supported_576p_50Hz = 1;
4391	if(Vresolution == 288)
4392	hdmi_tx_edid_result.supported_576i_50Hz = 1;
4393	}
4394	//HDMI_TX_DebugPrintf("Fresh rate :% bu Hz\n", Hz);
4395	//Ratio = H_image_size;
4396	//Ratio = Ratio / V_image_size;
4397	//HDMI_TX_DebugPrintf("Picture ratio : %f \n", Ratio);
4398	}
4399
4400	void HDMI_TX_Parse_NativeFormat()
4401	{
4402	BYTE temp;
4403	TT();
4404	temp = HDMI_TX_Read_EDID_BYTE(0,0x83) & 0xf0;
4405	if(temp & 0x20)
4406	{
4407	hdmi_tx_edid_result.ycbcr444_supported= 1;
4408	}
4409	if(temp & 0x10)
4410	{
4411	hdmi_tx_edid_result.ycbcr422_supported= 1;
4412	}
4413	}
4414
4415	void HDMI_TX_Parse_STD()
4416	{
4417	BYTE DTDbeginAddr;
4418	TT();
4419	hdmi_tx_stdaddr = 0x04 + 0x80 * hdmi_tx_ext_block_num;
4420	DTDbeginAddr = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(0x02 + 0x80 * hdmi_tx_ext_block_num));
4421	DTDbeginAddr = DTDbeginAddr + 0x80 * hdmi_tx_ext_block_num;
4422	// HDMI_TX_DebugPrintf("Video DTDbeginAddr Register :%.2x\n", (WORD) DTDbeginAddr);
4423	while(hdmi_tx_stdaddr < DTDbeginAddr)
4424	{
4425	hdmi_tx_stdreg = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,hdmi_tx_stdaddr);
4426	switch(hdmi_tx_stdreg & 0xe0)
4427	{
4428	case 0x20:
4429	HDMI_TX_Parse_AudioSTD();
4430	hdmi_tx_sau_length = hdmi_tx_stdreg & 0x1f;
4431	break;
4432	case 0x40:
4433	HDMI_TX_Parse_VideoSTD();
4434	hdmi_tx_svd_length = hdmi_tx_stdreg & 0x1f;
4435	break;
4436	case 0x80:
4437	HDMI_TX_Parse_SpeakerSTD();
4438	break;
4439	case 0x60:
4440	HDMI_TX_Parse_VendorSTD();
4441	break;
4442	default:
4443	break;
4444	}
4445	hdmi_tx_stdaddr = hdmi_tx_stdaddr + (hdmi_tx_stdreg & 0x1f) + 0x01;
4446	}
4447	}
4448
4449	void HDMI_TX_Parse_AudioSTD()
4450	{
4451	BYTE i,AudioFormat,STDReg_tmp,STDAddr_tmp;
4452	TT();
4453	STDReg_tmp = hdmi_tx_stdreg & 0x1f;
4454	STDAddr_tmp = hdmi_tx_stdaddr + 1;
4455	i = 0;
4456	while(i < STDReg_tmp)
4457	{
4458	AudioFormat = (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,STDAddr_tmp ) & 0xF8) >> 3;
4459	hdmi_tx_edid_result.AudioChannel[i/3] = (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,STDAddr_tmp) & 0x07) + 1;
4460	hdmi_tx_edid_result.AudioFormat[i/3] = AudioFormat;
4461	hdmi_tx_edid_result.AudioFs[i/3] = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(STDAddr_tmp + 1)) & 0x7f;
4462
4463	if(AudioFormat == 1)
4464	hdmi_tx_edid_result.AudioLength[i/3] = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(STDAddr_tmp + 2)) & 0x07;
4465	else
4466	hdmi_tx_edid_result.AudioLength[i/3] = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(STDAddr_tmp + 2)) << 3;
4467
4468	i = i + 3;
4469	STDAddr_tmp = STDAddr_tmp + 3;
4470	}
4471	}
4472
4473	void HDMI_TX_Parse_VideoSTD()
4474	{
4475	BYTE i,STDReg_tmp,STDAddr_tmp;
4476	BYTE SVD_ID[34];
4477	TT();
4478	STDReg_tmp = hdmi_tx_stdreg & 0x1f;
4479	STDAddr_tmp = hdmi_tx_stdaddr + 1;
4480	i = 0;
4481	while(i < STDReg_tmp)
4482	{
4483	SVD_ID[i] = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,STDAddr_tmp) & 0x7F;
4484	//HDMI_TX_DebugPrintf("hdmi_tx_edid_result.SVD_ID[%.2x]=0x%.2x\n",(WORD)i,(WORD)hdmi_tx_edid_result.SVD_ID[i]);
4485	//if(HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,STDAddr_tmp) & 0x80)
4486	// HDMI_TX_DebugPrintf(" Native mode\n");
4487	if(SVD_ID[i] == 1)
4488	hdmi_tx_edid_result.supported_640x480p_60Hz = 1;
4489	else if(SVD_ID[i] == 4)
4490	hdmi_tx_edid_result.supported_720p_60Hz = 1;
4491	else if(SVD_ID[i] == 19)
4492	hdmi_tx_edid_result.supported_720p_50Hz = 1;
4493	else if(SVD_ID[i] == 16)
4494	hdmi_tx_edid_result.supported_1080p_60Hz = 1;
4495	else if(SVD_ID[i] == 31)
4496	hdmi_tx_edid_result.supported_1080p_50Hz = 1;
4497	else if(SVD_ID[i] == 5)
4498	hdmi_tx_edid_result.supported_1080i_60Hz = 1;
4499	else if(SVD_ID[i] == 20)
4500	hdmi_tx_edid_result.supported_1080i_50Hz = 1;
4501	else if((SVD_ID[i] == 2) \|\|(SVD_ID[i] == 3))
4502	hdmi_tx_edid_result.supported_720x480p_60Hz = 1;
4503	else if((SVD_ID[i] == 6) \|\|(SVD_ID[i] == 7))
4504	hdmi_tx_edid_result.supported_720x480i_60Hz = 1;
4505	else if((SVD_ID[i] == 17) \|\|(SVD_ID[i] == 18))
4506	hdmi_tx_edid_result.supported_576p_50Hz = 1;
4507	else if((SVD_ID[i] == 21) \|\|(SVD_ID[i] == 22))
4508	hdmi_tx_edid_result.supported_576i_50Hz = 1;
4509
4510	i = i + 1;
4511	STDAddr_tmp = STDAddr_tmp + 1;
4512	}
4513	}
4514
4515	void HDMI_TX_Parse_SpeakerSTD()
4516	{
4517	TT();
4518	hdmi_tx_edid_result.SpeakerFormat = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(hdmi_tx_stdaddr + 1)) ;
4519	}
4520
4521	void HDMI_TX_Parse_VendorSTD()
4522	{
4523	BYTE c;
4524	TT();
4525	if((HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(hdmi_tx_stdaddr + 1)) == 0x03)
4526	&& (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(hdmi_tx_stdaddr + 2)) == 0x0c)
4527	&& (HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(hdmi_tx_stdaddr + 3)) == 0x00))
4528	{
4529	hdmi_tx_edid_result.is_HDMI = 1;
4530	}
4531	else
4532	{
4533	hdmi_tx_edid_result.is_HDMI = 0;
4534	}
4535
4536	//deep color mode information
4537	c = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2, hdmi_tx_stdaddr) & 0x1f;
4538	if(c >= 6)
4539	{
4540	c = HDMI_TX_Read_EDID_BYTE(hdmi_tx_ext_block_num/2,(hdmi_tx_stdaddr + 6));
4541	hdmi_tx_edid_result.RGB30bit = (c & 0x10) >> 4;
4542	hdmi_tx_edid_result.RGB36bit = (c & 0x20) >> 5;
4543	hdmi_tx_edid_result.RGB48bit = (c & 0x40) >> 6;
4544	hdmi_tx_edid_result.DC_Y444 = (c & 0x08) >> 3;
4545	}
4546	}
4547
4548	BYTE HDMI_TX_EDID_Checksum(BYTE block_number)
4549	{
4550	BYTE c;
4551	TT();
4552	c = block_number;
4553	/* WORD i;
4554	BYTE edid_block_checksum;
4555
4556	edid_block_checksum = 0;
4557	for(i=(128c); i<((128c)+127); i++)
4558	{
4559	edid_block_checksum = edid_block_checksum + HDMI_TX_Read_EDID_BYTE(c/2, i);
4560	}
4561	edid_block_checksum = (~edid_block_checksum) + 1;
4562	// HDMI_TX_DebugPrintf("edid_block_checksum = 0x%.2x\n",(WORD)edid_block_checksum);
4563	if(HDMI_TX_Read_EDID_BYTE(block_number/2,((128*block_number)+127))
4564	== edid_block_checksum)
4565	return 1;
4566	else
4567	return 0;*/
4568
4569	return 1;
4570	}
4571
4572	void HDMI_TX_EDID_Parsing_Result()
4573	{
4574	BYTE i;
4575	TT();
4576	hdmi_tx_edid_result.edid_errcode = hdmi_tx_edid_result.edid_errcode;
4577	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.edid_errcode = 0x%.2x\n",(WORD)hdmi_tx_edid_result.edid_errcode);
4578	hdmi_tx_edid_result.is_HDMI = hdmi_tx_edid_result.is_HDMI;
4579	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.is_HDMI = 0x%.2x\n",(WORD)hdmi_tx_edid_result.is_HDMI);
4580	hdmi_tx_edid_result.ycbcr422_supported = hdmi_tx_edid_result.ycbcr422_supported;
4581	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.ycbcr422_supported = 0x%.2x\n",(WORD)hdmi_tx_edid_result.ycbcr422_supported);
4582	hdmi_tx_edid_result.ycbcr444_supported = hdmi_tx_edid_result.ycbcr444_supported;
4583	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.ycbcr444_supported = 0x%.2x\n",(WORD)hdmi_tx_edid_result.ycbcr444_supported);
4584	hdmi_tx_edid_result.supported_1080p_60Hz = hdmi_tx_edid_result.supported_1080p_60Hz;
4585	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_1080p_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_1080p_60Hz);
4586	hdmi_tx_edid_result.supported_1080p_50Hz = hdmi_tx_edid_result.supported_1080p_50Hz;
4587	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_1080p_50Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_1080p_50Hz);
4588	hdmi_tx_edid_result.supported_1080i_60Hz = hdmi_tx_edid_result.supported_1080i_60Hz;
4589	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_1080i_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_1080i_60Hz);
4590	hdmi_tx_edid_result.supported_1080i_50Hz = hdmi_tx_edid_result.supported_1080i_50Hz;
4591	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_1080i_50Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_1080i_50Hz);
4592	hdmi_tx_edid_result.supported_720p_60Hz = hdmi_tx_edid_result.supported_720p_60Hz;
4593	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_720p_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_720p_60Hz);
4594	hdmi_tx_edid_result.supported_720p_50Hz = hdmi_tx_edid_result.supported_720p_50Hz;
4595	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_720p_50Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_720p_50Hz);
4596	hdmi_tx_edid_result.supported_640x480p_60Hz = hdmi_tx_edid_result.supported_640x480p_60Hz;
4597	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_640x480p_60Hz);
4598	hdmi_tx_edid_result.supported_720x480p_60Hz = hdmi_tx_edid_result.supported_720x480p_60Hz;
4599	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_720x480p_60Hz);
4600	hdmi_tx_edid_result.supported_720x480i_60Hz = hdmi_tx_edid_result.supported_720x480i_60Hz;
4601	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_720x480i_60Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_720x480i_60Hz);
4602	hdmi_tx_edid_result.supported_576p_50Hz = hdmi_tx_edid_result.supported_576p_50Hz;
4603	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_576p_50Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_576p_50Hz);
4604	hdmi_tx_edid_result.supported_576i_50Hz = hdmi_tx_edid_result.supported_576i_50Hz;
4605	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.supported_576i_50Hz = 0x%.2x\n",(WORD)hdmi_tx_edid_result.supported_576i_50Hz);
4606	if(!hdmi_tx_edid_result.edid_errcode)
4607	{
4608	for(i = 0; i < hdmi_tx_sau_length/3; i++)
4609	{
4610	hdmi_tx_edid_result.AudioChannel[i] = hdmi_tx_edid_result.AudioChannel[i];
4611	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.AudioChannel = 0x%.2x\n",(WORD)hdmi_tx_edid_result.AudioChannel[i]);
4612	hdmi_tx_edid_result.AudioFormat[i] = hdmi_tx_edid_result.AudioFormat[i];
4613	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.AudioFormat = 0x%.2x\n",(WORD)hdmi_tx_edid_result.AudioFormat[i]);
4614	hdmi_tx_edid_result.AudioFs[i] = hdmi_tx_edid_result.AudioFs[i];
4615	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.AudioFs = 0x%.2x\n",(WORD)hdmi_tx_edid_result.AudioFs[i]);
4616	hdmi_tx_edid_result.AudioLength[i] = hdmi_tx_edid_result.AudioLength[i];
4617	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.AudioLength = 0x%.2x\n",(WORD)hdmi_tx_edid_result.AudioLength[i]);
4618	}
4619	hdmi_tx_edid_result.SpeakerFormat = hdmi_tx_edid_result.SpeakerFormat;
4620	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.SpeakerFormat = 0x%.2x\n",(WORD)hdmi_tx_edid_result.SpeakerFormat);
4621	}
4622
4623	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.RGB30bit = 0x%.2x\n",(WORD)hdmi_tx_edid_result.RGB30bit);
4624	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.RGB36bit = 0x%.2x\n",(WORD)hdmi_tx_edid_result.RGB36bit);
4625	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.RGB48bit = 0x%.2x\n",(WORD)hdmi_tx_edid_result.RGB48bit);
4626	HDMI_TX_DebugPrintf("hdmi_tx_edid_result.DC_444 = 0x%.2x\n",(WORD)hdmi_tx_edid_result.DC_Y444);
4627	}
4628	void HDMI_TX_InitDDC_Read(BYTE devaddr, BYTE segmentpointer,
4629	BYTE offset, BYTE access_num_Low,BYTE access_num_high)
4630	{
4631	TT();
4632	//Write slave device address
4633	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_ADDR_REG, devaddr);
4634	// Write segment address
4635	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_SEGADDR_REG, segmentpointer);
4636	//Write offset
4637	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_OFFADDR_REG, offset);
4638	//Write number for access
4639	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACCNUM0_REG, access_num_Low);
4640	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACCNUM1_REG, access_num_high);
4641	//Clear FIFO
4642	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x05);
4643
4644	if ( segmentpointer >= 1 ) {
4645	//DDC sequential Read
4646	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x04);
4647	} else {
4648	//DDC sequential Read
4649	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x01);
4650	}
4651	}
4652
4653	/*void HDMI_TX_InitDDC_Write(BYTE devaddr, BYTE segmentpointer,
4654	BYTE offset, BYTE access_num_Low,BYTE access_num_high)
4655	{
4656	//Write slave device address
4657	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_ADDR_REG, devaddr);
4658	// Write segment address
4659	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_SEGADDR_REG, segmentpointer);
4660	//Write offset
4661	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_SLV_OFFADDR_REG, offset);
4662	//Write number for access
4663	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACCNUM0_REG, access_num_Low);
4664	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACCNUM1_REG, access_num_high);
4665	//DDC sequential write
4666	DHL_SYS_ANXWrite(0, HDMI_TX_DDC_ACC_CMD_REG, 0x02);
4667	}
4668	*/
4669
4670	BYTE HDMI_TX_Read_RealEDID_BYTE(BYTE segmentpointer,BYTE offset)
4671	{
4672	BYTE c;
4673	TT();
4674	HDMI_TX_InitDDC_Read(0xa0, segmentpointer, offset, 0x01, 0x00);
4675	OS_mDelay(3);
4676	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &c);
4677
4678	return c;
4679	}
4680
4681	BYTE HDMI_TX_Read_EDID_BYTE(BYTE segmentpointer,BYTE offset)
4682	{
4683	BYTE c;
4684	TT();
4685	#if 0
4686	// ¹ÙÀÌÆ®¾¿ ÀÐ±â¿¡´Â ³Ê¹« ´À¸². µû¶ó¼ MassRead¿¡¼ ÀÐ¾î¿Â edid ¹öÆÛ¸¦ »ç¿ëÇÑ´Ù.
4687	HDMI_TX_InitDDC_Read(0xa0, segmentpointer, offset, 0x01, 0x00);
4688	OS_mDelay(3);
4689	DHL_SYS_ANXRead(0, HDMI_TX_DDC_FIFO_ACC_REG, &c);
4690	#endif
4691	if (valid_hdmi_tx_edid)
4692	{
4693	c = hdmi_tx_edid_buf[(segmentpointer << 7) + offset];
4694	}
4695	else
4696	{
4697	c = 0x00;
4698	}
4699
4700	return c;
4701	}
4702
4703	void HDMI_TX_Timer_Process ()
4704	{
4705	static unsigned char timer_slot = 0;
4706	unsigned char timer_done;
4707
4708	HDMI_TX_Timer_Slot1();
4709	HDMI_TX_Timer_Slot2();
4710	HDMI_TX_Timer_Slot3();
4711	HDMI_TX_Timer_Slot4();
4712
4713	return;
4714	// if (timer_done)
4715	{
4716	timer_done = 0;
4717	if (timer_slot == 4)
4718	timer_slot = 0;
4719	else
4720	timer_slot ++;
4721	if (timer_slot == 0)
4722	{
4723	//** if(SWITCH1 == 0)
4724	HDMI_TX_Timer_Slot1();
4725	}
4726	else if (timer_slot == 1)
4727	{
4728	//** if(SWITCH1 == 0)
4729	HDMI_TX_Timer_Slot2();
4730	}
4731	else if (timer_slot == 2)
4732	{
4733	//**if(SWITCH1 == 0)
4734	HDMI_TX_Timer_Slot3();
4735	}
4736	else if (timer_slot == 3)
4737	{
4738	HDMI_TX_Timer_Slot4();
4739	}
4740	}
4741	}
4742	/*
4743	void Write_data_to_EE()
4744	{
4745	BYTE i;
4746	for(i=0;i<18;i++)
4747	{
4748	i2c_write_EE_reg(i, hdmi_tx_video_timingtype_table.hdmi_tx_640x480p_60Hz[i]);
4749	OS_mDelay(5);
4750	i2c_write_EE_reg(i+18, hdmi_tx_video_timingtype_table.hdmi_tx_720x480p_60Hz[i]);
4751	OS_mDelay(5);
4752	i2c_write_EE_reg(i+18*2, hdmi_tx_video_timingtype_table.hdmi_tx_1280x720p_60Hz[i]);
4753	OS_mDelay(5);
4754	i2c_write_EE_reg(i+18*3, hdmi_tx_video_timingtype_table.hdmi_tx_1920x1080i_60Hz[i]);
4755	OS_mDelay(5);
4756	i2c_write_EE_reg(i+18*4, hdmi_tx_video_timingtype_table.hdmi_tx_720x480i_60Hz[i]);
4757	OS_mDelay(5);
4758	i2c_write_EE_reg(i+18*5, hdmi_tx_video_timingtype_table.hdmi_tx_720x576p_50Hz[i]);
4759	OS_mDelay(5);
4760	i2c_write_EE_reg(i+18*6, hdmi_tx_video_timingtype_table.hdmi_tx_1280x720p_50Hz[i]);
4761	OS_mDelay(5);
4762	i2c_write_EE_reg(i+18*7, hdmi_tx_video_timingtype_table.hdmi_tx_1920x1080i_50Hz[i]);
4763	OS_mDelay(5);
4764	i2c_write_EE_reg(i+18*8, hdmi_tx_video_timingtype_table.hdmi_tx_720x576i_50Hz[i]);
4765	OS_mDelay(5);
4766	}
4767	HDMI_TX_DebugPrintf("finish writing EE\n");
4768	}*/
4769
4770	void HDMI_TX_Config_Auto_Video_Format(void)
4771	{
4772	BYTE c;
4773
4774	fprintf(stderr, "\|%s, %d\| Set auto video format\n", __FUNCTION__, __LINE__);
4775
4776	// Set auto video format
4777	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
4778	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & ~HDMI_TX_VID_CAPCTRL1_FORMAT_SEL));
4779	}
4780
4781	void HDMI_TX_Config_Manual_Video_Format(WORD bist_select_number)
4782	{
4783	WORD bist_data;
4784	BYTE c, c1, c2;
4785
4786	fprintf(stderr, "\|%s, %d\| Set manual video format (%d)\n", __FUNCTION__, __LINE__, (int)bist_select_number);
4787
4788	bist_data = _861_Video_Timing[bist_select_number].h_total_length;
4789	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESL_REG, bist_data);
4790	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESH_REG, (bist_data>>8));
4791
4792	bist_data = _861_Video_Timing[bist_select_number].h_active_length;
4793	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXL_REG, bist_data);
4794	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXH_REG, (bist_data>>8));
4795
4796	bist_data = _861_Video_Timing[bist_select_number].v_total_length;
4797	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESL_REG, bist_data);
4798	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESH_REG, (bist_data>>8));
4799
4800	bist_data = _861_Video_Timing[bist_select_number].v_active_length;
4801	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEL_REG, bist_data);
4802	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEH_REG, (bist_data>>8));
4803
4804	bist_data = _861_Video_Timing[bist_select_number].h_front_porch;
4805	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHL_REG, bist_data);
4806	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHH_REG, (bist_data>>8));
4807
4808	bist_data = _861_Video_Timing[bist_select_number].h_sync_width;
4809	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, bist_data);
4810	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, (bist_data>>8));
4811
4812	bist_data = _861_Video_Timing[bist_select_number].h_back_porch;
4813	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHL_REG, bist_data);
4814	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHH_REG, (bist_data>>8));
4815
4816	bist_data = _861_Video_Timing[bist_select_number].v_front_porch;
4817	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINE2VSYNC_REG, bist_data);
4818
4819	bist_data = _861_Video_Timing[bist_select_number].v_sync_width;
4820	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_WID_REG, bist_data);
4821
4822	bist_data = _861_Video_Timing[bist_select_number].v_back_porch;
4823	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_TAIL2VIDLINE_REG, bist_data);
4824
4825	bist_data = _861_Video_Timing[bist_select_number].h_sync_polarity;
4826	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
4827	if(bist_data == 1)
4828	{
4829	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_HSYNC_POL));
4830	}
4831	else
4832	{
4833	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xdf));
4834	}
4835
4836	bist_data = _861_Video_Timing[bist_select_number].v_sync_polarity;
4837	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
4838	if(bist_data == 1)
4839	{
4840	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VSYNC_POL));
4841	}
4842	else
4843	{
4844	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xbf));
4845	}
4846
4847	bist_data = _861_Video_Timing[bist_select_number].is_interlaced;
4848	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
4849	if(bist_data == 1)
4850	{
4851	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VID_TYPE));
4852	}
4853	else
4854	{
4855	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xf7));
4856	}
4857
4858	// Set manual video format
4859	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
4860	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_FORMAT_SEL));
4861
4862	return;
4863
4864	//For deep color mode, only RGB and YCbCr444 can be output
4865	c2 = hdmi_tx_edid_result.RGB30bit + ((hdmi_tx_edid_result.RGB36bit)<<1) + ((hdmi_tx_edid_result.RGB48bit)<<2);
4866	switch (c2)
4867	{
4868	case 0: //24bit mode
4869	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
4870	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,(c & 0x9f));
4871	break;
4872	case 1: //30bit mode
4873	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
4874	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x20));
4875	break;
4876	case 2:
4877	case 3: //36bit mode
4878	case 4: //48bit mode, also set to 36bit
4879	case 5:
4880	case 6:
4881	case 7:
4882	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
4883	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x40));
4884	break;
4885	default:
4886	break;
4887
4888	}
4889
4890	c1 = hdmi_tx_edid_result.ycbcr444_supported;
4891	c1 = (c1<<1) + (BYTE) hdmi_tx_edid_result.ycbcr422_supported;
4892
4893	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, 0x00);
4894
4895	if(c2)//deep color mode
4896	{
4897	//select RGB mode
4898	HDMI_TX_DebugPrintf("into deep color mode CSC config\n");
4899	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4900	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
4901	}
4902	else// not deep color mode
4903	{
4904	HDMI_TX_DebugPrintf("into not deep color mode CSC config\n");
4905	switch (c1)
4906	{
4907	case 0: //select RGB mode
4908	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4909	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
4910	break;
4911	case 1: //select YCbCr4:2:2 mode
4912	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4913	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
4914	break;
4915	case 2: //select YCbCr4:4:4 mode
4916	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4917	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
4918	//do upsample(from YCbCr4:2:2 to YCbCr4:4:4)
4919	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
4920	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, (c \|0x04));
4921	break;
4922	case 3: //Both YCbCr4:2:2 and YCbCr4:4:4 modes supported, then select YCbCr4:2:2 mode
4923	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4924	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
4925	}
4926	}
4927
4928	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
4929	if((c & 0xe0) == 0x20)
4930	{
4931	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
4932	c = c & 0x60;
4933	if(c == 0x40)
4934	{
4935	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
4936	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd8));
4937	}
4938	else if(c == 0x20)
4939	{
4940	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
4941	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd4));
4942	}
4943	else if(c == 0x00)
4944	{
4945	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
4946	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd0));
4947	}
4948	}
4949	else
4950	{
4951	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
4952	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xc0));
4953	}
4954	}
4955
4956	void HDMI_TX_Config_Manual_Video_FormatEx(const struct Video_Timing *pVT)
4957	{
4958	WORD bist_data;
4959	BYTE c, c1, c2;
4960
4961	bist_data = pVT->h_total_length;
4962	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESL_REG, bist_data);
4963	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESH_REG, (bist_data>>8));
4964
4965	bist_data = pVT->h_active_length;
4966	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXL_REG, bist_data);
4967	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXH_REG, (bist_data>>8));
4968
4969	bist_data = pVT->v_total_length;
4970	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESL_REG, bist_data);
4971	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESH_REG, (bist_data>>8));
4972
4973	bist_data = pVT->v_active_length;
4974	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEL_REG, bist_data);
4975	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEH_REG, (bist_data>>8));
4976
4977	bist_data = pVT->h_front_porch;
4978	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHL_REG, bist_data);
4979	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHH_REG, (bist_data>>8));
4980
4981	bist_data = pVT->h_sync_width;
4982	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, bist_data);
4983	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, (bist_data>>8));
4984
4985	bist_data = pVT->h_back_porch;
4986	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHL_REG, bist_data);
4987	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHH_REG, (bist_data>>8));
4988
4989	bist_data = pVT->v_front_porch;
4990	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINE2VSYNC_REG, bist_data);
4991
4992	bist_data = pVT->v_sync_width;
4993	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_WID_REG, bist_data);
4994
4995	bist_data = pVT->v_back_porch;
4996	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_TAIL2VIDLINE_REG, bist_data);
4997
4998	bist_data = pVT->h_sync_polarity;
4999	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5000	if(bist_data == 1)
5001	{
5002	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_HSYNC_POL));
5003	}
5004	else
5005	{
5006	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xdf));
5007	}
5008
5009	bist_data = pVT->v_sync_polarity;
5010	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5011	if(bist_data == 1)
5012	{
5013	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VSYNC_POL));
5014	}
5015	else
5016	{
5017	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xbf));
5018	}
5019
5020	bist_data = pVT->is_interlaced;
5021	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5022	if(bist_data == 1)
5023	{
5024	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VID_TYPE));
5025	}
5026	else
5027	{
5028	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xf7));
5029	}
5030
5031	// Set manual video format
5032	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5033	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_FORMAT_SEL));
5034
5035	return;
5036
5037	//For deep color mode, only RGB and YCbCr444 can be output
5038	c2 = hdmi_tx_edid_result.RGB30bit + ((hdmi_tx_edid_result.RGB36bit)<<1) + ((hdmi_tx_edid_result.RGB48bit)<<2);
5039	switch (c2)
5040	{
5041	case 0: //24bit mode
5042	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5043	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,(c & 0x9f));
5044	break;
5045	case 1: //30bit mode
5046	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5047	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x20));
5048	break;
5049	case 2:
5050	case 3: //36bit mode
5051	case 4: //48bit mode, also set to 36bit
5052	case 5:
5053	case 6:
5054	case 7:
5055	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5056	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x40));
5057	break;
5058	default:
5059	break;
5060
5061	}
5062
5063	c1 = hdmi_tx_edid_result.ycbcr444_supported;
5064	c1 = (c1<<1) + (BYTE) hdmi_tx_edid_result.ycbcr422_supported;
5065
5066	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, 0x00);
5067
5068	if(c2)//deep color mode
5069	{
5070	//select RGB mode
5071	HDMI_TX_DebugPrintf("into deep color mode CSC config\n");
5072	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5073	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
5074	}
5075	else// not deep color mode
5076	{
5077	HDMI_TX_DebugPrintf("into not deep color mode CSC config\n");
5078	switch (c1)
5079	{
5080	case 0: //select RGB mode
5081	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5082	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
5083	break;
5084	case 1: //select YCbCr4:2:2 mode
5085	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5086	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5087	break;
5088	case 2: //select YCbCr4:4:4 mode
5089	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5090	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5091	//do upsample(from YCbCr4:2:2 to YCbCr4:4:4)
5092	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5093	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, (c \|0x04));
5094	break;
5095	case 3: //Both YCbCr4:2:2 and YCbCr4:4:4 modes supported, then select YCbCr4:2:2 mode
5096	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5097	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5098	}
5099	}
5100
5101	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5102	if((c & 0xe0) == 0x20)
5103	{
5104	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5105	c = c & 0x60;
5106	if(c == 0x40)
5107	{
5108	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5109	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd8));
5110	}
5111	else if(c == 0x20)
5112	{
5113	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5114	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd4));
5115	}
5116	else if(c == 0x00)
5117	{
5118	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5119	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd0));
5120	}
5121	}
5122	else
5123	{
5124	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5125	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xc0));
5126	}
5127	}
5128
5129	void HDMI_TX_Set_Video_Format(int i)
5130	{
5131	saved_hdmi_tx_video_timing_id = i;
5132	fprintf(stderr, "\|%s, %d\| Set video format = %d\n", __FUNCTION__, __LINE__, saved_hdmi_tx_video_timing_id);
5133	}
5134
5135	#if BIST_MODE_USED
5136
5137	void HDMI_TX_BIST()
5138	{
5139	BYTE c, c1,i;
5140	BIT bist_again;
5141	BYTE switch_value_sw,switch_value_pc;
5142	static BYTE pattern_value_backup;
5143	BYTE temp3,temp2,temp1,temp0,temp;
5144
5145	temp3 = BIST_MODE3;
5146	temp2 = BIST_MODE2;
5147	temp1 = BIST_MODE1;
5148	temp0 = BIST_MODE0;
5149	switch_value_sw = (temp3 << 3) + (temp2 << 2) + (temp1 << 1) + temp0;
5150
5151	switch_value_pc = bist_switch_value_pc;
5152	if((switch_value_sw_backup != switch_value_sw)
5153	\|\| (switch_value_pc_backup != switch_value_pc)
5154	\|\| (pattern_value_backup != g_BIST_Pattern))
5155	bist_again = 1;
5156	else
5157	bist_again = 0;
5158
5159	if(switch_value_sw_backup != switch_value_sw)
5160	switch_value = switch_value_sw;
5161	else if(switch_value_pc_backup != switch_value_pc)
5162	switch_value = switch_value_pc;
5163
5164	switch_value_sw_backup = switch_value_sw;
5165	switch_value_pc_backup = switch_value_pc;
5166	pattern_value_backup = g_BIST_Pattern;
5167
5168	if((bist_again == 1) && (HDMI_TX_system_state != HDMI_TX_INITIAL)
5169	&& (HDMI_TX_system_state != HDMI_TX_WAIT_HOTPLUG)
5170	&& (HDMI_TX_system_state != HDMI_TX_READ_PARSE_EDID))
5171	{
5172	HDMI_TX_Reset_BIST_Setting();
5173	HDMI_TX_Reset_AVI();
5174	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
5175	}
5176
5177	if(HDMI_TX_system_state == HDMI_TX_INITIAL)
5178	return;
5179
5180	if(HDMI_TX_system_state == HDMI_TX_WAIT_HOTPLUG)
5181	return;
5182
5183	if(HDMI_TX_system_state == HDMI_TX_READ_PARSE_EDID)
5184	{
5185	DHL_SYS_ANXRead(0, HDMI_TX_HDCP_CTRL0_REG, &c);
5186	DHL_SYS_ANXWrite(0, HDMI_TX_HDCP_CTRL0_REG, (c &(~HDMI_TX_HDCP_CTRL0_HW_AUTHEN)));
5187	hdmi_tx_hdcp_auth_en = 0;
5188	HDMI_TX_RST_DDCChannel();
5189	HDMI_TX_Parse_EDID();
5190	hdmi_tx_parse_edid_done = 1;
5191	HDMI_TX_EDID_Parsing_Result();
5192	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
5193	}
5194	/*
5195	if(HDMI_TX_system_state == HDMI_TX_WAIT_RX_SENSE)
5196	{
5197	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
5198	if(c & HDMI_TX_SYS_STATE_RSV_DET)
5199	{
5200	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_VIDEO);
5201	}
5202	else
5203	{
5204	;
5205	}
5206	}
5207	*/
5208	if(HDMI_TX_system_state == HDMI_TX_CONFIG_VIDEO)
5209	{
5210	HDMI_TX_Clean_HDCP();
5211	if(HDMI_TX_CLK_SOURCE == 1)
5212	{ //use on board clock generator as clock source
5213	HDMI_TX_Config_Clock_Generator_Frequency(switch_value);
5214	OS_mDelay(5);
5215	}
5216	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
5217	if(!(c & 0x02))
5218	{
5219	HDMI_TX_DebugPrintf("No clock detected !\n");
5220	return;
5221	}
5222	DHL_SYS_ANXRead(0, HDMI_TX_SYS_STATE_REG, &c);
5223	if(!(c & 0x40))
5224	{
5225	HDMI_TX_DebugPrintf("PLL not lock !\n");
5226	return;
5227	}
5228	if(HDMI_TX_CLK_SOURCE == 1)
5229	HDMI_TX_Config_Bist_Video(switch_value);
5230	else
5231	HDMI_TX_Config_Bist_Video(1);
5232	//enable video input
5233	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5234	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, c \| HDMI_TX_VID_CTRL_IN_EN);
5235	DHL_SYS_ANXRead(0, HDMI_TX_VID_STATUS_REG, &c);
5236	if((switch_value == 4) \|\| (switch_value == 10))
5237	{
5238	if(misc_reset_needed)
5239	{
5240	misc_reset_needed = 0;
5241	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5242	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, c \| 0x01);
5243	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, 0x02);
5244	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, 0x00);
5245	}
5246	}
5247	else
5248	{
5249	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5250	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, c & 0xfc);
5251	}
5252	if(!(c & HDMI_TX_VID_STATUS_VID_STABLE))
5253	{
5254	return;
5255	}
5256
5257	if(hdmi_tx_edid_result.is_HDMI)
5258	{
5259	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL1_REG, &c);
5260	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL1_REG, c \| 0x02);
5261	}
5262	//reset TMDS link
5263	DHL_SYS_ANXRead(0, HDMI_TX_SRST_REG, &c);
5264	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, (c \| HDMI_TX_TMDS_CHNL_ALIGN));
5265	DHL_SYS_ANXWrite(0, HDMI_TX_SRST_REG, (c & (~HDMI_TX_TMDS_CHNL_ALIGN)));
5266
5267	//Enable TMDS output
5268	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, &c);
5269	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, (c \| HDMI_TX_TMDS_CLKCH_MUTE));
5270
5271	HDMI_TX_Set_System_State(HDMI_TX_HDCP_AUTHENTICATION);
5272	}
5273
5274	if(HDMI_TX_system_state == HDMI_TX_CONFIG_AUDIO)
5275	{
5276	// ACR_N
5277	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N1_SW_REG, 0x00);
5278	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N2_SW_REG, 0x18);
5279	DHL_SYS_ANXWrite(1, HDMI_TX_ACR_N3_SW_REG, 0x00);
5280
5281	//Enable control of ACR
5282	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
5283	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, (c \| HDMI_TX_INFO_PKTCTRL1_ACR_EN));
5284
5285	//audio enable:
5286	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
5287	c \|= HDMI_TX_HDMI_AUDCTRL1_IN_EN;
5288	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, c);
5289
5290	if ( hdmi_tx_audio_input == 0x01 /* I2S*/) {
5291	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
5292	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, (c \| 0x10));
5293	} else {
5294	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL0_REG, &c);
5295	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL0_REG, (c & 0xef));
5296	}
5297	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDCTRL1_REG, &c);
5298	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDCTRL1_REG, (c \| 0x01));
5299	DHL_SYS_ANXRead(0, HDMI_TX_HDMI_AUDBIST_CTRL_REG, &c);
5300	DHL_SYS_ANXWrite(0, HDMI_TX_HDMI_AUDBIST_CTRL_REG, (c \| 0xcf));
5301
5302	HDMI_TX_Set_System_State(HDMI_TX_CONFIG_PACKETS);
5303	}
5304
5305	if(HDMI_TX_system_state == HDMI_TX_CONFIG_PACKETS)
5306	{
5307	s_hdmi_tx_packet_config.packets_need_config = 0x00;
5308	//config Y0, Y1 of AVI
5309	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5310	if((c & 0xe0) == 0x20)//RGB
5311	{
5312	hdmi_tx_avi_data[4] = hdmi_tx_avi_data[4] & 0x9f;
5313	}
5314	else
5315	{
5316	c1 = hdmi_tx_edid_result.ycbcr444_supported;
5317	temp = hdmi_tx_edid_result.ycbcr422_supported;
5318	c1 = (c1<<1) + temp;
5319
5320	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
5321
5322	c &= ~HDMI_TX_INFO_PKTCTRL1_AVI_RPT;
5323	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, c);
5324	switch (c1)
5325	{
5326	case 0: //config to RGB mode
5327	hdmi_tx_avi_data[4] = hdmi_tx_avi_data[4] & 0x9f;
5328	break;
5329	case 1: //config to YCbCr4:2:2 mode
5330	hdmi_tx_avi_data[4] = (hdmi_tx_avi_data[4] & 0x9f) \| 0x20;
5331	break;
5332	case 2: //config to YCbCr4:4:4 mode
5333	hdmi_tx_avi_data[4] = (hdmi_tx_avi_data[4] & 0x9f) \| 0x40;
5334	break;
5335	case 3: //config to YCbCr4:2:2 mode
5336	hdmi_tx_avi_data[4] = (hdmi_tx_avi_data[4] & 0x9f) \| 0x20;
5337	}
5338	}
5339	//config AVI data byte4
5340	switch (switch_value)
5341	{
5342	case 0: //640x480p@60
5343	hdmi_tx_avi_data[7] = 0x01;
5344	hdmi_tx_avi_data[5] = 0x58; //ITU601, Pixcure Aspect Ration = 4:3, ACtive Format Aspect Ration same as picture aspect ratio.
5345	break;
5346	case 1: //1280x720p@60
5347	hdmi_tx_avi_data[7] = 0x04;
5348	hdmi_tx_avi_data[5] = 0xa8; //ITU709, Pixcure Aspect Ration = 16:9, ACtive Format Aspect Ration same as picture aspect ratio.
5349	break;
5350	case 2: //1920x10800i@60
5351	hdmi_tx_avi_data[7] = 0x05;
5352	hdmi_tx_avi_data[5] = 0xa8; //ITU709, Pixcure Aspect Ration = 16:9, ACtive Format Aspect Ration same as picture aspect ratio.
5353	break;
5354	case 3: //720x480p@60
5355	hdmi_tx_avi_data[7] = 0x03;
5356	hdmi_tx_avi_data[5] = 0x58;
5357	break;
5358	case 4: //720x480i@60
5359	hdmi_tx_avi_data[7] = 0x06;
5360	hdmi_tx_avi_data[5] = 0x58;
5361	break;
5362	case 5: //1080p@60
5363	hdmi_tx_avi_data[7] = 0x10;
5364	hdmi_tx_avi_data[5] = 0xa8;
5365	break;
5366	case 6: //1080p@50
5367	hdmi_tx_avi_data[7] = 0x1f;
5368	hdmi_tx_avi_data[5] = 0xa8;
5369	break;
5370	case 7: //720p@50
5371	hdmi_tx_avi_data[7] = 0x13;
5372	hdmi_tx_avi_data[5] = 0xa8;
5373	break;
5374	case 8: //1080i@50
5375	hdmi_tx_avi_data[7] = 0x14;
5376	hdmi_tx_avi_data[5] = 0xa8;
5377	break;
5378	case 9: //576p@50
5379	hdmi_tx_avi_data[7] = 0x11;
5380	hdmi_tx_avi_data[5] = 0x58;
5381	break;
5382	case 10: //576i@50
5383	hdmi_tx_avi_data[7] = 0x15;
5384	hdmi_tx_avi_data[5] = 0x58;
5385	break;
5386	default:
5387	break;
5388	}
5389
5390	//Caculate Checksum
5391	hdmi_tx_avi_data[3] = 0;
5392	c =0;
5393	for(i=0; i<17;i++)
5394	{
5395	c = c + hdmi_tx_avi_data[i];
5396	}
5397	c = (~c) +1;
5398	hdmi_tx_avi_data[3] = c;
5399
5400	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
5401	if(c & HDMI_TX_INFO_PKTCTRL1_AVI_EN)
5402	{
5403	return ;
5404	}
5405
5406	//Config AVI infoframe
5407	for(i=0; i<17; i++ )
5408	{
5409	DHL_SYS_ANXWrite(1, i, hdmi_tx_avi_data[i]);
5410	}
5411
5412	//Enable send AVI InfoFrame
5413	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL1_REG, &c);
5414	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL1_REG, (c \| 0x30));
5415
5416	//Config Audio Infoframe
5417	HDMI_TX_Load_Infoframe( HDMI_TX_audio_infoframe,
5418	&(s_hdmi_tx_packet_config.audio_info));
5419
5420	DHL_SYS_ANXRead(1, HDMI_TX_INFO_PKTCTRL2_REG, &c);
5421	c \|= 0x03;
5422	DHL_SYS_ANXWrite(1, HDMI_TX_INFO_PKTCTRL2_REG, c);
5423
5424	//Config Channel Status
5425	c = s_hdmi_tx_audio_config.i2s_config.Channel_status1;
5426	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS1_REG, c);
5427	c = s_hdmi_tx_audio_config.i2s_config.Channel_status2;
5428	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS2_REG, c);
5429	c = s_hdmi_tx_audio_config.i2s_config.Channel_status3;
5430	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS3_REG, c);
5431	c = s_hdmi_tx_audio_config.i2s_config.Channel_status4;
5432	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS4_REG, c);
5433	c = s_hdmi_tx_audio_config.i2s_config.Channel_status5;
5434	DHL_SYS_ANXWrite(0, HDMI_TX_I2SCH_STATUS5_REG, c);
5435
5436	HDMI_TX_Clear_AVMute();
5437	HDMI_TX_Set_System_State(HDMI_TX_PLAY_BACK);
5438	HDMI_TX_Show_Video_Parameter();
5439	}
5440
5441	if(HDMI_TX_system_state == HDMI_TX_HDCP_AUTHENTICATION)
5442	{
5443	#if (HDMI_TX_USE_NATIVE_CODE) && USE_HDMI_RX
5444	hdmi_rx_chip_id = 0xff;
5445	#endif
5446	HDMI_TX_HDCP_Process();
5447	}
5448
5449	if(HDMI_TX_system_state == HDMI_TX_PLAY_BACK)
5450	{
5451	HDMI_TX_PLAYBACK_Process();
5452	}
5453
5454	}
5455	#endif
5456
5457	void HDMI_TX_Config_Clock_Generator_Frequency(WORD bist_select_number)
5458	{
5459	#if (0)
5460	switch (bist_select_number)
5461	{
5462	case 0: //Freq = 25.125MHz, M=201, N=8
5463	MC12429_send_Tbits(0);//Send Test bits, 0 : shift registers out
5464	MC12429_send_Nbits(3);//Send N bits
5465	MC12429_send_Mbits(201);//Send M bits
5466	break;
5467	case 1: //Freq = 74.25MHz, M=297, N=4
5468	case 2:
5469	case 7:
5470	case 8:
5471	MC12429_send_Tbits(0);
5472	MC12429_send_Nbits(2);
5473	MC12429_send_Mbits(297);
5474	break;
5475	case 5: //Freq = 148.5MHz, M=297, N=2
5476	case 6:
5477	MC12429_send_Tbits(0);
5478	MC12429_send_Nbits(1);
5479	MC12429_send_Mbits(297);
5480	break;
5481	case 3://27M, M = 27, N=1
5482	case 4:
5483	case 9:
5484	case 10:
5485	MC12429_send_Tbits(0);
5486	MC12429_send_Nbits(3);
5487	MC12429_send_Mbits(216);
5488	break;
5489	/* case 11: //37.5M, M=75, N=2
5490	MC12429_send_Tbits(0);
5491	MC12429_send_Nbits(2);
5492	MC12429_send_Mbits(75);
5493	break;
5494	case 12: //111.375M, M=223, N=2. so exact freq=111.5MHz
5495	case 13:
5496	MC12429_send_Tbits(0);
5497	MC12429_send_Nbits(2);
5498	MC12429_send_Mbits(297);
5499	DHL_SYS_ANXWrite(0, 0x0a, 0x40);
5500	break;
5501	case 14: //222.75M, M=223, N=1. so exact freq=223MHz
5502	case 15:
5503	MC12429_send_Tbits(0);
5504	MC12429_send_Nbits(1);
5505	MC12429_send_Mbits(223);
5506	break;
5507	case 15: //40.5M, M=81, N=2
5508	MC12429_send_Tbits(0);
5509	MC12429_send_Nbits(2);
5510	MC12429_send_Mbits(81);
5511	break;*/
5512	default:
5513	break;
5514	}
5515	MC12429_load_data_EN();//Load data into MC12429
5516	#endif
5517	}
5518
5519	void HDMI_TX_Reset_BIST_Setting(void)
5520	{
5521	BYTE c;
5522	//Reset video mode register to disable up sampling.
5523	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5524	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, (c & 0xfb));
5525	}
5526
5527	void HDMI_TX_Config_Bist_Video(WORD bist_select_number)
5528	{
5529	WORD bist_data;
5530	BYTE c, c1, c2;
5531
5532	bist_data = _861_Video_Timing[bist_select_number].h_total_length;
5533	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESL_REG, bist_data);
5534	DHL_SYS_ANXWrite(0, HDMI_TX_H_RESH_REG, (bist_data>>8));
5535
5536	bist_data = _861_Video_Timing[bist_select_number].h_active_length;
5537	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXL_REG, bist_data);
5538	DHL_SYS_ANXWrite(0, HDMI_TX_VID_PIXH_REG, (bist_data>>8));
5539
5540	bist_data = _861_Video_Timing[bist_select_number].v_total_length;
5541	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESL_REG, bist_data);
5542	DHL_SYS_ANXWrite(0, HDMI_TX_V_RESH_REG, (bist_data>>8));
5543
5544	bist_data = _861_Video_Timing[bist_select_number].v_active_length;
5545	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEL_REG, bist_data);
5546	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINEH_REG, (bist_data>>8));
5547
5548	bist_data = _861_Video_Timing[bist_select_number].h_front_porch;
5549	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHL_REG, bist_data);
5550	DHL_SYS_ANXWrite(0, HDMI_TX_H_FRONTPORCHH_REG, (bist_data>>8));
5551
5552	bist_data = _861_Video_Timing[bist_select_number].h_sync_width;
5553	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHL_REG, bist_data);
5554	DHL_SYS_ANXWrite(0, HDMI_TX_HSYNC_ACT_WIDTHH_REG, (bist_data>>8));
5555
5556	bist_data = _861_Video_Timing[bist_select_number].h_back_porch;
5557	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHL_REG, bist_data);
5558	DHL_SYS_ANXWrite(0, HDMI_TX_H_BACKPORCHH_REG, (bist_data>>8));
5559
5560	bist_data = _861_Video_Timing[bist_select_number].v_front_porch;
5561	DHL_SYS_ANXWrite(0, HDMI_TX_ACT_LINE2VSYNC_REG, bist_data);
5562
5563	bist_data = _861_Video_Timing[bist_select_number].v_sync_width;
5564	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_WID_REG, bist_data);
5565
5566	bist_data = _861_Video_Timing[bist_select_number].v_back_porch;
5567	DHL_SYS_ANXWrite(0, HDMI_TX_VSYNC_TAIL2VIDLINE_REG, bist_data);
5568
5569	bist_data = _861_Video_Timing[bist_select_number].h_sync_polarity;
5570	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5571	if(bist_data == 1)
5572	{
5573	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_HSYNC_POL));
5574	}
5575	else
5576	{
5577	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xdf));
5578	}
5579
5580	bist_data = _861_Video_Timing[bist_select_number].v_sync_polarity;
5581	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5582	if(bist_data == 1)
5583	{
5584	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VSYNC_POL));
5585	}
5586	else
5587	{
5588	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xbf));
5589	}
5590
5591	bist_data = _861_Video_Timing[bist_select_number].is_interlaced;
5592	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL1_REG, &c);
5593	if(bist_data == 1)
5594	{
5595	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c \| HDMI_TX_VID_CAPCTRL1_VID_TYPE));
5596	}
5597	else
5598	{
5599	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL1_REG, (c & 0xf7));
5600	}
5601
5602	//For deep color mode, only RGB and YCbCr444 can be output
5603	c2 = hdmi_tx_edid_result.RGB30bit + ((hdmi_tx_edid_result.RGB36bit)<<1) + ((hdmi_tx_edid_result.RGB48bit)<<2);
5604	switch (c2)
5605	{
5606	case 0: //24bit mode
5607	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5608	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,(c & 0x9f));
5609	break;
5610	case 1: //30bit mode
5611	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5612	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x20));
5613	break;
5614	case 2:
5615	case 3: //36bit mode
5616	case 4: //48bit mode, also set to 36bit
5617	case 5:
5618	case 6:
5619	case 7:
5620	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5621	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,((c & 0x9f) \| 0x40));
5622	break;
5623	default:
5624	break;
5625
5626	}
5627
5628	c1 = hdmi_tx_edid_result.ycbcr444_supported;
5629	c1 = (c1<<1) + (BYTE) hdmi_tx_edid_result.ycbcr422_supported;
5630
5631	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, 0x00);
5632
5633	if(c2)//deep color mode
5634	{
5635	//select RGB mode
5636	HDMI_TX_DebugPrintf("into deep color mode CSC config\n");
5637	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5638	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
5639	}
5640	else// not deep color mode
5641	{
5642	HDMI_TX_DebugPrintf("into not deep color mode CSC config\n");
5643	switch (c1)
5644	{
5645	case 0: //select RGB mode
5646	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5647	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0x20));
5648	break;
5649	case 1: //select YCbCr4:2:2 mode
5650	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5651	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5652	break;
5653	case 2: //select YCbCr4:4:4 mode
5654	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5655	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5656	//do upsample(from YCbCr4:2:2 to YCbCr4:4:4)
5657	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5658	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, (c \|0x04));
5659	break;
5660	case 3: //Both YCbCr4:2:2 and YCbCr4:4:4 modes supported, then select YCbCr4:2:2 mode
5661	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5662	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG,((c & 0x1f) \| 0xa0));
5663	}
5664	}
5665
5666	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
5667	if((c & 0xe0) == 0x20)
5668	{
5669	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5670	c = c & 0x60;
5671	if(c == 0x40)
5672	{
5673	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5674	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd8));
5675	}
5676	else if(c == 0x20)
5677	{
5678	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5679	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd4));
5680	}
5681	else if(c == 0x00)
5682	{
5683	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5684	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xd0));
5685	}
5686	}
5687	else
5688	{
5689	DHL_SYS_ANXRead(1, HDMI_TX_GNRL_CTRL_PKT_REG, &c1);
5690	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c1 & 0x03) \| 0xc0));
5691	}
5692
5693	bist_data = g_BIST_Pattern;//_861_Video_Timing[bist_select_number].video_mode;
5694	DHL_SYS_ANXRead(0, HDMI_TX_VID_STATUS_REG, &c);
5695	DHL_SYS_ANXWrite(0, HDMI_TX_VID_STATUS_REG, ((c & 0x3f) \| (bist_data<<6)));
5696
5697	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
5698	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, (c \| HDMI_TX_VID_CAPCTRL0_VIDBIST_EN));
5699
5700	}
5701
5702
5703	void HDMI_TX_Reset_AVI(void)
5704	{
5705	TT();
5706	hdmi_tx_avi_data[0] = 0x82; //type, HDMI defined
5707	hdmi_tx_avi_data[1] = 0x02; //Version
5708	hdmi_tx_avi_data[2] = 0x0d; //AVI data byte length is 13
5709	hdmi_tx_avi_data[3] = 0x00; //checksum
5710	hdmi_tx_avi_data[4] = 0x00; //data byte 1
5711	hdmi_tx_avi_data[5] = 0x08; //data byte 2
5712	hdmi_tx_avi_data[6] = 0x00; //data byte 3
5713	hdmi_tx_avi_data[7] = 0x01; //data byte 4
5714	hdmi_tx_avi_data[8] = 0x00; //data byte 5
5715	hdmi_tx_avi_data[9] = 0x00; //data byte 6
5716	hdmi_tx_avi_data[10] = 0x00; //data byte 7
5717	hdmi_tx_avi_data[11] = 0x00; //data byte 8
5718	hdmi_tx_avi_data[12] = 0x00; //data byte 9
5719	hdmi_tx_avi_data[13] = 0x00; //data byte 10
5720	hdmi_tx_avi_data[14] = 0x00; //data byte 11
5721	hdmi_tx_avi_data[15] = 0x00; //data byte 12
5722	hdmi_tx_avi_data[16] = 0x00; //data byte 13
5723	hdmi_tx_avi_data[17] = 0x00; //for firmware use
5724	hdmi_tx_avi_data[18] = 0x00; //for firmware use
5725	}
5726
5727	void HDMI_TX_PLLFilter_Reset(void)
5728	{
5729	BYTE c;
5730	//power down and then on PLL Filter
5731	TT();
5732	DHL_SYS_ANXRead(0, HDMI_TX_SYS_PD_REG, &c);
5733	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_PD_REG, c & ~HDMI_TX_SYS_PD_PLLF);
5734	OS_mDelay(100);
5735	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_PD_REG, c \| HDMI_TX_SYS_PD_PLLF);
5736	}
5737
5738	void HDMI_TX_MuteTMDS_CLK(void)
5739	{
5740	BYTE c;
5741	TT();
5742	DHL_SYS_ANXRead(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, &c);
5743	DHL_SYS_ANXWrite(0, HDMI_TX_TMDS_CLKCH_CONFIG_REG, c & (~HDMI_TX_TMDS_CLKCH_MUTE));
5744	}
5745
5746	void HDMI_TX_HW_Vid_Testing(void)
5747	{
5748	#if (0)
5749	BYTE c;
5750	if((P2_1 == 1) && (P2_2 == 0) && (P2_3 == 0))//ycmux
5751	{
5752	HDMI_RX_VID_Output_Fmt(YCbCr422_YCMUX);
5753	HDMI_RX_WriteI2C_RX0(0x86,0);//select yc-mux output bonding mode
5754	hdmi_tx_video_format_config = 4;
5755	hdmi_tx_input_csc = 0x01;
5756	HDMI_TX_DebugPrintf("ycmux\n");
5757	}
5758	else if((P2_1 == 0) && (P2_2 == 1) && (P2_3 == 0))//656
5759	{
5760	HDMI_RX_VID_Output_Fmt(YCbCr422_656);
5761	hdmi_tx_video_format_config = 0x02;
5762	hdmi_tx_input_csc = 0x01;
5763	HDMI_TX_DebugPrintf("656\n");
5764	}
5765	else if((P2_1 == 1) && (P2_2 == 1) && (P2_3 == 0))//ycmux + 656
5766	{
5767	HDMI_RX_VID_Output_Fmt(YCbCr422_656_YCMUX);
5768	HDMI_RX_WriteI2C_RX0(0x86,0);//select yc-mux output bonding mode
5769	hdmi_tx_video_format_config = 6;
5770	hdmi_tx_input_csc = 0x01;
5771	HDMI_TX_DebugPrintf("ycmux + 656\n");
5772
5773	}
5774	else if((P2_1 == 0) && (P2_2 == 0) && (P2_3 == 1))//no de
5775	{
5776	HDMI_RX_VID_Output_Fmt(YCbCr444);
5777	hdmi_tx_video_format_config = 0x09;
5778	hdmi_tx_input_csc = 0x02;
5779	HDMI_TX_DebugPrintf("no de\n");
5780	}
5781	else if((P2_1 == 1) && (P2_2 == 1) && (P2_3 == 1))//DDR
5782	{
5783	HDMI_RX_VID_Output_Fmt(RGB444);
5784	HDMI_RX_ReadI2C_RX0(HDMI_RX_SYS_CTRL1_REG, &c);
5785	HDMI_RX_WriteI2C_RX0(HDMI_RX_SYS_CTRL1_REG, c & 0xfb);
5786	HDMI_RX_WriteI2C_RX0(HDMI_RX_VID_OUTPUT_CTRL1_REG, 0x00);
5787	HDMI_RX_WriteI2C_RX0(HDMI_RX_VID_OUTPUT_CTRL2_REG, 0x00);
5788	HDMI_RX_WriteI2C_RX0(HDMI_RX_VID_DDR_OUTPUT_CTRL_REG, 0x00);
5789
5790	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG,0x10);
5791	hdmi_tx_video_format_config = 0x07;
5792	hdmi_tx_input_csc = 0x00;
5793	HDMI_TX_DebugPrintf("DDR\n");
5794	}
5795	else
5796
5797	{
5798	#if (HDMI_TX_USE_NATIVE_CODE)
5799	HDMI_RX_VID_Output_Fmt(RGB444);
5800	#endif
5801	hdmi_tx_video_format_config = 0x00;
5802
5803	// Junku for debugging purpose.
5804	//hdmi_tx_video_format_config = hdmi_tx_RGB_YCrCb444_SepSync_No_DE;
5805	hdmi_tx_input_csc = 0x00;
5806	HDMI_TX_DebugPrintf("separate sync\n");
5807	}
5808	#endif
5809	}
5810
5811	void HDMI_TX_CSCandColorDepth_Setting(void)
5812	{
5813	BIT cspace_y2r, y2r_sel, up_sample,range_y2r, cspace_r2y, down_sample, range_r2y;
5814	BYTE c;
5815
5816	TT();
5817	cspace_y2r = 0;
5818	y2r_sel = 0;
5819	up_sample = 0;
5820	range_y2r = 0;
5821	cspace_r2y = 0;
5822	down_sample = 0;
5823	range_r2y = 0;
5824	//clean CSC
5825	hdmi_tx_RGBorYCbCr = hdmi_tx_input_csc;
5826	DHL_SYS_ANXWrite(0, HDMI_TX_VIDEO_MODE_REG, 0x00);
5827	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, 0x00);
5828	fprintf(stderr, "\|%s:%d\| HDMI_TX_VID_MODE_REG = 0x00\n", __FUNCTION__, __LINE__);
5829
5830	switch(hdmi_tx_video_timing_id)
5831	{
5832	case hdmi_tx_V1280x720p_50Hz:
5833	case hdmi_tx_V1280x720p_60Hz:
5834	case hdmi_tx_V1920x1080i_60Hz:
5835	case hdmi_tx_V1920x1080i_50Hz:
5836	case hdmi_tx_V1920x1080p_60Hz:
5837	case hdmi_tx_V1920x1080p_50Hz:
5838	y2r_sel = HDMI_TX_CSC_BT709;
5839	break;
5840	default:
5841	y2r_sel = HDMI_TX_CSC_BT601;
5842	break;
5843	}
5844	if((hdmi_tx_edid_result.RGB30bit == 0) && (hdmi_tx_edid_result.RGB36bit == 0)
5845	&& (hdmi_tx_edid_result.RGB48bit == 0))//not deep color mode
5846	{
5847	if(hdmi_tx_RGBorYCbCr == HDMI_TX_RGB)
5848	{
5849	if(hdmi_tx_edid_result.ycbcr422_supported && hdmi_tx_edid_result.ycbcr444_supported)
5850	{
5851	cspace_r2y = 1;
5852	down_sample = 1;
5853	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr422;
5854
5855	}
5856	else if(hdmi_tx_edid_result.ycbcr444_supported && (!hdmi_tx_edid_result.ycbcr422_supported))
5857	{
5858	cspace_r2y = 1;
5859	down_sample = 0;
5860	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr444;
5861	}
5862	else if((!hdmi_tx_edid_result.ycbcr444_supported) && (!hdmi_tx_edid_result.ycbcr422_supported))
5863	{
5864	cspace_r2y = 0;
5865	down_sample = 0;
5866	}
5867
5868	}
5869	else if(hdmi_tx_RGBorYCbCr == HDMI_TX_YCbCr422)
5870	{
5871	if(hdmi_tx_edid_result.ycbcr422_supported && hdmi_tx_edid_result.ycbcr444_supported)
5872	{
5873	;
5874	}
5875	else if(hdmi_tx_edid_result.ycbcr444_supported && (!hdmi_tx_edid_result.ycbcr422_supported))
5876	{
5877	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr444;
5878	up_sample = 1;
5879	}
5880	else if((!hdmi_tx_edid_result.ycbcr444_supported) && (!hdmi_tx_edid_result.ycbcr422_supported))
5881	{
5882	cspace_y2r = 1;
5883	up_sample = 1;
5884	hdmi_tx_RGBorYCbCr = HDMI_TX_RGB;
5885	}
5886	}
5887	else
5888	{
5889	if(hdmi_tx_edid_result.ycbcr422_supported && (!hdmi_tx_edid_result.ycbcr444_supported))
5890	{
5891	down_sample = 1;
5892	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr422;
5893	}
5894	else if(hdmi_tx_edid_result.ycbcr444_supported && (!hdmi_tx_edid_result.ycbcr422_supported))
5895	{
5896	;
5897	}
5898	else if((!hdmi_tx_edid_result.ycbcr444_supported) && (!hdmi_tx_edid_result.ycbcr422_supported))
5899	{
5900	cspace_y2r = 1;
5901	hdmi_tx_RGBorYCbCr = HDMI_TX_RGB;
5902	}
5903	}
5904	}
5905	else if(hdmi_tx_edid_result.DC_Y444)//deep color mode
5906	{
5907	if(hdmi_tx_RGBorYCbCr == HDMI_TX_RGB)
5908	{
5909	cspace_r2y = 1;
5910	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr444;
5911	}
5912	else if(hdmi_tx_RGBorYCbCr == HDMI_TX_YCbCr444)
5913	{
5914	;
5915	}
5916	else
5917	{
5918	up_sample = 1;
5919	hdmi_tx_RGBorYCbCr = HDMI_TX_YCbCr444;
5920	}
5921
5922	if((hdmi_tx_edid_result.RGB48bit == 1) \|\| (hdmi_tx_edid_result.RGB36bit == 1))
5923	{
5924	//set 36 bit mode
5925	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5926	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, ((c & 0x9f) \| 0x40));
5927	//set the GCP packet for 36 bits
5928	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
5929	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0x03) \| 0xd8));
5930	HDMI_TX_DebugPrintf("GCP packet value is %.2x\n", (WORD)((c & 0x03) \| 0xd8));
5931	}
5932	else
5933	{
5934	//set 30 bit mode
5935	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5936	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, ((c & 0x9f) \| 0x20));
5937	//set the GCP packet for 30 bits
5938	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
5939	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0x03) \| 0xd4));
5940	}
5941	}
5942	else//deep color mode
5943	{
5944	if(hdmi_tx_RGBorYCbCr == HDMI_TX_RGB)
5945	{
5946	;
5947	}
5948	else if(hdmi_tx_RGBorYCbCr == HDMI_TX_YCbCr444)
5949	{
5950	cspace_y2r = 1;
5951	hdmi_tx_RGBorYCbCr = HDMI_TX_RGB;
5952	}
5953	else
5954	{
5955	up_sample = 1;
5956	cspace_y2r = 1;
5957	hdmi_tx_RGBorYCbCr = HDMI_TX_RGB;
5958	}
5959	if((hdmi_tx_edid_result.RGB48bit == 1) \|\| (hdmi_tx_edid_result.RGB36bit == 1))
5960	{
5961	//set 36 bit mode
5962	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5963	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, ((c & 0x9f) \| 0x40));
5964	//set the GCP packet for 36 bits
5965	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
5966	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0x03) \| 0xd8));
5967	}
5968	else
5969	{
5970	//set 30 bit mode
5971	DHL_SYS_ANXRead(0, HDMI_TX_SYS_CTRL4_REG, &c);
5972	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL4_REG, ((c & 0x9f) \| 0x20));
5973	//set the GCP packet for 30 bits
5974	DHL_SYS_ANXRead(1,HDMI_TX_GNRL_CTRL_PKT_REG, &c);
5975	DHL_SYS_ANXWrite(1, HDMI_TX_GNRL_CTRL_PKT_REG, ((c & 0x03) \| 0xd4));
5976	}
5977	}
5978
5979	if(cspace_y2r)
5980	{
5981	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5982	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c \| HDMI_TX_VID_MODE_CSPACE_Y2R);
5983	if(y2r_sel)
5984	{
5985	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5986	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c \| HDMI_TX_VID_MODE_CSC_MODE_SEL);
5987	}
5988	else
5989	{
5990	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5991	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c & (~HDMI_TX_VID_MODE_CSC_MODE_SEL));
5992	}
5993	}
5994
5995	if(up_sample)
5996	{
5997	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
5998	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c \| HDMI_TX_VID_MODE_UPSAMPLE);
5999	}
6000
6001	if(range_y2r)
6002	{
6003	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
6004	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, c \| HDMI_TX_VID_MODE_RANGE_Y2R);
6005	}
6006
6007	if(cspace_r2y)
6008	{
6009	//DHL_SYS_ANXRead(0, HDMI_TX_VIDEO_MODE_REG, &c);
6010	//DHL_SYS_ANXWrite(0, HDMI_TX_VIDEO_MODE_REG, (c&0xfe) \| HDMI_TX_VIDEO_MODE_CSPACE_R2Y); for YCbCr input
6011	}
6012
6013	if(down_sample)
6014	{
6015	DHL_SYS_ANXRead(0, HDMI_TX_VIDEO_MODE_REG, &c);
6016	DHL_SYS_ANXWrite(0, HDMI_TX_VIDEO_MODE_REG, (c&0xfb) \| HDMI_TX_VIDEO_MODE_DOWN_SAMPLE);
6017	}
6018	}
6019
6020	void HDMI_TX_RepeatTimes_Setting(void)
6021	{
6022	BYTE c;
6023	TT();
6024	if(!hdmi_tx_pix_rpt_set_by_sys)
6025	{
6026	if((hdmi_tx_video_timing_id == hdmi_tx_V720x480i_60Hz_16x9)
6027	\|\| (hdmi_tx_video_timing_id == hdmi_tx_V720x576i_50Hz_16x9)
6028	\|\| (hdmi_tx_video_timing_id == hdmi_tx_V720x480i_60Hz_4x3)
6029	\|\| (hdmi_tx_video_timing_id == hdmi_tx_V720x576i_50Hz_4x3))
6030	hdmi_tx_tx_pix_rpt = 1;
6031	else
6032	hdmi_tx_tx_pix_rpt = 0;
6033	}
6034	//set input pixel repeat times
6035	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE_REG, &c);
6036	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE_REG, ((c & 0xfc) \|hdmi_tx_in_pix_rpt));
6037	//set link pixel repeat times
6038	DHL_SYS_ANXRead(0, HDMI_TX_VID_CTRL_REG, &c);
6039	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CTRL_REG, ((c & 0xfc) \|hdmi_tx_tx_pix_rpt));
6040
6041	if((hdmi_tx_in_pix_rpt != hdmi_tx_in_pix_rpt_bkp)
6042	\|\|(hdmi_tx_tx_pix_rpt != hdmi_tx_tx_pix_rpt_bkp) )
6043	{
6044	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, 0x02);
6045	DHL_SYS_ANXWrite(0, HDMI_TX_SYS_CTRL2_REG, 0x00);
6046	HDMI_TX_DebugPrintf("MISC_Reset!\n");
6047	hdmi_tx_in_pix_rpt_bkp = hdmi_tx_in_pix_rpt;
6048	hdmi_tx_tx_pix_rpt_bkp = hdmi_tx_tx_pix_rpt;
6049	}
6050	}
6051
6052	void HDMI_TX_Video_Interface_HW_Setting(void)
6053	{
6054	BYTE c;
6055	TT();
6056	if(hdmi_tx_de_gen_en)
6057	{
6058	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
6059	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, c \| HDMI_TX_VID_CAPCTRL0_DEGEN_EN);
6060	}
6061	if(hdmi_tx_emb_sync_mode)
6062	{
6063	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
6064	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, c \| HDMI_TX_VID_CAPCTRL0_EMSYNC_EN);
6065	}
6066	if(hdmi_tx_demux_yc_en)
6067	{
6068	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
6069	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, c \| HDMI_TX_VID_CAPCTRL0_DEMUX_EN);
6070	DHL_SYS_ANXRead(0, HDMI_TX_VID_MODE2_REG, &c);
6071	DHL_SYS_ANXWrite(0, HDMI_TX_VID_MODE2_REG, ((c & 0xf3) \| hdmi_tx_ycmux_BIT_sel << 2));
6072	}
6073	if(hdmi_tx_ddr_bus_mode)
6074	{
6075	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
6076	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, c \| HDMI_TX_VID_CAPCTRL0_DV_BUSMODE);
6077	if(hdmi_tx_ddr_edge)
6078	{
6079	DHL_SYS_ANXRead(0, HDMI_TX_VID_CAPCTRL0_REG, &c);
6080	DHL_SYS_ANXWrite(0, HDMI_TX_VID_CAPCTRL0_REG, c \| HDMI_TX_VID_CAPCTRL0_DDR_EDGE);
6081	}
6082	}
6083	}
6084
6085	#if (HDMI_TX_USE_NATIVE_CODE)
6086	///////////////for repeater
6087	void HDMI_RPT_Set_BCAPS_Repeater(BIT is_repeater)
6088	{
6089	#if USE_HDMI_RX
6090	BYTE c;
6091
6092	if (DD_SYS_IsANX8775Exist())
6093	{
6094	HDMI_RX_ReadI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, &c);
6095	if(is_repeater)
6096	{
6097	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, c \| HDMI_RX_REPERTER);
6098	printf("[HDMI_TX] Repeater Bit is SET.\n");
6099	}
6100	else
6101	{
6102	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, c & ~HDMI_RX_REPERTER);
6103	printf("[HDMI_TX] Repeater Bit is CLEAR.\n");
6104	}
6105	}
6106	#endif
6107	}
6108
6109	void HDMI_RPT_Set_KSVList_Init(BYTE start_addr,BYTE length)
6110	{
6111	#if USE_HDMI_RX
6112	if(DD_SYS_IsANX8775Exist())
6113	{
6114	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_SHA_LENGTHL_REG, length);
6115	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_KSV_SHA_STARTL_REG, start_addr);
6116	}
6117	#endif
6118	}
6119
6120	void HDMI_RPT_Set_BSTATUS1(BYTE bstatus1)
6121	{
6122	#if USE_HDMI_RX
6123	if(DD_SYS_IsANX8775Exist())
6124	{
6125	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW1_REG, bstatus1);
6126	}
6127	#endif
6128	}
6129
6130	void HDMI_RPT_Set_BSTATUS2(BYTE bstatus2)
6131	{
6132	#if USE_HDMI_RX
6133	if(DD_SYS_IsANX8775Exist())
6134	{
6135	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BSTATUS_SHADOW2_REG, bstatus2);
6136	}
6137	#endif
6138	}
6139
6140	void HDMI_RPT_Set_SHA_Calc_Start(void)
6141	{
6142	#if USE_HDMI_RX
6143	if (DD_SYS_IsANX8775Exist())
6144	{
6145	HDMI_TX_DebugPrintf("Start SHA Calc\n");
6146	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_SHA_CTRL_REG, HDMI_RX_SHA_GO);
6147	}
6148	#endif
6149	}
6150
6151	BIT HDMI_RPT_Get_SHA_Ready(void)
6152	{
6153	#if USE_HDMI_RX
6154	if(DD_SYS_IsANX8775Exist())
6155	{
6156	BYTE c;
6157	HDMI_RX_ReadI2C_RX1(HDMI_RX_HDCP_SHA_CTRL_REG, &c);
6158	if(c & 0x01)
6159	return 0;
6160	return 1;
6161	}
6162	#endif
6163	return 1;
6164	}
6165
6166	void HDMI_RPT_Set_BCAPS_Ready(BIT ready)
6167	{
6168	#if USE_HDMI_RX
6169	BYTE c;
6170
6171	if (DD_SYS_IsANX8775Exist())
6172	{
6173	HDMI_RX_ReadI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, &c);
6174	if(ready)
6175	{
6176	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, c \| HDMI_RX_READY);
6177	HDMI_TX_DebugPrintf("Set KSV FIFO ready!\n");
6178	}
6179	else
6180	HDMI_RX_WriteI2C_RX1(HDMI_RX_HDCP_BCAPS_SHADOW_REG, c & ~HDMI_RX_READY);
6181	}
6182	#endif
6183	}
6184	#endif
6185
6186	void HDMI_Print_Register(void)
6187	{
6188	int i;
6189	BYTE c1, c2;
6190
6191	printf("Address Value \| Address Value\n");
6192	for (i=0; i<=0xFF; i++) {
6193	DHL_SYS_ANXRead(0, i, &c1);
6194	DHL_SYS_ANXRead(1, i, &c2);
6195	printf(" 0x%02X 0x%02X \| 0x%02X 0x%02X\n", i, c1, i, c2);
6196	}
6197	}
6198
6199
6200	void HDMI_TX_Read_EDID_Test(int segptr)
6201	{
6202	TT();
6203	HDMI_TX_RST_DDCChannel();
6204
6205	HDMI_TX_InitDDC_Read(0xa0, segptr, 0x00, 0x80, 0x00);
6206	HDMI_TX_DDC_Mass_Read(128, hdmi_tx_edid_buf);
6207	HDMI_TX_DebugPrintf("Finish reading EDID\n");
6208	}
6209
6210	int HDMI_TX_IsPlayback(void)
6211	{
6212	return HDMI_TX_system_state == HDMI_TX_PLAY_BACK;
6213	}

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source: svn/zas_dstar/devices/HDMI_TX/ANX8560/HDMI_TX_DRV.c

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