/****************************************************************************** *_Copyright (c) 2009 Digital Stream Technology Inc. All Rights Reserved. * * Module: panel_data.h * * Description * * @author * @version $Revision: 1.1 $ * ******************************************************************************/ #ifndef __PANEL_DATA_H__ #define __PANEL_DATA_H__ #include "dsthalcommon.h" typedef enum { PIF_NO_DIVISION = 0, PIF_DIVISION_BY_2, PIF_DIVISION_BY_4, PIF_DIVISION_BY_8 }PIFDivSel; #define NO_OF_LVDSTX_MAPS 21 #define NO_OF_LVDSRX_MUX 12 typedef struct LvdsTxConfig { DS_U32 LvdsTxEn:1; //0: TTL 1:LVDS DS_U32 LvdsTxEvenOddSwap:1; DS_U32 LvdsTxPosNegSwap:1; DS_U8 LvdsTxClockData; }LvdsTxIFConfig; typedef struct LvdsRxConfig { DS_U32 LvdsRxEn:1; DS_U32 LvdsRxOddEvenSyncSel:1; DS_U32 LvdsRxOddEvenDataSwap:1; DS_U32 LvdsRxJmodeEn:1; DS_U32 LvdsRxRBSwap:1; DS_U32 LvdsRxPosNegSwap:1; DS_U32 LvdsRxResTrim:5; DS_U32 LvdsRxEvenChEn:7; DS_U32 LvdsRxOddChEn:7; DS_U16 LvdsRxPllCtrl_0; }LvdsRxIFConfig; typedef struct PanelIFConfig { DS_U32 Input_PPC:1; DS_U32 Output_PPC:1; DS_U32 Invert_DVS:1; DS_U32 Invert_DHS:1; DS_U32 Invert_DCLK:1; DS_U32 Invert_DEN:1; DS_U32 VidIn_BPP_sel:2; DS_U32 DisplayTTLRBSwap:1; DS_U32 DisplayTTLDataRev:1; DS_U32 PanelPowerFastTickEn:1; DS_U32 Reserved:21; PIFDivSel DivRatio; DS_U32 VidInOutputClkDelayCtrl; DS_U16 VidinVerticalActive; DS_U16 LvdsorTTLTxEvenPadCtrl; DS_U16 LvdsorTTLTxOddPadCtrl; DS_U16 PanelPowerUpTime; DS_U16 PanelPowerDownTime; LvdsTxIFConfig LvdsTxIFConf; LvdsRxIFConfig LvdsRxIFConf; }PanelIFConfig; typedef struct tag_PanelConfig_t { DS_U8 LvdsTxFmt; /* LVDS Format Pin - Reflects LVDS_FMT */ DS_U8 LvdsRxClock; /* LVDS Rx Clock Polarity */ DS_U16 RxPll; /* Rx PLL Register Value - 0x854 or 0xad0 */ PanelIFConfig PnlCfg; DS_S16 DimmOnTime; // backlight on to Dimming on delay if negative, dimming must started before backlight on DS_S16 DimmOffTime; // backlight off to Dimming on delay DS_S16 InvertOnTime; // Inverter on to Dimming on delay DS_S16 InvertOffTime; // Dimming off to Inverter Off } PanelConfig_t; ///////////////////////////////////////////////////////////////////////////// // RX PLL Register Value // Following values are evaluated and tested for various panel. // - 0xAD0 for LG 17" panel // - 0x854 for other panel ///////////////////////////////////////////////////////////////////////////// #define STANDARD_FMT 0x100 #define JEIDA_FMT 0x101 ///////////////////////////////////////////////////////////////////////////// // LVDS Transmit Mapping // Single: Use only one channel of LVDS, even or odd. // Double: Use both channel of LVDS, even and odd. // Standard: Map R/G/B[6:0] to R/G/B[6:0] // Japanese: Map R/G/B[7:2] to R/G/B[5:0] and R/G/B[1:0] to R/G/B[7:6] (2-bit shifted) ///////////////////////////////////////////////////////////////////////////// /* Single link - Standard */ #define LVDSTX_MAPS__SINGLE_ST { \ 0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF } /* Single link - Japanese */ #define LVDSTX_MAPS__SINGLE_JP { \ 0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF } /* Double link - Standard */ #define LVDSTX_MAPS__DOUBLE_ST { \ 0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF } /* Double link - Japanese */ #define LVDSTX_MAPS__DOUBLE_JP { \ 0xC2, 0x144,0x1C6, 0x3CE, 0x450, 0x4D2, 0x6DA, 0x75C, 0x7DE, 0x964, 0x26 , 0x301, 0x60D, 0x9D9 } /* CMO TX MAP인데 HS, VS --> 1로 바꿈 */ #define LVDSTX_MAPS__CMO_SPECIFIC { \ 0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0xA28, 0x1A6, 0x487, 0x793, 0x9DF } #define LVDSTX_MAPS__LPL_SPECIFIC { \ 0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0xA28, 0x1A6, 0x487, 0x793, 0xA1F } ///////////////////////////////////////////////////////////////////////////// // LVDS Rx Mapping // This depends on the LVDS connector. // If LVDS[0:3] is connected to LVDS[0:3], then use NORMAL. // If LVDS[0:3] is connected to LVDS[3:0], i.e. connected in reverse order, then use SWAP. ///////////////////////////////////////////////////////////////////////////// #define LVDSRX_MAPS__SINGLE_NORMAL { 0x43, 0x42, 0x41, 0x40, 0x44, 0x45 } #define LVDSRX_MAPS__SINGLE_SWAP { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45 } #define LVDSRX_MAPS__DOUBLE_NORMAL { 0x43, 0x42, 0x41, 0x40, 0x44, 0x45, 0x43, 0x42, 0x41, 0x40, 0x44, 0x45 } #define LVDSRX_MAPS__DOUBLE_SWAP { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45 } ///////////////////////////////////////////////////////////////////////////// // PanelPowerUpTime / PanelPowerDownTime // 값 1 당 약 4.8ms ( FastTickEn = 0 시 ) ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // AUO 26" 768P Panel ///////////////////////////////////////////////////////////////////////////// PanelConfig_t PanelData_T260XW02 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x7E07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_LTA46WT_L03 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_LC320W01 = { 1, // LVDS_FMT = 0 1, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_LC420W01 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_LC171W03 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_V320B1 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x6907, //PanelPowerUpTime 0x0715, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_T370HW01 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a06, //PanelPowerUpTime 0x0715, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_V370H1 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x1507, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_LC420WU1_SL01 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_V216C1 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 900, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x5e07, //PanelPowerUpTime 0x0715, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x1E, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 1, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_V420H1 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x6907, //PanelPowerUpTime 0x0715, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_V470H1_L02 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x6907, //PanelPowerUpTime 0x0715, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_CUSTOM_720P = { // nLighten 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x2d0, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x96, //PanelPowerUpTime 0xff, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxSTANDARDBit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_CUSTOM = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x2d0, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0x96, //PanelPowerUpTime 0xff, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxSTANDARDBit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_LTA460HS_LH4 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0xDC07, //PanelPowerUpTime 0x0719, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, -500, 500, 500, 500 }; PanelConfig_t PanelData_LC470WU1_SL01 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_LTA460HS_L02 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0xDC07, //PanelPowerUpTime 0x0719, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, -500, 500, 500, 500 }; PanelConfig_t PanelData_LG_WSXGA_LM201W01 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x3407, //PanelPowerUpTime 0x0734, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_T420XW01 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0xa607, //PanelPowerUpTime 0x07a6, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, -500, 0, 0, 0 }; PanelConfig_t PanelData_T460HW02 = { 1, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 0, //Input_PPC 0, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x0F80, //LvdsorTTLTxEvenPadCtrl 0x0000, //LvdsorTTLTxOddPadCtrl 0xa607, //PanelPowerUpTime 0x07a6, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 0, 0 }; PanelConfig_t PanelData_LG_PDP60X62000 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_T420HW01 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_LC520WU1_SLA1 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity JEIDA_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x438, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 1, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; PanelConfig_t PanelData_LG_PDP71H2 = { 0, // LVDS_FMT = 0 0, // LVDS Clock Polarity STANDARD_FMT, // PLL Value { // PanelIFConfig 1, //Input_PPC 1, //Output_PPC 0, //Invert_DVS 0, //Invert_DHS 0, //Invert_DCLK 0, //Invert_DEN 0, //VidIn_BPP_sel 0, //DisplayTTLRBSwap 0, //DisplayTTLDataRev 0, //PanelPowerFastTickEn 0, //Reserved PIF_DIVISION_BY_8, 0x00, //VidInOutputClkDelayCtrl 0x300, //VidinVerticalActive 0x3F80, //LvdsorTTLTxEvenPadCtrl 0x3F80, //LvdsorTTLTxOddPadCtrl 0x2a07, //PanelPowerUpTime 0x072a, //PanelPowerDownTime { 1, //LvdsTxEn 0, //LvdsTxEvenOddSwap 0, //LvdsTxPosNegSwap 0x63, //LvdsTxClockData; }, { 1, //LvdsRxEn:1; //0: TTL 1:LVDS 0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link 0, //LvdsRxOddEvenDataSwap:1; 0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config 0, //LvdsRxRBSwap:1; 1, //LvdsRxPosNegSwap:1; 0, //LvdsRxResTrim:5;//control bits for termination resistance 0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0 STANDARD_FMT,//LvdsRxPllCtrl_0 } }, 0, 0, 500, 0 }; #endif