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panel_data.h @ 76

Last change on this file since 76 was 76, checked in by megakiss, 10 years ago
1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
File size: 33.5 KB

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1	/******************************************************************************
2	*_Copyright (c) 2009 Digital Stream Technology Inc. All Rights Reserved.
3	*
4	* Module: panel_data.h
5	*
6	* Description
7	*
8	* @author
9	* @version $Revision: 1.1 $
10	*
11	******************************************************************************/
12
13	#ifndef __PANEL_DATA_H__
14	#define __PANEL_DATA_H__
15
16	#include "dsthalcommon.h"
17
18	typedef enum
19	{
20	PIF_NO_DIVISION = 0,
21	PIF_DIVISION_BY_2,
22	PIF_DIVISION_BY_4,
23	PIF_DIVISION_BY_8
24	}PIFDivSel;
25
26	#define NO_OF_LVDSTX_MAPS 21
27	#define NO_OF_LVDSRX_MUX 12
28
29	typedef struct LvdsTxConfig
30	{
31	DS_U32 LvdsTxEn:1; //0: TTL 1:LVDS
32	DS_U32 LvdsTxEvenOddSwap:1;
33	DS_U32 LvdsTxPosNegSwap:1;
34	DS_U8 LvdsTxClockData;
35	}LvdsTxIFConfig;
36
37	typedef struct LvdsRxConfig
38	{
39	DS_U32 LvdsRxEn:1;
40	DS_U32 LvdsRxOddEvenSyncSel:1;
41	DS_U32 LvdsRxOddEvenDataSwap:1;
42	DS_U32 LvdsRxJmodeEn:1;
43	DS_U32 LvdsRxRBSwap:1;
44	DS_U32 LvdsRxPosNegSwap:1;
45	DS_U32 LvdsRxResTrim:5;
46	DS_U32 LvdsRxEvenChEn:7;
47	DS_U32 LvdsRxOddChEn:7;
48	DS_U16 LvdsRxPllCtrl_0;
49	}LvdsRxIFConfig;
50
51	typedef struct PanelIFConfig
52	{
53	DS_U32 Input_PPC:1;
54	DS_U32 Output_PPC:1;
55	DS_U32 Invert_DVS:1;
56	DS_U32 Invert_DHS:1;
57	DS_U32 Invert_DCLK:1;
58	DS_U32 Invert_DEN:1;
59	DS_U32 VidIn_BPP_sel:2;
60	DS_U32 DisplayTTLRBSwap:1;
61	DS_U32 DisplayTTLDataRev:1;
62	DS_U32 PanelPowerFastTickEn:1;
63	DS_U32 Reserved:21;
64	PIFDivSel DivRatio;
65	DS_U32 VidInOutputClkDelayCtrl;
66	DS_U16 VidinVerticalActive;
67	DS_U16 LvdsorTTLTxEvenPadCtrl;
68	DS_U16 LvdsorTTLTxOddPadCtrl;
69	DS_U16 PanelPowerUpTime;
70	DS_U16 PanelPowerDownTime;
71	LvdsTxIFConfig LvdsTxIFConf;
72	LvdsRxIFConfig LvdsRxIFConf;
73	}PanelIFConfig;
74
75	typedef struct tag_PanelConfig_t {
76	DS_U8 LvdsTxFmt; /* LVDS Format Pin - Reflects LVDS_FMT */
77	DS_U8 LvdsRxClock; /* LVDS Rx Clock Polarity */
78	DS_U16 RxPll; /* Rx PLL Register Value - 0x854 or 0xad0 */
79	PanelIFConfig PnlCfg;
80	DS_S16 DimmOnTime; // backlight on to Dimming on delay if negative, dimming must started before backlight on
81	DS_S16 DimmOffTime; // backlight off to Dimming on delay
82	DS_S16 InvertOnTime; // Inverter on to Dimming on delay
83	DS_S16 InvertOffTime; // Dimming off to Inverter Off
84	} PanelConfig_t;
85
86	/////////////////////////////////////////////////////////////////////////////
87	// RX PLL Register Value
88	// Following values are evaluated and tested for various panel.
89	// - 0xAD0 for LG 17" panel
90	// - 0x854 for other panel
91	/////////////////////////////////////////////////////////////////////////////
92	#define STANDARD_FMT 0x100
93	#define JEIDA_FMT 0x101
94
95	/////////////////////////////////////////////////////////////////////////////
96	// LVDS Transmit Mapping
97	// Single: Use only one channel of LVDS, even or odd.
98	// Double: Use both channel of LVDS, even and odd.
99	// Standard: Map R/G/B[6:0] to R/G/B[6:0]
100	// Japanese: Map R/G/B[7:2] to R/G/B[5:0] and R/G/B[1:0] to R/G/B[7:6] (2-bit shifted)
101	/////////////////////////////////////////////////////////////////////////////
102	/* Single link - Standard */
103	#define LVDSTX_MAPS__SINGLE_ST { \
104	0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF }
105
106	/* Single link - Japanese */
107	#define LVDSTX_MAPS__SINGLE_JP { \
108	0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF }
109
110	/* Double link - Standard */
111	#define LVDSTX_MAPS__DOUBLE_ST { \
112	0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0x964, 0x1A6, 0x487, 0x793, 0x9DF }
113
114	/* Double link - Japanese */
115	#define LVDSTX_MAPS__DOUBLE_JP { \
116	0xC2, 0x144,0x1C6, 0x3CE, 0x450, 0x4D2, 0x6DA, 0x75C, 0x7DE, 0x964, 0x26 , 0x301, 0x60D, 0x9D9 }
117
118	/* CMO TX MAPÀÎµ¥ HS, VS --> 1·Î ¹Ù²Þ */
119	#define LVDSTX_MAPS__CMO_SPECIFIC { \
120	0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0xA28, 0x1A6, 0x487, 0x793, 0x9DF }
121
122	#define LVDSTX_MAPS__LPL_SPECIFIC { \
123	0x40, 0xC2, 0x144, 0x34C, 0x3CE, 0x450, 0x658, 0x6DA, 0x75C, 0xA28, 0x1A6, 0x487, 0x793, 0xA1F }
124	/////////////////////////////////////////////////////////////////////////////
125	// LVDS Rx Mapping
126	// This depends on the LVDS connector.
127	// If LVDS[0:3] is connected to LVDS[0:3], then use NORMAL.
128	// If LVDS[0:3] is connected to LVDS[3:0], i.e. connected in reverse order, then use SWAP.
129	/////////////////////////////////////////////////////////////////////////////
130	#define LVDSRX_MAPS__SINGLE_NORMAL { 0x43, 0x42, 0x41, 0x40, 0x44, 0x45 }
131
132	#define LVDSRX_MAPS__SINGLE_SWAP { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45 }
133
134	#define LVDSRX_MAPS__DOUBLE_NORMAL { 0x43, 0x42, 0x41, 0x40, 0x44, 0x45, 0x43, 0x42, 0x41, 0x40, 0x44, 0x45 }
135
136	#define LVDSRX_MAPS__DOUBLE_SWAP { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45 }
137	/////////////////////////////////////////////////////////////////////////////
138	// PanelPowerUpTime / PanelPowerDownTime
139	// °ª 1 ´ç ¾à 4.8ms ( FastTickEn = 0 ½Ã )
140	/////////////////////////////////////////////////////////////////////////////
141
142	/////////////////////////////////////////////////////////////////////////////
143	// AUO 26" 768P Panel
144	/////////////////////////////////////////////////////////////////////////////
145	PanelConfig_t PanelData_T260XW02 = {
146	0, // LVDS_FMT = 0
147	0, // LVDS Clock Polarity
148	STANDARD_FMT, // PLL Value
149	{ // PanelIFConfig
150	0, //Input_PPC
151	0, //Output_PPC
152	0, //Invert_DVS
153	0, //Invert_DHS
154	0, //Invert_DCLK
155	0, //Invert_DEN
156	0, //VidIn_BPP_sel
157	0, //DisplayTTLRBSwap
158	0, //DisplayTTLDataRev
159	0, //PanelPowerFastTickEn
160	0, //Reserved
161	PIF_DIVISION_BY_8,
162	0x00, //VidInOutputClkDelayCtrl
163	0x300, //VidinVerticalActive
164	0x0F80, //LvdsorTTLTxEvenPadCtrl
165	0x0000, //LvdsorTTLTxOddPadCtrl
166	0x7E07, //PanelPowerUpTime
167	0x072a, //PanelPowerDownTime
168	{
169	1, //LvdsTxEn
170	0, //LvdsTxEvenOddSwap
171	0, //LvdsTxPosNegSwap
172	0x63, //LvdsTxClockData;
173	},
174	{
175	1, //LvdsRxEn:1; //0: TTL 1:LVDS
176	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
177	0, //LvdsRxOddEvenDataSwap:1;
178	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
179	0, //LvdsRxRBSwap:1;
180	1, //LvdsRxPosNegSwap:1;
181	0, //LvdsRxResTrim:5;//control bits for termination resistance
182	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
183	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
184	STANDARD_FMT,//LvdsRxPllCtrl_0
185	}
186	},
187	0,
188	0,
189	0,
190	0
191	};
192
193	PanelConfig_t PanelData_LTA46WT_L03 = {
194	1, // LVDS_FMT = 0
195	0, // LVDS Clock Polarity
196	JEIDA_FMT, // PLL Value
197	{ // PanelIFConfig
198	0, //Input_PPC
199	0, //Output_PPC
200	0, //Invert_DVS
201	0, //Invert_DHS
202	0, //Invert_DCLK
203	0, //Invert_DEN
204	0, //VidIn_BPP_sel
205	0, //DisplayTTLRBSwap
206	0, //DisplayTTLDataRev
207	0, //PanelPowerFastTickEn
208	0, //Reserved
209	PIF_DIVISION_BY_8,
210	0x00, //VidInOutputClkDelayCtrl
211	0x300, //VidinVerticalActive
212	0x0F80, //LvdsorTTLTxEvenPadCtrl
213	0x0000, //LvdsorTTLTxOddPadCtrl
214	0x2a07, //PanelPowerUpTime
215	0x072a, //PanelPowerDownTime
216	{
217	1, //LvdsTxEn
218	0, //LvdsTxEvenOddSwap
219	0, //LvdsTxPosNegSwap
220	0x63, //LvdsTxClockData;
221	},
222	{
223	1, //LvdsRxEn:1; //0: TTL 1:LVDS
224	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
225	0, //LvdsRxOddEvenDataSwap:1;
226	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
227	0, //LvdsRxRBSwap:1;
228	1, //LvdsRxPosNegSwap:1;
229	0, //LvdsRxResTrim:5;//control bits for termination resistance
230	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
231	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
232	STANDARD_FMT,//LvdsRxPllCtrl_0
233	}
234	},
235	0,
236	0,
237	500,
238	0
239	};
240
241	PanelConfig_t PanelData_LC320W01 = {
242	1, // LVDS_FMT = 0
243	1, // LVDS Clock Polarity
244	STANDARD_FMT, // PLL Value
245	{ // PanelIFConfig
246	0, //Input_PPC
247	0, //Output_PPC
248	0, //Invert_DVS
249	0, //Invert_DHS
250	0, //Invert_DCLK
251	0, //Invert_DEN
252	0, //VidIn_BPP_sel
253	0, //DisplayTTLRBSwap
254	0, //DisplayTTLDataRev
255	0, //PanelPowerFastTickEn
256	0, //Reserved
257	PIF_DIVISION_BY_8,
258	0x00, //VidInOutputClkDelayCtrl
259	0x300, //VidinVerticalActive
260	0x0F80, //LvdsorTTLTxEvenPadCtrl
261	0x0000, //LvdsorTTLTxOddPadCtrl
262	0x2a07, //PanelPowerUpTime
263	0x072a, //PanelPowerDownTime
264	{
265	1, //LvdsTxEn
266	0, //LvdsTxEvenOddSwap
267	0, //LvdsTxPosNegSwap
268	0x63, //LvdsTxClockData;
269	},
270	{
271	1, //LvdsRxEn:1; //0: TTL 1:LVDS
272	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
273	0, //LvdsRxOddEvenDataSwap:1;
274	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
275	0, //LvdsRxRBSwap:1;
276	1, //LvdsRxPosNegSwap:1;
277	0, //LvdsRxResTrim:5;//control bits for termination resistance
278	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
279	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
280	STANDARD_FMT,//LvdsRxPllCtrl_0
281	}
282	},
283	0,
284	0,
285	0,
286	0
287	};
288
289	PanelConfig_t PanelData_LC420W01 = {
290	0, // LVDS_FMT = 0
291	0, // LVDS Clock Polarity
292	JEIDA_FMT, // PLL Value
293	{ // PanelIFConfig
294	0, //Input_PPC
295	0, //Output_PPC
296	0, //Invert_DVS
297	0, //Invert_DHS
298	0, //Invert_DCLK
299	0, //Invert_DEN
300	0, //VidIn_BPP_sel
301	0, //DisplayTTLRBSwap
302	0, //DisplayTTLDataRev
303	0, //PanelPowerFastTickEn
304	0, //Reserved
305	PIF_DIVISION_BY_8,
306	0x00, //VidInOutputClkDelayCtrl
307	0x300, //VidinVerticalActive
308	0x0F80, //LvdsorTTLTxEvenPadCtrl
309	0x0000, //LvdsorTTLTxOddPadCtrl
310	0x2a07, //PanelPowerUpTime
311	0x072a, //PanelPowerDownTime
312	{
313	1, //LvdsTxEn
314	0, //LvdsTxEvenOddSwap
315	0, //LvdsTxPosNegSwap
316	0x63, //LvdsTxClockData;
317	},
318	{
319	1, //LvdsRxEn:1; //0: TTL 1:LVDS
320	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
321	0, //LvdsRxOddEvenDataSwap:1;
322	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
323	0, //LvdsRxRBSwap:1;
324	1, //LvdsRxPosNegSwap:1;
325	0, //LvdsRxResTrim:5;//control bits for termination resistance
326	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
327	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
328	STANDARD_FMT,//LvdsRxPllCtrl_0
329	}
330	},
331	0,
332	0,
333	500,
334	0
335	};
336
337	PanelConfig_t PanelData_LC171W03 = {
338	1, // LVDS_FMT = 0
339	0, // LVDS Clock Polarity
340	JEIDA_FMT, // PLL Value
341	{ // PanelIFConfig
342	0, //Input_PPC
343	0, //Output_PPC
344	0, //Invert_DVS
345	0, //Invert_DHS
346	0, //Invert_DCLK
347	0, //Invert_DEN
348	0, //VidIn_BPP_sel
349	0, //DisplayTTLRBSwap
350	0, //DisplayTTLDataRev
351	0, //PanelPowerFastTickEn
352	0, //Reserved
353	PIF_DIVISION_BY_8,
354	0x00, //VidInOutputClkDelayCtrl
355	0x300, //VidinVerticalActive
356	0x0F80, //LvdsorTTLTxEvenPadCtrl
357	0x0000, //LvdsorTTLTxOddPadCtrl
358	0x2a07, //PanelPowerUpTime
359	0x072a, //PanelPowerDownTime
360	{
361	1, //LvdsTxEn
362	0, //LvdsTxEvenOddSwap
363	0, //LvdsTxPosNegSwap
364	0x63, //LvdsTxClockData;
365	},
366	{
367	1, //LvdsRxEn:1; //0: TTL 1:LVDS
368	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
369	0, //LvdsRxOddEvenDataSwap:1;
370	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
371	0, //LvdsRxRBSwap:1;
372	1, //LvdsRxPosNegSwap:1;
373	0, //LvdsRxResTrim:5;//control bits for termination resistance
374	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
375	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
376	STANDARD_FMT,//LvdsRxPllCtrl_0
377	}
378	},
379	0,
380	0,
381	0,
382	0
383	};
384
385	PanelConfig_t PanelData_V320B1 = {
386	0, // LVDS_FMT = 0
387	0, // LVDS Clock Polarity
388	STANDARD_FMT, // PLL Value
389	{ // PanelIFConfig
390	0, //Input_PPC
391	0, //Output_PPC
392	0, //Invert_DVS
393	0, //Invert_DHS
394	0, //Invert_DCLK
395	0, //Invert_DEN
396	0, //VidIn_BPP_sel
397	0, //DisplayTTLRBSwap
398	0, //DisplayTTLDataRev
399	0, //PanelPowerFastTickEn
400	0, //Reserved
401	PIF_DIVISION_BY_8,
402	0x00, //VidInOutputClkDelayCtrl
403	0x300, //VidinVerticalActive
404	0x0F80, //LvdsorTTLTxEvenPadCtrl
405	0x0000, //LvdsorTTLTxOddPadCtrl
406	0x6907, //PanelPowerUpTime
407	0x0715, //PanelPowerDownTime
408	{
409	1, //LvdsTxEn
410	0, //LvdsTxEvenOddSwap
411	0, //LvdsTxPosNegSwap
412	0x63, //LvdsTxClockData;
413	},
414	{
415	1, //LvdsRxEn:1; //0: TTL 1:LVDS
416	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
417	0, //LvdsRxOddEvenDataSwap:1;
418	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
419	0, //LvdsRxRBSwap:1;
420	1, //LvdsRxPosNegSwap:1;
421	0, //LvdsRxResTrim:5;//control bits for termination resistance
422	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
423	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
424	STANDARD_FMT,//LvdsRxPllCtrl_0
425	}
426	},
427	0,
428	0,
429	0,
430	0
431	};
432
433	PanelConfig_t PanelData_T370HW01 = {
434	1, // LVDS_FMT = 0
435	0, // LVDS Clock Polarity
436	JEIDA_FMT, // PLL Value
437	{ // PanelIFConfig
438	1, //Input_PPC
439	1, //Output_PPC
440	0, //Invert_DVS
441	0, //Invert_DHS
442	0, //Invert_DCLK
443	0, //Invert_DEN
444	0, //VidIn_BPP_sel
445	0, //DisplayTTLRBSwap
446	0, //DisplayTTLDataRev
447	0, //PanelPowerFastTickEn
448	0, //Reserved
449	PIF_DIVISION_BY_8,
450	0x00, //VidInOutputClkDelayCtrl
451	0x438, //VidinVerticalActive
452	0x3F80, //LvdsorTTLTxEvenPadCtrl
453	0x3F80, //LvdsorTTLTxOddPadCtrl
454	0x2a06, //PanelPowerUpTime
455	0x0715, //PanelPowerDownTime
456	{
457	1, //LvdsTxEn
458	1, //LvdsTxEvenOddSwap
459	0, //LvdsTxPosNegSwap
460	0x63, //LvdsTxClockData;
461	},
462	{
463	1, //LvdsRxEn:1; //0: TTL 1:LVDS
464	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
465	0, //LvdsRxOddEvenDataSwap:1;
466	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
467	0, //LvdsRxRBSwap:1;
468	1, //LvdsRxPosNegSwap:1;
469	0, //LvdsRxResTrim:5;//control bits for termination resistance
470	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
471	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
472	STANDARD_FMT,//LvdsRxPllCtrl_0
473	}
474	},
475	0,
476	0,
477	0,
478	0
479	};
480
481	PanelConfig_t PanelData_V370H1 = {
482	1, // LVDS_FMT = 0
483	0, // LVDS Clock Polarity
484	STANDARD_FMT, // PLL Value
485	{ // PanelIFConfig
486	0, //Input_PPC
487	0, //Output_PPC
488	0, //Invert_DVS
489	0, //Invert_DHS
490	0, //Invert_DCLK
491	0, //Invert_DEN
492	0, //VidIn_BPP_sel
493	0, //DisplayTTLRBSwap
494	0, //DisplayTTLDataRev
495	0, //PanelPowerFastTickEn
496	0, //Reserved
497	PIF_DIVISION_BY_8,
498	0x00, //VidInOutputClkDelayCtrl
499	0x300, //VidinVerticalActive
500	0x0F80, //LvdsorTTLTxEvenPadCtrl
501	0x0000, //LvdsorTTLTxOddPadCtrl
502	0x1507, //PanelPowerUpTime
503	0x072a, //PanelPowerDownTime
504	{
505	1, //LvdsTxEn
506	0, //LvdsTxEvenOddSwap
507	0, //LvdsTxPosNegSwap
508	0x63, //LvdsTxClockData;
509	},
510	{
511	1, //LvdsRxEn:1; //0: TTL 1:LVDS
512	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
513	0, //LvdsRxOddEvenDataSwap:1;
514	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
515	0, //LvdsRxRBSwap:1;
516	1, //LvdsRxPosNegSwap:1;
517	0, //LvdsRxResTrim:5;//control bits for termination resistance
518	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
519	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
520	STANDARD_FMT,//LvdsRxPllCtrl_0
521	}
522	},
523	0,
524	0,
525	0,
526	0
527	};
528
529
530	PanelConfig_t PanelData_LC420WU1_SL01 = {
531	0, // LVDS_FMT = 0
532	0, // LVDS Clock Polarity
533	JEIDA_FMT, // PLL Value
534	{ // PanelIFConfig
535	1, //Input_PPC
536	1, //Output_PPC
537	0, //Invert_DVS
538	0, //Invert_DHS
539	0, //Invert_DCLK
540	0, //Invert_DEN
541	0, //VidIn_BPP_sel
542	0, //DisplayTTLRBSwap
543	0, //DisplayTTLDataRev
544	0, //PanelPowerFastTickEn
545	0, //Reserved
546	PIF_DIVISION_BY_8,
547	0x00, //VidInOutputClkDelayCtrl
548	0x438, //VidinVerticalActive
549	0x3F80, //LvdsorTTLTxEvenPadCtrl
550	0x3F80, //LvdsorTTLTxOddPadCtrl
551	0x2a07, //PanelPowerUpTime
552	0x072a, //PanelPowerDownTime
553	{
554	1, //LvdsTxEn
555	1, //LvdsTxEvenOddSwap
556	0, //LvdsTxPosNegSwap
557	0x63, //LvdsTxClockData;
558	},
559	{
560	1, //LvdsRxEn:1; //0: TTL 1:LVDS
561	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
562	0, //LvdsRxOddEvenDataSwap:1;
563	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
564	0, //LvdsRxRBSwap:1;
565	1, //LvdsRxPosNegSwap:1;
566	0, //LvdsRxResTrim:5;//control bits for termination resistance
567	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
568	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
569	STANDARD_FMT,//LvdsRxPllCtrl_0
570	}
571	},
572	0,
573	0,
574	500,
575	0
576	};
577
578	PanelConfig_t PanelData_V216C1 = {
579	1, // LVDS_FMT = 0
580	0, // LVDS Clock Polarity
581	STANDARD_FMT, // PLL Value
582	{ // PanelIFConfig
583	1, //Input_PPC
584	1, //Output_PPC
585	0, //Invert_DVS
586	0, //Invert_DHS
587	0, //Invert_DCLK
588	0, //Invert_DEN
589	0, //VidIn_BPP_sel
590	0, //DisplayTTLRBSwap
591	0, //DisplayTTLDataRev
592	0, //PanelPowerFastTickEn
593	0, //Reserved
594	PIF_DIVISION_BY_8,
595	0x00, //VidInOutputClkDelayCtrl
596	900, //VidinVerticalActive
597	0x3F80, //LvdsorTTLTxEvenPadCtrl
598	0x3F80, //LvdsorTTLTxOddPadCtrl
599	0x5e07, //PanelPowerUpTime
600	0x0715, //PanelPowerDownTime
601	{
602	1, //LvdsTxEn
603	1, //LvdsTxEvenOddSwap
604	0, //LvdsTxPosNegSwap
605	0x1E, //LvdsTxClockData;
606	},
607	{
608	1, //LvdsRxEn:1; //0: TTL 1:LVDS
609	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
610	1, //LvdsRxOddEvenDataSwap:1;
611	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
612	0, //LvdsRxRBSwap:1;
613	1, //LvdsRxPosNegSwap:1;
614	0, //LvdsRxResTrim:5;//control bits for termination resistance
615	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
616	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
617	STANDARD_FMT,//LvdsRxPllCtrl_0
618	}
619	},
620	0,
621	0,
622	0,
623	0
624	};
625
626	PanelConfig_t PanelData_V420H1 = {
627	0, // LVDS_FMT = 0
628	0, // LVDS Clock Polarity
629	JEIDA_FMT, // PLL Value
630	{ // PanelIFConfig
631	1, //Input_PPC
632	1, //Output_PPC
633	0, //Invert_DVS
634	0, //Invert_DHS
635	0, //Invert_DCLK
636	0, //Invert_DEN
637	0, //VidIn_BPP_sel
638	0, //DisplayTTLRBSwap
639	0, //DisplayTTLDataRev
640	0, //PanelPowerFastTickEn
641	0, //Reserved
642	PIF_DIVISION_BY_8,
643	0x00, //VidInOutputClkDelayCtrl
644	0x438, //VidinVerticalActive
645	0x3F80, //LvdsorTTLTxEvenPadCtrl
646	0x3F80, //LvdsorTTLTxOddPadCtrl
647	0x6907, //PanelPowerUpTime
648	0x0715, //PanelPowerDownTime
649	{
650	1, //LvdsTxEn
651	0, //LvdsTxEvenOddSwap
652	0, //LvdsTxPosNegSwap
653	0x63, //LvdsTxClockData;
654	},
655	{
656	1, //LvdsRxEn:1; //0: TTL 1:LVDS
657	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
658	0, //LvdsRxOddEvenDataSwap:1;
659	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
660	0, //LvdsRxRBSwap:1;
661	1, //LvdsRxPosNegSwap:1;
662	0, //LvdsRxResTrim:5;//control bits for termination resistance
663	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
664	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
665	STANDARD_FMT,//LvdsRxPllCtrl_0
666	}
667	},
668	0,
669	0,
670	0,
671	0
672	};
673
674	PanelConfig_t PanelData_V470H1_L02 = {
675	1, // LVDS_FMT = 0
676	0, // LVDS Clock Polarity
677	JEIDA_FMT, // PLL Value
678	{ // PanelIFConfig
679	1, //Input_PPC
680	1, //Output_PPC
681	0, //Invert_DVS
682	0, //Invert_DHS
683	0, //Invert_DCLK
684	0, //Invert_DEN
685	0, //VidIn_BPP_sel
686	0, //DisplayTTLRBSwap
687	0, //DisplayTTLDataRev
688	0, //PanelPowerFastTickEn
689	0, //Reserved
690	PIF_DIVISION_BY_8,
691	0x00, //VidInOutputClkDelayCtrl
692	0x438, //VidinVerticalActive
693	0x3F80, //LvdsorTTLTxEvenPadCtrl
694	0x3F80, //LvdsorTTLTxOddPadCtrl
695	0x6907, //PanelPowerUpTime
696	0x0715, //PanelPowerDownTime
697	{
698	1, //LvdsTxEn
699	0, //LvdsTxEvenOddSwap
700	0, //LvdsTxPosNegSwap
701	0x63, //LvdsTxClockData;
702	},
703	{
704	1, //LvdsRxEn:1; //0: TTL 1:LVDS
705	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
706	0, //LvdsRxOddEvenDataSwap:1;
707	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
708	0, //LvdsRxRBSwap:1;
709	1, //LvdsRxPosNegSwap:1;
710	0, //LvdsRxResTrim:5;//control bits for termination resistance
711	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
712	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
713	STANDARD_FMT,//LvdsRxPllCtrl_0
714	}
715	},
716	0,
717	0,
718	0,
719	0
720	};
721
722	PanelConfig_t PanelData_CUSTOM_720P = { // nLighten
723	1, // LVDS_FMT = 0
724	0, // LVDS Clock Polarity
725	STANDARD_FMT, // PLL Value
726	{ // PanelIFConfig
727	0, //Input_PPC
728	0, //Output_PPC
729	0, //Invert_DVS
730	0, //Invert_DHS
731	0, //Invert_DCLK
732	0, //Invert_DEN
733	0, //VidIn_BPP_sel
734	0, //DisplayTTLRBSwap
735	0, //DisplayTTLDataRev
736	0, //PanelPowerFastTickEn
737	0, //Reserved
738	PIF_DIVISION_BY_8,
739	0x00, //VidInOutputClkDelayCtrl
740	0x2d0, //VidinVerticalActive
741	0x0F80, //LvdsorTTLTxEvenPadCtrl
742	0x0000, //LvdsorTTLTxOddPadCtrl
743	0x96, //PanelPowerUpTime
744	0xff, //PanelPowerDownTime
745	{
746	1, //LvdsTxEn
747	0, //LvdsTxEvenOddSwap
748	0, //LvdsTxPosNegSwap
749	0x63, //LvdsTxClockData;
750	},
751	{
752	1, //LvdsRxEn:1; //0: TTL 1:LVDS
753	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
754	0, //LvdsRxOddEvenDataSwap:1;
755	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
756	0, //LvdsRxRBSwap:1;
757	1, //LvdsRxPosNegSwap:1;
758	0, //LvdsRxResTrim:5;//control bits for termination resistance
759	0x1F,//LvdsRxSTANDARDBit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
760	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
761	STANDARD_FMT,//LvdsRxPllCtrl_0
762	}
763	},
764	0,
765	0,
766	0,
767	0
768	};
769
770	PanelConfig_t PanelData_CUSTOM = {
771	1, // LVDS_FMT = 0
772	0, // LVDS Clock Polarity
773	STANDARD_FMT, // PLL Value
774	{ // PanelIFConfig
775	0, //Input_PPC
776	0, //Output_PPC
777	0, //Invert_DVS
778	0, //Invert_DHS
779	0, //Invert_DCLK
780	0, //Invert_DEN
781	0, //VidIn_BPP_sel
782	0, //DisplayTTLRBSwap
783	0, //DisplayTTLDataRev
784	0, //PanelPowerFastTickEn
785	0, //Reserved
786	PIF_DIVISION_BY_8,
787	0x00, //VidInOutputClkDelayCtrl
788	0x2d0, //VidinVerticalActive
789	0x0F80, //LvdsorTTLTxEvenPadCtrl
790	0x0000, //LvdsorTTLTxOddPadCtrl
791	0x96, //PanelPowerUpTime
792	0xff, //PanelPowerDownTime
793	{
794	1, //LvdsTxEn
795	0, //LvdsTxEvenOddSwap
796	0, //LvdsTxPosNegSwap
797	0x63, //LvdsTxClockData;
798	},
799	{
800	1, //LvdsRxEn:1; //0: TTL 1:LVDS
801	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
802	0, //LvdsRxOddEvenDataSwap:1;
803	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
804	0, //LvdsRxRBSwap:1;
805	1, //LvdsRxPosNegSwap:1;
806	0, //LvdsRxResTrim:5;//control bits for termination resistance
807	0x1F,//LvdsRxSTANDARDBit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
808	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
809	STANDARD_FMT,//LvdsRxPllCtrl_0
810	}
811	},
812	0,
813	0,
814	0,
815	0
816	};
817
818	PanelConfig_t PanelData_LTA460HS_LH4 = {
819	1, // LVDS_FMT = 0
820	0, // LVDS Clock Polarity
821	JEIDA_FMT, // PLL Value
822	{ // PanelIFConfig
823	1, //Input_PPC
824	1, //Output_PPC
825	0, //Invert_DVS
826	0, //Invert_DHS
827	0, //Invert_DCLK
828	0, //Invert_DEN
829	0, //VidIn_BPP_sel
830	0, //DisplayTTLRBSwap
831	0, //DisplayTTLDataRev
832	0, //PanelPowerFastTickEn
833	0, //Reserved
834	PIF_DIVISION_BY_8,
835	0x00, //VidInOutputClkDelayCtrl
836	0x438, //VidinVerticalActive
837	0x3F80, //LvdsorTTLTxEvenPadCtrl
838	0x3F80, //LvdsorTTLTxOddPadCtrl
839	0xDC07, //PanelPowerUpTime
840	0x0719, //PanelPowerDownTime
841	{
842	1, //LvdsTxEn
843	1, //LvdsTxEvenOddSwap
844	0, //LvdsTxPosNegSwap
845	0x63, //LvdsTxClockData;
846	},
847	{
848	1, //LvdsRxEn:1; //0: TTL 1:LVDS
849	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
850	0, //LvdsRxOddEvenDataSwap:1;
851	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
852	0, //LvdsRxRBSwap:1;
853	1, //LvdsRxPosNegSwap:1;
854	0, //LvdsRxResTrim:5;//control bits for termination resistance
855	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
856	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
857	STANDARD_FMT,//LvdsRxPllCtrl_0
858	}
859	},
860	-500,
861	500,
862	500,
863	500
864	};
865
866	PanelConfig_t PanelData_LC470WU1_SL01 = {
867	0, // LVDS_FMT = 0
868	0, // LVDS Clock Polarity
869	JEIDA_FMT, // PLL Value
870	{ // PanelIFConfig
871	1, //Input_PPC
872	1, //Output_PPC
873	0, //Invert_DVS
874	0, //Invert_DHS
875	0, //Invert_DCLK
876	0, //Invert_DEN
877	0, //VidIn_BPP_sel
878	0, //DisplayTTLRBSwap
879	0, //DisplayTTLDataRev
880	0, //PanelPowerFastTickEn
881	0, //Reserved
882	PIF_DIVISION_BY_8,
883	0x00, //VidInOutputClkDelayCtrl
884	0x438, //VidinVerticalActive
885	0x3F80, //LvdsorTTLTxEvenPadCtrl
886	0x3F80, //LvdsorTTLTxOddPadCtrl
887	0x2a07, //PanelPowerUpTime
888	0x072a, //PanelPowerDownTime
889	{
890	1, //LvdsTxEn
891	1, //LvdsTxEvenOddSwap
892	0, //LvdsTxPosNegSwap
893	0x63, //LvdsTxClockData;
894	},
895	{
896	1, //LvdsRxEn:1; //0: TTL 1:LVDS
897	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
898	0, //LvdsRxOddEvenDataSwap:1;
899	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
900	0, //LvdsRxRBSwap:1;
901	1, //LvdsRxPosNegSwap:1;
902	0, //LvdsRxResTrim:5;//control bits for termination resistance
903	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
904	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
905	STANDARD_FMT,//LvdsRxPllCtrl_0
906	}
907	},
908	0,
909	0,
910	500,
911	0
912	};
913
914	PanelConfig_t PanelData_LTA460HS_L02 = {
915	1, // LVDS_FMT = 0
916	0, // LVDS Clock Polarity
917	JEIDA_FMT, // PLL Value
918	{ // PanelIFConfig
919	1, //Input_PPC
920	1, //Output_PPC
921	0, //Invert_DVS
922	0, //Invert_DHS
923	0, //Invert_DCLK
924	0, //Invert_DEN
925	0, //VidIn_BPP_sel
926	0, //DisplayTTLRBSwap
927	0, //DisplayTTLDataRev
928	0, //PanelPowerFastTickEn
929	0, //Reserved
930	PIF_DIVISION_BY_8,
931	0x00, //VidInOutputClkDelayCtrl
932	0x438, //VidinVerticalActive
933	0x3F80, //LvdsorTTLTxEvenPadCtrl
934	0x3F80, //LvdsorTTLTxOddPadCtrl
935	0xDC07, //PanelPowerUpTime
936	0x0719, //PanelPowerDownTime
937	{
938	1, //LvdsTxEn
939	1, //LvdsTxEvenOddSwap
940	0, //LvdsTxPosNegSwap
941	0x63, //LvdsTxClockData;
942	},
943	{
944	1, //LvdsRxEn:1; //0: TTL 1:LVDS
945	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
946	0, //LvdsRxOddEvenDataSwap:1;
947	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
948	0, //LvdsRxRBSwap:1;
949	1, //LvdsRxPosNegSwap:1;
950	0, //LvdsRxResTrim:5;//control bits for termination resistance
951	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
952	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
953	STANDARD_FMT,//LvdsRxPllCtrl_0
954	}
955	},
956	-500,
957	500,
958	500,
959	500
960	};
961	PanelConfig_t PanelData_LG_WSXGA_LM201W01 = {
962	0, // LVDS_FMT = 0
963	0, // LVDS Clock Polarity
964	STANDARD_FMT, // PLL Value
965	{ // PanelIFConfig
966	1, //Input_PPC
967	1, //Output_PPC
968	0, //Invert_DVS
969	0, //Invert_DHS
970	0, //Invert_DCLK
971	0, //Invert_DEN
972	0, //VidIn_BPP_sel
973	0, //DisplayTTLRBSwap
974	0, //DisplayTTLDataRev
975	0, //PanelPowerFastTickEn
976	0, //Reserved
977	PIF_DIVISION_BY_8,
978	0x00, //VidInOutputClkDelayCtrl
979	0x438, //VidinVerticalActive
980	0x3F80, //LvdsorTTLTxEvenPadCtrl
981	0x3F80, //LvdsorTTLTxOddPadCtrl
982	0x3407, //PanelPowerUpTime
983	0x0734, //PanelPowerDownTime
984	{
985	1, //LvdsTxEn
986	0, //LvdsTxEvenOddSwap
987	0, //LvdsTxPosNegSwap
988	0x63, //LvdsTxClockData;
989	},
990	{
991	1, //LvdsRxEn:1; //0: TTL 1:LVDS
992	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
993	0, //LvdsRxOddEvenDataSwap:1;
994	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
995	0, //LvdsRxRBSwap:1;
996	1, //LvdsRxPosNegSwap:1;
997	0, //LvdsRxResTrim:5;//control bits for termination resistance
998	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
999	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1000	STANDARD_FMT,//LvdsRxPllCtrl_0
1001	}
1002	},
1003	0,
1004	0,
1005	0,
1006	0
1007	};
1008
1009	PanelConfig_t PanelData_T420XW01 = {
1010	1, // LVDS_FMT = 0
1011	0, // LVDS Clock Polarity
1012	STANDARD_FMT, // PLL Value
1013	{ // PanelIFConfig
1014	0, //Input_PPC
1015	0, //Output_PPC
1016	0, //Invert_DVS
1017	0, //Invert_DHS
1018	0, //Invert_DCLK
1019	0, //Invert_DEN
1020	0, //VidIn_BPP_sel
1021	0, //DisplayTTLRBSwap
1022	0, //DisplayTTLDataRev
1023	0, //PanelPowerFastTickEn
1024	0, //Reserved
1025	PIF_DIVISION_BY_8,
1026	0x00, //VidInOutputClkDelayCtrl
1027	0x300, //VidinVerticalActive
1028	0x0F80, //LvdsorTTLTxEvenPadCtrl
1029	0x0000, //LvdsorTTLTxOddPadCtrl
1030	0xa607, //PanelPowerUpTime
1031	0x07a6, //PanelPowerDownTime
1032	{
1033	1, //LvdsTxEn
1034	0, //LvdsTxEvenOddSwap
1035	0, //LvdsTxPosNegSwap
1036	0x63, //LvdsTxClockData;
1037	},
1038	{
1039	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1040	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1041	0, //LvdsRxOddEvenDataSwap:1;
1042	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1043	0, //LvdsRxRBSwap:1;
1044	1, //LvdsRxPosNegSwap:1;
1045	0, //LvdsRxResTrim:5;//control bits for termination resistance
1046	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1047	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1048	STANDARD_FMT,//LvdsRxPllCtrl_0
1049	}
1050	},
1051	-500,
1052	0,
1053	0,
1054	0
1055	};
1056
1057	PanelConfig_t PanelData_T460HW02 = {
1058	1, // LVDS_FMT = 0
1059	0, // LVDS Clock Polarity
1060	JEIDA_FMT, // PLL Value
1061	{ // PanelIFConfig
1062	0, //Input_PPC
1063	0, //Output_PPC
1064	0, //Invert_DVS
1065	0, //Invert_DHS
1066	0, //Invert_DCLK
1067	0, //Invert_DEN
1068	0, //VidIn_BPP_sel
1069	0, //DisplayTTLRBSwap
1070	0, //DisplayTTLDataRev
1071	0, //PanelPowerFastTickEn
1072	0, //Reserved
1073	PIF_DIVISION_BY_8,
1074	0x00, //VidInOutputClkDelayCtrl
1075	0x300, //VidinVerticalActive
1076	0x0F80, //LvdsorTTLTxEvenPadCtrl
1077	0x0000, //LvdsorTTLTxOddPadCtrl
1078	0xa607, //PanelPowerUpTime
1079	0x07a6, //PanelPowerDownTime
1080	{
1081	1, //LvdsTxEn
1082	0, //LvdsTxEvenOddSwap
1083	0, //LvdsTxPosNegSwap
1084	0x63, //LvdsTxClockData;
1085	},
1086	{
1087	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1088	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1089	0, //LvdsRxOddEvenDataSwap:1;
1090	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1091	0, //LvdsRxRBSwap:1;
1092	1, //LvdsRxPosNegSwap:1;
1093	0, //LvdsRxResTrim:5;//control bits for termination resistance
1094	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1095	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1096	STANDARD_FMT,//LvdsRxPllCtrl_0
1097	}
1098	},
1099	0,
1100	0,
1101	0,
1102	0
1103	};
1104
1105	PanelConfig_t PanelData_LG_PDP60X62000 = {
1106	0, // LVDS_FMT = 0
1107	0, // LVDS Clock Polarity
1108	STANDARD_FMT, // PLL Value
1109	{ // PanelIFConfig
1110	1, //Input_PPC
1111	1, //Output_PPC
1112	0, //Invert_DVS
1113	0, //Invert_DHS
1114	0, //Invert_DCLK
1115	0, //Invert_DEN
1116	0, //VidIn_BPP_sel
1117	0, //DisplayTTLRBSwap
1118	0, //DisplayTTLDataRev
1119	0, //PanelPowerFastTickEn
1120	0, //Reserved
1121	PIF_DIVISION_BY_8,
1122	0x00, //VidInOutputClkDelayCtrl
1123	0x300, //VidinVerticalActive
1124	0x3F80, //LvdsorTTLTxEvenPadCtrl
1125	0x3F80, //LvdsorTTLTxOddPadCtrl
1126	0x2a07, //PanelPowerUpTime
1127	0x072a, //PanelPowerDownTime
1128	{
1129	1, //LvdsTxEn
1130	0, //LvdsTxEvenOddSwap
1131	0, //LvdsTxPosNegSwap
1132	0x63, //LvdsTxClockData;
1133	},
1134	{
1135	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1136	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1137	0, //LvdsRxOddEvenDataSwap:1;
1138	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1139	0, //LvdsRxRBSwap:1;
1140	1, //LvdsRxPosNegSwap:1;
1141	0, //LvdsRxResTrim:5;//control bits for termination resistance
1142	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1143	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1144	STANDARD_FMT,//LvdsRxPllCtrl_0
1145	}
1146	},
1147	0,
1148	0,
1149	500,
1150	0
1151	};
1152
1153	PanelConfig_t PanelData_T420HW01 = {
1154	0, // LVDS_FMT = 0
1155	0, // LVDS Clock Polarity
1156	JEIDA_FMT, // PLL Value
1157	{ // PanelIFConfig
1158	1, //Input_PPC
1159	1, //Output_PPC
1160	0, //Invert_DVS
1161	0, //Invert_DHS
1162	0, //Invert_DCLK
1163	0, //Invert_DEN
1164	0, //VidIn_BPP_sel
1165	0, //DisplayTTLRBSwap
1166	0, //DisplayTTLDataRev
1167	0, //PanelPowerFastTickEn
1168	0, //Reserved
1169	PIF_DIVISION_BY_8,
1170	0x00, //VidInOutputClkDelayCtrl
1171	0x438, //VidinVerticalActive
1172	0x3F80, //LvdsorTTLTxEvenPadCtrl
1173	0x3F80, //LvdsorTTLTxOddPadCtrl
1174	0x2a07, //PanelPowerUpTime
1175	0x072a, //PanelPowerDownTime
1176	{
1177	1, //LvdsTxEn
1178	1, //LvdsTxEvenOddSwap
1179	0, //LvdsTxPosNegSwap
1180	0x63, //LvdsTxClockData;
1181	},
1182	{
1183	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1184	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1185	0, //LvdsRxOddEvenDataSwap:1;
1186	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1187	0, //LvdsRxRBSwap:1;
1188	1, //LvdsRxPosNegSwap:1;
1189	0, //LvdsRxResTrim:5;//control bits for termination resistance
1190	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1191	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1192	STANDARD_FMT,//LvdsRxPllCtrl_0
1193	}
1194	},
1195	0,
1196	0,
1197	500,
1198	0
1199	};
1200
1201	PanelConfig_t PanelData_LC520WU1_SLA1 = {
1202	0, // LVDS_FMT = 0
1203	0, // LVDS Clock Polarity
1204	JEIDA_FMT, // PLL Value
1205	{ // PanelIFConfig
1206	1, //Input_PPC
1207	1, //Output_PPC
1208	0, //Invert_DVS
1209	0, //Invert_DHS
1210	0, //Invert_DCLK
1211	0, //Invert_DEN
1212	0, //VidIn_BPP_sel
1213	0, //DisplayTTLRBSwap
1214	0, //DisplayTTLDataRev
1215	0, //PanelPowerFastTickEn
1216	0, //Reserved
1217	PIF_DIVISION_BY_8,
1218	0x00, //VidInOutputClkDelayCtrl
1219	0x438, //VidinVerticalActive
1220	0x3F80, //LvdsorTTLTxEvenPadCtrl
1221	0x3F80, //LvdsorTTLTxOddPadCtrl
1222	0x2a07, //PanelPowerUpTime
1223	0x072a, //PanelPowerDownTime
1224	{
1225	1, //LvdsTxEn
1226	1, //LvdsTxEvenOddSwap
1227	0, //LvdsTxPosNegSwap
1228	0x63, //LvdsTxClockData;
1229	},
1230	{
1231	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1232	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1233	0, //LvdsRxOddEvenDataSwap:1;
1234	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1235	0, //LvdsRxRBSwap:1;
1236	1, //LvdsRxPosNegSwap:1;
1237	0, //LvdsRxResTrim:5;//control bits for termination resistance
1238	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1239	0x1F,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1240	STANDARD_FMT,//LvdsRxPllCtrl_0
1241	}
1242	},
1243	0,
1244	0,
1245	500,
1246	0
1247	};
1248
1249	PanelConfig_t PanelData_LG_PDP71H2 = {
1250	0, // LVDS_FMT = 0
1251	0, // LVDS Clock Polarity
1252	STANDARD_FMT, // PLL Value
1253	{ // PanelIFConfig
1254	1, //Input_PPC
1255	1, //Output_PPC
1256	0, //Invert_DVS
1257	0, //Invert_DHS
1258	0, //Invert_DCLK
1259	0, //Invert_DEN
1260	0, //VidIn_BPP_sel
1261	0, //DisplayTTLRBSwap
1262	0, //DisplayTTLDataRev
1263	0, //PanelPowerFastTickEn
1264	0, //Reserved
1265	PIF_DIVISION_BY_8,
1266	0x00, //VidInOutputClkDelayCtrl
1267	0x300, //VidinVerticalActive
1268	0x3F80, //LvdsorTTLTxEvenPadCtrl
1269	0x3F80, //LvdsorTTLTxOddPadCtrl
1270	0x2a07, //PanelPowerUpTime
1271	0x072a, //PanelPowerDownTime
1272	{
1273	1, //LvdsTxEn
1274	0, //LvdsTxEvenOddSwap
1275	0, //LvdsTxPosNegSwap
1276	0x63, //LvdsTxClockData;
1277	},
1278	{
1279	1, //LvdsRxEn:1; //0: TTL 1:LVDS
1280	0, //LvdsRxOddEvenSyncSel:1; //0:even link 1:odd link
1281	0, //LvdsRxOddEvenDataSwap:1;
1282	0, //LvdsRxJmodeEn:1;//0:non-japanese LVDS config 1:japanese config
1283	0, //LvdsRxRBSwap:1;
1284	1, //LvdsRxPosNegSwap:1;
1285	0, //LvdsRxResTrim:5;//control bits for termination resistance
1286	0x1F,//LvdsRxEvenChEn:7; //Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1287	0x00,//LvdsRxOddChEn:7;//Bit order Ch5,ch4,Clk,Ch3,Ch2,Ch1,ch0
1288	STANDARD_FMT,//LvdsRxPllCtrl_0
1289	}
1290	},
1291	0,
1292	0,
1293	500,
1294	0
1295	};
1296	#endif

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source: svn/zas_dstar/hal/platform/panel_data.h @ 76

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