source: svn/trunk/newcon3bcm2_21bu/dta/src/bootloader7574/clocks.c @ 2

/***************************************************************************
 *     Copyright (c) 2011, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description: Setup MEMC ARB client and Clocks
 *
 * Revision History:
 *
 * $brcm_Log: $
 * 
 *
 ***************************************************************************/
#include "bstd.h"
#include "bmips.h"
#include "bchp_common.h"
#include "bchp_clkgen.h"
#include "bchp_memc_arb_0.h"
#include "memc_0_1_core_val.h"

#include "bchp_aon_ctrl.h"
#include "bchp_ufe_afe.h"
#include "bchp_gio_aon.h"

/* Description:
 * set_memc0_rts_val and set_clocks_for_profile is coming from
 * CFE's bcm97358_devs.c
 *
 * ARB_0_CLIENT value is defined in memc_0_1_core_val.h
 * CLOCK info comes from bootloader.mk
 */

void set_memc0_rts_val(void)
{
        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_0) = BCHP_MEMC_ARB_0_CLIENT_INFO_0_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_1) = BCHP_MEMC_ARB_0_CLIENT_INFO_1_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_2) = BCHP_MEMC_ARB_0_CLIENT_INFO_2_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_3) = BCHP_MEMC_ARB_0_CLIENT_INFO_3_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_4) = BCHP_MEMC_ARB_0_CLIENT_INFO_4_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_5) = BCHP_MEMC_ARB_0_CLIENT_INFO_5_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_6) = BCHP_MEMC_ARB_0_CLIENT_INFO_6_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_7) = BCHP_MEMC_ARB_0_CLIENT_INFO_7_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_8) = BCHP_MEMC_ARB_0_CLIENT_INFO_8_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_9) = BCHP_MEMC_ARB_0_CLIENT_INFO_9_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_10) = BCHP_MEMC_ARB_0_CLIENT_INFO_10_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_11) = BCHP_MEMC_ARB_0_CLIENT_INFO_11_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_12) = BCHP_MEMC_ARB_0_CLIENT_INFO_12_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_13) = BCHP_MEMC_ARB_0_CLIENT_INFO_13_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_14) = BCHP_MEMC_ARB_0_CLIENT_INFO_14_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_15) = BCHP_MEMC_ARB_0_CLIENT_INFO_15_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_16) = BCHP_MEMC_ARB_0_CLIENT_INFO_16_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_17) = BCHP_MEMC_ARB_0_CLIENT_INFO_17_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_18) = BCHP_MEMC_ARB_0_CLIENT_INFO_18_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_19) = BCHP_MEMC_ARB_0_CLIENT_INFO_19_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_20) = BCHP_MEMC_ARB_0_CLIENT_INFO_20_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_21) = BCHP_MEMC_ARB_0_CLIENT_INFO_21_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_22) = BCHP_MEMC_ARB_0_CLIENT_INFO_22_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_23) = BCHP_MEMC_ARB_0_CLIENT_INFO_23_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_24) = BCHP_MEMC_ARB_0_CLIENT_INFO_24_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_25) = BCHP_MEMC_ARB_0_CLIENT_INFO_25_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_26) = BCHP_MEMC_ARB_0_CLIENT_INFO_26_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_27) = BCHP_MEMC_ARB_0_CLIENT_INFO_27_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_28) = BCHP_MEMC_ARB_0_CLIENT_INFO_28_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_29) = BCHP_MEMC_ARB_0_CLIENT_INFO_29_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_30) = BCHP_MEMC_ARB_0_CLIENT_INFO_30_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_31) = BCHP_MEMC_ARB_0_CLIENT_INFO_31_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_32) = BCHP_MEMC_ARB_0_CLIENT_INFO_32_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_33) = BCHP_MEMC_ARB_0_CLIENT_INFO_33_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_34) = BCHP_MEMC_ARB_0_CLIENT_INFO_34_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_35) = BCHP_MEMC_ARB_0_CLIENT_INFO_35_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_36) = BCHP_MEMC_ARB_0_CLIENT_INFO_36_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_37) = BCHP_MEMC_ARB_0_CLIENT_INFO_37_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_38) = BCHP_MEMC_ARB_0_CLIENT_INFO_38_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_39) = BCHP_MEMC_ARB_0_CLIENT_INFO_39_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_40) = BCHP_MEMC_ARB_0_CLIENT_INFO_40_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_41) = BCHP_MEMC_ARB_0_CLIENT_INFO_41_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_42) = BCHP_MEMC_ARB_0_CLIENT_INFO_42_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_43) = BCHP_MEMC_ARB_0_CLIENT_INFO_43_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_44) = BCHP_MEMC_ARB_0_CLIENT_INFO_44_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_45) = BCHP_MEMC_ARB_0_CLIENT_INFO_45_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_46) = BCHP_MEMC_ARB_0_CLIENT_INFO_46_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_47) = BCHP_MEMC_ARB_0_CLIENT_INFO_47_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_48) = BCHP_MEMC_ARB_0_CLIENT_INFO_48_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_49) = BCHP_MEMC_ARB_0_CLIENT_INFO_49_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_50) = BCHP_MEMC_ARB_0_CLIENT_INFO_50_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_51) = BCHP_MEMC_ARB_0_CLIENT_INFO_51_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_52) = BCHP_MEMC_ARB_0_CLIENT_INFO_52_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_53) = BCHP_MEMC_ARB_0_CLIENT_INFO_53_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_54) = BCHP_MEMC_ARB_0_CLIENT_INFO_54_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_55) = BCHP_MEMC_ARB_0_CLIENT_INFO_55_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_56) = BCHP_MEMC_ARB_0_CLIENT_INFO_56_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_57) = BCHP_MEMC_ARB_0_CLIENT_INFO_57_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_58) = BCHP_MEMC_ARB_0_CLIENT_INFO_58_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_59) = BCHP_MEMC_ARB_0_CLIENT_INFO_59_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_60) = BCHP_MEMC_ARB_0_CLIENT_INFO_60_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_61) = BCHP_MEMC_ARB_0_CLIENT_INFO_61_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_62) = BCHP_MEMC_ARB_0_CLIENT_INFO_62_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_63) = BCHP_MEMC_ARB_0_CLIENT_INFO_63_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_64) = BCHP_MEMC_ARB_0_CLIENT_INFO_64_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_65) = BCHP_MEMC_ARB_0_CLIENT_INFO_65_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_66) = BCHP_MEMC_ARB_0_CLIENT_INFO_66_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_67) = BCHP_MEMC_ARB_0_CLIENT_INFO_67_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_68) = BCHP_MEMC_ARB_0_CLIENT_INFO_68_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_69) = BCHP_MEMC_ARB_0_CLIENT_INFO_69_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_70) = BCHP_MEMC_ARB_0_CLIENT_INFO_70_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_71) = BCHP_MEMC_ARB_0_CLIENT_INFO_71_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_72) = BCHP_MEMC_ARB_0_CLIENT_INFO_72_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_73) = BCHP_MEMC_ARB_0_CLIENT_INFO_73_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_74) = BCHP_MEMC_ARB_0_CLIENT_INFO_74_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_75) = BCHP_MEMC_ARB_0_CLIENT_INFO_75_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_76) = BCHP_MEMC_ARB_0_CLIENT_INFO_76_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_77) = BCHP_MEMC_ARB_0_CLIENT_INFO_77_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_78) = BCHP_MEMC_ARB_0_CLIENT_INFO_78_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_79) = BCHP_MEMC_ARB_0_CLIENT_INFO_79_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_80) = BCHP_MEMC_ARB_0_CLIENT_INFO_80_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_81) = BCHP_MEMC_ARB_0_CLIENT_INFO_81_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_82) = BCHP_MEMC_ARB_0_CLIENT_INFO_82_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_83) = BCHP_MEMC_ARB_0_CLIENT_INFO_83_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_84) = BCHP_MEMC_ARB_0_CLIENT_INFO_84_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_85) = BCHP_MEMC_ARB_0_CLIENT_INFO_85_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_86) = BCHP_MEMC_ARB_0_CLIENT_INFO_86_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_87) = BCHP_MEMC_ARB_0_CLIENT_INFO_87_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_88) = BCHP_MEMC_ARB_0_CLIENT_INFO_88_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_89) = BCHP_MEMC_ARB_0_CLIENT_INFO_89_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_90) = BCHP_MEMC_ARB_0_CLIENT_INFO_90_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_91) = BCHP_MEMC_ARB_0_CLIENT_INFO_91_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_92) = BCHP_MEMC_ARB_0_CLIENT_INFO_92_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_93)= BCHP_MEMC_ARB_0_CLIENT_INFO_93_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_94) = BCHP_MEMC_ARB_0_CLIENT_INFO_94_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_95) = BCHP_MEMC_ARB_0_CLIENT_INFO_95_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_96) = BCHP_MEMC_ARB_0_CLIENT_INFO_96_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_97) = BCHP_MEMC_ARB_0_CLIENT_INFO_97_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_98) = BCHP_MEMC_ARB_0_CLIENT_INFO_98_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_99) = BCHP_MEMC_ARB_0_CLIENT_INFO_99_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_100) = BCHP_MEMC_ARB_0_CLIENT_INFO_100_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_101) = BCHP_MEMC_ARB_0_CLIENT_INFO_101_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_102) = BCHP_MEMC_ARB_0_CLIENT_INFO_102_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_103) = BCHP_MEMC_ARB_0_CLIENT_INFO_103_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_104) = BCHP_MEMC_ARB_0_CLIENT_INFO_104_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_105) = BCHP_MEMC_ARB_0_CLIENT_INFO_105_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_106) = BCHP_MEMC_ARB_0_CLIENT_INFO_106_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_107) = BCHP_MEMC_ARB_0_CLIENT_INFO_107_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_108) = BCHP_MEMC_ARB_0_CLIENT_INFO_108_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_109) = BCHP_MEMC_ARB_0_CLIENT_INFO_109_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_110) = BCHP_MEMC_ARB_0_CLIENT_INFO_110_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_111) = BCHP_MEMC_ARB_0_CLIENT_INFO_111_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_112) = BCHP_MEMC_ARB_0_CLIENT_INFO_112_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_113) = BCHP_MEMC_ARB_0_CLIENT_INFO_113_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_114) = BCHP_MEMC_ARB_0_CLIENT_INFO_114_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_115) = BCHP_MEMC_ARB_0_CLIENT_INFO_115_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_116) = BCHP_MEMC_ARB_0_CLIENT_INFO_116_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_117) = BCHP_MEMC_ARB_0_CLIENT_INFO_117_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_118) = BCHP_MEMC_ARB_0_CLIENT_INFO_118_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_119) = BCHP_MEMC_ARB_0_CLIENT_INFO_119_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_120) = BCHP_MEMC_ARB_0_CLIENT_INFO_120_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_121) = BCHP_MEMC_ARB_0_CLIENT_INFO_121_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_122) = BCHP_MEMC_ARB_0_CLIENT_INFO_122_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_123) = BCHP_MEMC_ARB_0_CLIENT_INFO_123_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_124) = BCHP_MEMC_ARB_0_CLIENT_INFO_124_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_125) = BCHP_MEMC_ARB_0_CLIENT_INFO_125_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_126) = BCHP_MEMC_ARB_0_CLIENT_INFO_126_VAL;

        REG(BCHP_MEMC_ARB_0_CLIENT_INFO_127) = BCHP_MEMC_ARB_0_CLIENT_INFO_127_VAL;
}

void set_clocks_for_profile(void)
{
        volatile unsigned long temp_reg;

        /* set SPI clock */
        temp_reg =      *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4);
        temp_reg &= ~(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK | BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK);
        temp_reg |= (32 << BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4) = temp_reg;
        temp_reg |= BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4) = temp_reg;

        /* Setting CPU clock */
        temp_reg = *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0);
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK;
        temp_reg |= (CPU_MDIV << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0) = temp_reg;

        /* Generate the pulse by writing 1 followed by 0 to POST_DIVIDER_LOAD_EN_CH0 bit*/
        temp_reg |= (1 << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0) = temp_reg;
        /* clear the POST_DIVIDER_LOAD_EN_CH0 bit */
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0) = temp_reg;

        /* Setting AVD core clock */
        temp_reg = *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1);
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK;
        temp_reg |= (AVD_MDIV << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1) = temp_reg;

        /* Generate the pulse by writing 1 followed by 0 to POST_DIVIDER_LOAD_EN_CH1 bit*/
        temp_reg |= (1 << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1) = temp_reg;
        /* clear the POST_DIVIDER_LOAD_EN_CH1 bit */
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1) = temp_reg;

        /* Setting AVD CPU clock */
        temp_reg = *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2);
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK;
        temp_reg |= (AVD_CPU_MDIV << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2) = temp_reg;

        /* Generate the pulse by writing 1 followed by 0 to POST_DIVIDER_LOAD_EN_CH2 bit*/
        temp_reg |= (1 << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2) = temp_reg;
        /* clear the POST_DIVIDER_LOAD_EN_CH2 bit */
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2) = temp_reg;

        /* Setting DSP clock */
        temp_reg = *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3);
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK;
        temp_reg |= (DSP_MDIV << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3) = temp_reg;

        /* Generate the pulse by writing 1 followed by 0 to POST_DIVIDER_LOAD_EN_CH3 bit*/
        temp_reg |= (1 << BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3) = temp_reg;
        /* clear the POST_DIVIDER_LOAD_EN_CH3 bit */
        temp_reg &= ~BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3) = temp_reg;

        /* Setting SCB clock */
        temp_reg = *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3);
        temp_reg &= ~BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK;
        temp_reg |= (SCB_MDIV << BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3) = temp_reg;

        /* Generate the pulse by writing 1 followed by 0 to POST_DIVIDER_LOAD_EN_CH3 bit*/
        temp_reg |= (1 << BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT);
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3) = temp_reg;
        /* clear the POST_DIVIDER_LOAD_EN_CH3 bit */
        temp_reg &= ~BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK;
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3) = temp_reg;

        /* turn off tuner loop */
        temp_reg = REG(BCHP_UFE_AFE_TNR0_PWRUP_01);
        temp_reg &= ~BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LT_MASK;
        /*  power off daisy */
        temp_reg &= ~BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_UHF_MASK;
        temp_reg &= ~BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_VHF_MASK;
        REG(BCHP_UFE_AFE_TNR0_PWRUP_01) = temp_reg;
        /* turn off THD clocks */
        REG(BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE) = 0;
        /* set m2mc to lowest rate */
        REG(BCHP_CLKGEN_INTERNAL_MUX_SELECT) = 0;
}

/* 
 * Description:
 * when waking up, turn on Green LED. It's been called only when CONFIG_STANDBY is enabled
 */
void turn_on_led(void)
{
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_AON_CTRL_PM_LED_CTRL) = BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK;
}


void AOV_turn_on_led(void)
{
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_GIO_AON_DATA_LO) = 0x200;               /* set LED to green AON_GPIO_09 */
        *(volatile unsigned long *)PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_GIO_AON_IODIR_LO) = 0xFFFFFDEF;
}