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bhab_3461_bbsi.h

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2005-2011, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bhab_3461_bbsi.h $
11	* $brcm_Revision: Hydra_Software_Devel/1 $
12	* $brcm_Date: 3/16/11 3:33p $
13	*
14	* [File Description:]
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/basemodules/hab/3461/bhab_3461_bbsi.h $
19	*
20	* Hydra_Software_Devel/1 3/16/11 3:33p atanugul
21	* SW3461-3: Add support for BCM3461
22	*
23	*
24	***************************************************************************/
25
26	#ifndef HOST_SERIAL_INTERFACE_H__
27	#define HOST_SERIAL_INTERFACE_H__
28
29	/**
30	* m = memory, c = core, r = register, f = field, d = data.
31	*/
32	#if !defined(GET_FIELD) && !defined(SET_FIELD)
33	#define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN
34	#define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS
35	#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
36	#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
37
38	#define GET_FIELD(m,c,r,f) \
39	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))
40
41	#define SET_FIELD(m,c,r,f,d) \
42	((m) = (((m) & ~BRCM_MASK(c,r,f)) \| ((((d) >> BRCM_ALIGN(c,r,f)) << \
43	BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
44	)
45
46	#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
47	#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
48	#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
49
50	#endif /* GET & SET */
51
52	/***************************************************************************
53	*CSR - BBSI Control & Status Registers
54	***************************************************************************/
55	#define CSR_SER_PROT_REV 0x00 /* Serial protocol revision ID */
56	#define CSR_CHIP_FAM0 0x01 /* Bits [15:08] of the 16-bit chip family ID */
57	#define CSR_CHIP_FAM1 0x02 /* Bits [07:00] of the 16-bit chip family ID */
58	#define CSR_CHIP_REV0 0x03 /* Bits [15:08] of the 16-bit chip revision ID */
59	#define CSR_CHIP_REV1 0x04 /* Bits [07:00] of the 16-bit chip revision ID */
60	#define CSR_STATUS 0x05 /* Status register of the serial interface */
61	#define CSR_CONFIG 0x06 /* Configuration register of the serial interface */
62	#define CSR_RBUS_ADDR0 0x08 /* Bits [31:24] of the 32-bit RBUS address */
63	#define CSR_RBUS_ADDR1 0x09 /* Bits [23:16] of the 32-bit RBUS address */
64	#define CSR_RBUS_ADDR2 0x0a /* Bits [15:08] of the 32-bit RBUS address */
65	#define CSR_RBUS_ADDR3 0x0b /* Bits [07:00] of the 32-bit RBUS address */
66	#define CSR_RBUS_DATA0 0x0c /* Bits [31:24] of the 32-bit RBUS data */
67	#define CSR_RBUS_DATA1 0x0d /* Bits [23:16] of the 32-bit RBUS data */
68	#define CSR_RBUS_DATA2 0x0e /* Bits [15:08] of the 32-bit RBUS data */
69	#define CSR_RBUS_DATA3 0x0f /* Bits [07:00] of the 32-bit RBUS data */
70
71	/***************************************************************************
72	*HIF - BBSI Host Interface Registers
73	***************************************************************************/
74	#define HIF_SFT_RST 0x40 /* Software Reset Control Register */
75	#define HIF_SFT_RST_CFG 0x41 /* Soft Reset Configuration Control Register */
76	#define HIF_PWRDN 0x42 /* Power Down Control Register */
77	#define HIF_MEM_CTRL 0x43 /* Memory Power Control Register */
78	#define HIF_OSC_LDO_CTRL 0x44 /* XTAL Oscillator LDO Control */
79	#define HIF_OSC_BIAS_CTRL 0x45 /* XTAL Oscillator Bias Control */
80	#define HIF_OSC_CML_CTRL 0x46 /* XTAL Oscillator CML Control */
81	#define HIF_OSC_MISC_CTRL 0x47 /* XTAL Oscillator Bias Control */
82	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS 0x48 /* XTAL Oscillator Stap Override Control for xcore_bias */
83	#define HIF_OSC_STRAP_OVRD_HIGHPASS 0x49 /* XTAL Oscillator Stap Override Control for highpass */
84	#define HIF_REG_PLL_RST 0x4a /* Register PLL Reset Control */
85	#define HIF_REG_PLL_PDIV 0x4b /* Register PLL PDIV Divider Control */
86	#define HIF_REG_PLL_NDIV_INT 0x4c /* Register PLL NDIV_INT Divider Control */
87	#define HIF_REG_PLL_MDIV_CLK_108 0x4d /* Register PLL 108 MHz Clock Divider Control */
88	#define HIF_REG_PLL_MDIV_CLK_054 0x4e /* Register PLL 54 MHz Clock Divider Control */
89	#define HIF_REG_PLL_MDEL_CLK_108 0x4f /* Register PLL Output Delay Control */
90	#define HIF_REG_PLL_MDEL_CLK_054 0x50 /* Register PLL Output Delay Control */
91	#define HIF_REG_PLL_MISC_CLK_108 0x51 /* Register PLL 108 MHz Clock Miscellaneous Control */
92	#define HIF_REG_PLL_MISC_CLK_054 0x52 /* Register PLL 54 MHz Clock Miscellaneous Control */
93	#define HIF_REG_PLL_GAIN_KA 0x53 /* Register PLL Ka Gain Control */
94	#define HIF_REG_PLL_GAIN_KI 0x54 /* Register PLL Ki Gain Control */
95	#define HIF_REG_PLL_GAIN_KP 0x55 /* Register PLL Kp Gain Control */
96	#define HIF_REG_PLL_DCO_BYP_EN 0x56 /* Register PLL DCO Bypass Enable Control */
97	#define HIF_REG_PLL_DCO_CTRL1 0x57 /* Register PLL DCO Control */
98	#define HIF_REG_PLL_DCO_CTRL0 0x58 /* Register PLL DCO Control */
99	#define HIF_REG_PLL_FB_EN 0x59 /* Register PLL Feedback Enable Control */
100	#define HIF_REG_PLL_FB_OFFSET1 0x5a /* Register PLL Feedback Offset Control */
101	#define HIF_REG_PLL_FB_OFFSET0 0x5b /* Register PLL Feedback Offset Control */
102	#define HIF_REG_PLL_SS_CTRL 0x5c /* System PLL Spread Spectrum Control */
103	#define HIF_REG_PLL_SS_STEP1 0x5d /* System PLL Spread Spectrum Step Size Control */
104	#define HIF_REG_PLL_SS_STEP0 0x5e /* System PLL Spread Spectrum Step Size Control */
105	#define HIF_REG_PLL_SS_LIMIT3 0x5f /* System PLL Spread Spectrum Limit Control */
106	#define HIF_REG_PLL_SS_LIMIT2 0x60 /* System PLL Spread Spectrum Limit Control */
107	#define HIF_REG_PLL_SS_LIMIT1 0x61 /* System PLL Spread Spectrum Limit Control */
108	#define HIF_REG_PLL_SS_LIMIT0 0x62 /* System PLL Spread Spectrum Limit Control */
109	#define HIF_REG_PLL_MISC_CTRL1 0x63 /* Register PLL Miscellaneous Control */
110	#define HIF_REG_PLL_MISC_CTRL0 0x64 /* Register PLL Miscellaneous Control */
111	#define HIF_REG_PLL_STAT_CTRL 0x65 /* Register PLL Status Control */
112	#define HIF_REG_PLL_STATUS2 0x66 /* Register PLL Status */
113	#define HIF_REG_PLL_STATUS1 0x67 /* Register PLL Status */
114	#define HIF_REG_PLL_STATUS0 0x68 /* Register PLL Status */
115	#define HIF_REG_CLK_EN 0x69 /* Register Clock Enable */
116	#define HIF_SYS_CLK_EN 0x6a /* System Clock Enable */
117	#define HIF_MISC_CTRL 0x6b /* Miscellaneous Control */
118	#define HIF_SPARE3 0x78 /* Spare Register */
119	#define HIF_SPARE2 0x79 /* Spare Register */
120	#define HIF_SPARE1 0x7a /* Spare Register */
121	#define HIF_SPARE0 0x7b /* Spare Register */
122	#define HIF_SFT3 0x7c /* Software Register */
123	#define HIF_SFT2 0x7d /* Software Register */
124	#define HIF_SFT1 0x7e /* Software Register */
125	#define HIF_SFT0 0x7f /* Software Register */
126
127	/***************************************************************************
128	*SER_PROT_REV - Serial protocol revision ID
129	***************************************************************************/
130	/* CSR :: SER_PROT_REV :: SER_PROT_REV [07:00] */
131	#define CSR_SER_PROT_REV_SER_PROT_REV_MASK 0xff
132	#define CSR_SER_PROT_REV_SER_PROT_REV_ALIGN 0
133	#define CSR_SER_PROT_REV_SER_PROT_REV_BITS 8
134	#define CSR_SER_PROT_REV_SER_PROT_REV_SHIFT 0
135
136	/***************************************************************************
137	*CHIP_FAM0 - Bits [15:08] of the 16-bit chip family ID
138	***************************************************************************/
139	/* CSR :: CHIP_FAM0 :: CHIP_FAMILY [07:00] */
140	#define CSR_CHIP_FAM0_CHIP_FAMILY_MASK 0xff
141	#define CSR_CHIP_FAM0_CHIP_FAMILY_ALIGN 0
142	#define CSR_CHIP_FAM0_CHIP_FAMILY_BITS 8
143	#define CSR_CHIP_FAM0_CHIP_FAMILY_SHIFT 0
144
145	/***************************************************************************
146	*CHIP_FAM1 - Bits [07:00] of the 16-bit chip family ID
147	***************************************************************************/
148	/* CSR :: CHIP_FAM1 :: CHIP_FAMILY [07:00] */
149	#define CSR_CHIP_FAM1_CHIP_FAMILY_MASK 0xff
150	#define CSR_CHIP_FAM1_CHIP_FAMILY_ALIGN 0
151	#define CSR_CHIP_FAM1_CHIP_FAMILY_BITS 8
152	#define CSR_CHIP_FAM1_CHIP_FAMILY_SHIFT 0
153
154	/***************************************************************************
155	*CHIP_REV0 - Bits [15:08] of the 16-bit chip revision ID
156	***************************************************************************/
157	/* CSR :: CHIP_REV0 :: CHIP_REV [07:00] */
158	#define CSR_CHIP_REV0_CHIP_REV_MASK 0xff
159	#define CSR_CHIP_REV0_CHIP_REV_ALIGN 0
160	#define CSR_CHIP_REV0_CHIP_REV_BITS 8
161	#define CSR_CHIP_REV0_CHIP_REV_SHIFT 0
162
163	/***************************************************************************
164	*CHIP_REV1 - Bits [07:00] of the 16-bit chip revision ID
165	***************************************************************************/
166	/* CSR :: CHIP_REV1 :: CHIP_REV [07:00] */
167	#define CSR_CHIP_REV1_CHIP_REV_MASK 0xff
168	#define CSR_CHIP_REV1_CHIP_REV_ALIGN 0
169	#define CSR_CHIP_REV1_CHIP_REV_BITS 8
170	#define CSR_CHIP_REV1_CHIP_REV_SHIFT 0
171
172	/***************************************************************************
173	*STATUS - Status register of the serial interface
174	***************************************************************************/
175	/* CSR :: STATUS :: reserved0 [07:07] */
176	#define CSR_STATUS_reserved0_MASK 0x80
177	#define CSR_STATUS_reserved0_ALIGN 0
178	#define CSR_STATUS_reserved0_BITS 1
179	#define CSR_STATUS_reserved0_SHIFT 7
180
181	/* CSR :: STATUS :: CPU_RUNNING [06:06] */
182	#define CSR_STATUS_CPU_RUNNING_MASK 0x40
183	#define CSR_STATUS_CPU_RUNNING_ALIGN 0
184	#define CSR_STATUS_CPU_RUNNING_BITS 1
185	#define CSR_STATUS_CPU_RUNNING_SHIFT 6
186
187	/* CSR :: STATUS :: HAB_REQ [05:05] */
188	#define CSR_STATUS_HAB_REQ_MASK 0x20
189	#define CSR_STATUS_HAB_REQ_ALIGN 0
190	#define CSR_STATUS_HAB_REQ_BITS 1
191	#define CSR_STATUS_HAB_REQ_SHIFT 5
192
193	/* CSR :: STATUS :: BUSY [04:04] */
194	#define CSR_STATUS_BUSY_MASK 0x10
195	#define CSR_STATUS_BUSY_ALIGN 0
196	#define CSR_STATUS_BUSY_BITS 1
197	#define CSR_STATUS_BUSY_SHIFT 4
198
199	/* CSR :: STATUS :: RBUS_UNEXP_TX [03:03] */
200	#define CSR_STATUS_RBUS_UNEXP_TX_MASK 0x08
201	#define CSR_STATUS_RBUS_UNEXP_TX_ALIGN 0
202	#define CSR_STATUS_RBUS_UNEXP_TX_BITS 1
203	#define CSR_STATUS_RBUS_UNEXP_TX_SHIFT 3
204
205	/* CSR :: STATUS :: RBUS_TIMEOUT [02:02] */
206	#define CSR_STATUS_RBUS_TIMEOUT_MASK 0x04
207	#define CSR_STATUS_RBUS_TIMEOUT_ALIGN 0
208	#define CSR_STATUS_RBUS_TIMEOUT_BITS 1
209	#define CSR_STATUS_RBUS_TIMEOUT_SHIFT 2
210
211	/* CSR :: STATUS :: RBUS_ERR_ACK [01:01] */
212	#define CSR_STATUS_RBUS_ERR_ACK_MASK 0x02
213	#define CSR_STATUS_RBUS_ERR_ACK_ALIGN 0
214	#define CSR_STATUS_RBUS_ERR_ACK_BITS 1
215	#define CSR_STATUS_RBUS_ERR_ACK_SHIFT 1
216
217	/* CSR :: STATUS :: ERROR [00:00] */
218	#define CSR_STATUS_ERROR_MASK 0x01
219	#define CSR_STATUS_ERROR_ALIGN 0
220	#define CSR_STATUS_ERROR_BITS 1
221	#define CSR_STATUS_ERROR_SHIFT 0
222
223	/***************************************************************************
224	*CONFIG - Configuration register of the serial interface
225	***************************************************************************/
226	/* CSR :: CONFIG :: reserved0 [07:05] */
227	#define CSR_CONFIG_reserved0_MASK 0xe0
228	#define CSR_CONFIG_reserved0_ALIGN 0
229	#define CSR_CONFIG_reserved0_BITS 3
230	#define CSR_CONFIG_reserved0_SHIFT 5
231
232	/* CSR :: CONFIG :: TRANSFER_MODE [04:03] */
233	#define CSR_CONFIG_TRANSFER_MODE_MASK 0x18
234	#define CSR_CONFIG_TRANSFER_MODE_8BIT 3
235	#define CSR_CONFIG_TRANSFER_MODE_16BIT 2
236	#define CSR_CONFIG_TRANSFER_MODE_24BIT 1
237	#define CSR_CONFIG_TRANSFER_MODE_32BIT 0
238	#define CSR_CONFIG_TRANSFER_MODE_ALIGN 0
239	#define CSR_CONFIG_TRANSFER_MODE_BITS 2
240	#define CSR_CONFIG_TRANSFER_MODE_SHIFT 3
241
242	/* CSR :: CONFIG :: NO_RBUS_ADDR_INC [02:02] */
243	#define CSR_CONFIG_NO_RBUS_ADDR_INC_MASK 0x04
244	#define CSR_CONFIG_NO_RBUS_ADDR_INC_ALIGN 0
245	#define CSR_CONFIG_NO_RBUS_ADDR_INC_BITS 1
246	#define CSR_CONFIG_NO_RBUS_ADDR_INC_SHIFT 2
247
248	/* CSR :: CONFIG :: SPECULATIVE_READ_EN [01:01] */
249	#define CSR_CONFIG_SPECULATIVE_READ_EN_MASK 0x02
250	#define CSR_CONFIG_SPECULATIVE_READ_EN_ALIGN 0
251	#define CSR_CONFIG_SPECULATIVE_READ_EN_BITS 1
252	#define CSR_CONFIG_SPECULATIVE_READ_EN_SHIFT 1
253
254	/* CSR :: CONFIG :: READ_RBUS [00:00] */
255	#define CSR_CONFIG_READ_RBUS_MASK 0x01
256	#define CSR_CONFIG_READ_RBUS_READ 0x01
257	#define CSR_CONFIG_READ_RBUS_WRITE 0x00
258	#define CSR_CONFIG_READ_RBUS_ALIGN 0
259	#define CSR_CONFIG_READ_RBUS_BITS 1
260	#define CSR_CONFIG_READ_RBUS_SHIFT 0
261
262	/***************************************************************************
263	*RBUS_ADDR0 - Bits [31:24] of the 32-bit RBUS address
264	***************************************************************************/
265	/* CSR :: RBUS_ADDR0 :: RBUS_ADDR0 [07:00] */
266	#define CSR_RBUS_ADDR0_RBUS_ADDR0_MASK 0xff
267	#define CSR_RBUS_ADDR0_RBUS_ADDR0_ALIGN 0
268	#define CSR_RBUS_ADDR0_RBUS_ADDR0_BITS 8
269	#define CSR_RBUS_ADDR0_RBUS_ADDR0_SHIFT 0
270
271	/***************************************************************************
272	*RBUS_ADDR1 - Bits [23:16] of the 32-bit RBUS address
273	***************************************************************************/
274	/* CSR :: RBUS_ADDR1 :: RBUS_ADDR1 [07:00] */
275	#define CSR_RBUS_ADDR1_RBUS_ADDR1_MASK 0xff
276	#define CSR_RBUS_ADDR1_RBUS_ADDR1_ALIGN 0
277	#define CSR_RBUS_ADDR1_RBUS_ADDR1_BITS 8
278	#define CSR_RBUS_ADDR1_RBUS_ADDR1_SHIFT 0
279
280	/***************************************************************************
281	*RBUS_ADDR2 - Bits [15:08] of the 32-bit RBUS address
282	***************************************************************************/
283	/* CSR :: RBUS_ADDR2 :: RBUS_ADDR2 [07:00] */
284	#define CSR_RBUS_ADDR2_RBUS_ADDR2_MASK 0xff
285	#define CSR_RBUS_ADDR2_RBUS_ADDR2_ALIGN 0
286	#define CSR_RBUS_ADDR2_RBUS_ADDR2_BITS 8
287	#define CSR_RBUS_ADDR2_RBUS_ADDR2_SHIFT 0
288
289	/***************************************************************************
290	*RBUS_ADDR3 - Bits [07:00] of the 32-bit RBUS address
291	***************************************************************************/
292	/* CSR :: RBUS_ADDR3 :: RBUS_ADDR3 [07:00] */
293	#define CSR_RBUS_ADDR3_RBUS_ADDR3_MASK 0xff
294	#define CSR_RBUS_ADDR3_RBUS_ADDR3_ALIGN 0
295	#define CSR_RBUS_ADDR3_RBUS_ADDR3_BITS 8
296	#define CSR_RBUS_ADDR3_RBUS_ADDR3_SHIFT 0
297
298	/***************************************************************************
299	*RBUS_DATA0 - Bits [31:24] of the 32-bit RBUS data
300	***************************************************************************/
301	/* CSR :: RBUS_DATA0 :: RBUS_DATA0 [07:00] */
302	#define CSR_RBUS_DATA0_RBUS_DATA0_MASK 0xff
303	#define CSR_RBUS_DATA0_RBUS_DATA0_ALIGN 0
304	#define CSR_RBUS_DATA0_RBUS_DATA0_BITS 8
305	#define CSR_RBUS_DATA0_RBUS_DATA0_SHIFT 0
306
307	/***************************************************************************
308	*RBUS_DATA1 - Bits [23:16] of the 32-bit RBUS data
309	***************************************************************************/
310	/* CSR :: RBUS_DATA1 :: RBUS_DATA1 [07:00] */
311	#define CSR_RBUS_DATA1_RBUS_DATA1_MASK 0xff
312	#define CSR_RBUS_DATA1_RBUS_DATA1_ALIGN 0
313	#define CSR_RBUS_DATA1_RBUS_DATA1_BITS 8
314	#define CSR_RBUS_DATA1_RBUS_DATA1_SHIFT 0
315
316	/***************************************************************************
317	*RBUS_DATA2 - Bits [15:08] of the 32-bit RBUS data
318	***************************************************************************/
319	/* CSR :: RBUS_DATA2 :: RBUS_DATA2 [07:00] */
320	#define CSR_RBUS_DATA2_RBUS_DATA2_MASK 0xff
321	#define CSR_RBUS_DATA2_RBUS_DATA2_ALIGN 0
322	#define CSR_RBUS_DATA2_RBUS_DATA2_BITS 8
323	#define CSR_RBUS_DATA2_RBUS_DATA2_SHIFT 0
324
325	/***************************************************************************
326	*RBUS_DATA3 - Bits [07:00] of the 32-bit RBUS data
327	***************************************************************************/
328	/* CSR :: RBUS_DATA3 :: RBUS_DATA3 [07:00] */
329	#define CSR_RBUS_DATA3_RBUS_DATA3_MASK 0xff
330	#define CSR_RBUS_DATA3_RBUS_DATA3_ALIGN 0
331	#define CSR_RBUS_DATA3_RBUS_DATA3_BITS 8
332	#define CSR_RBUS_DATA3_RBUS_DATA3_SHIFT 0
333
334	/***************************************************************************
335	*SFT_RST - Software Reset Control Register
336	***************************************************************************/
337	/* HIF :: SFT_RST :: RSVD [07:06] */
338	#define HIF_SFT_RST_RSVD_MASK 0xc0
339	#define HIF_SFT_RST_RSVD_ALIGN 0
340	#define HIF_SFT_RST_RSVD_BITS 2
341	#define HIF_SFT_RST_RSVD_SHIFT 6
342
343	/* HIF :: SFT_RST :: DS_TOPB [05:05] */
344	#define HIF_SFT_RST_DS_TOPB_MASK 0x20
345	#define HIF_SFT_RST_DS_TOPB_ALIGN 0
346	#define HIF_SFT_RST_DS_TOPB_BITS 1
347	#define HIF_SFT_RST_DS_TOPB_SHIFT 5
348
349	/* HIF :: SFT_RST :: DS_TOPA [04:04] */
350	#define HIF_SFT_RST_DS_TOPA_MASK 0x10
351	#define HIF_SFT_RST_DS_TOPA_ALIGN 0
352	#define HIF_SFT_RST_DS_TOPA_BITS 1
353	#define HIF_SFT_RST_DS_TOPA_SHIFT 4
354
355	/* HIF :: SFT_RST :: WFE [03:03] */
356	#define HIF_SFT_RST_WFE_MASK 0x08
357	#define HIF_SFT_RST_WFE_ALIGN 0
358	#define HIF_SFT_RST_WFE_BITS 1
359	#define HIF_SFT_RST_WFE_SHIFT 3
360
361	/* HIF :: SFT_RST :: CG [02:02] */
362	#define HIF_SFT_RST_CG_MASK 0x04
363	#define HIF_SFT_RST_CG_ALIGN 0
364	#define HIF_SFT_RST_CG_BITS 1
365	#define HIF_SFT_RST_CG_SHIFT 2
366
367	/* HIF :: SFT_RST :: PERIPH [01:01] */
368	#define HIF_SFT_RST_PERIPH_MASK 0x02
369	#define HIF_SFT_RST_PERIPH_ALIGN 0
370	#define HIF_SFT_RST_PERIPH_BITS 1
371	#define HIF_SFT_RST_PERIPH_SHIFT 1
372
373	/* HIF :: SFT_RST :: LEAP [00:00] */
374	#define HIF_SFT_RST_LEAP_MASK 0x01
375	#define HIF_SFT_RST_LEAP_ALIGN 0
376	#define HIF_SFT_RST_LEAP_BITS 1
377	#define HIF_SFT_RST_LEAP_SHIFT 0
378
379	/***************************************************************************
380	*SFT_RST_CFG - Soft Reset Configuration Control Register
381	***************************************************************************/
382	/* HIF :: SFT_RST_CFG :: RSVD [07:06] */
383	#define HIF_SFT_RST_CFG_RSVD_MASK 0xc0
384	#define HIF_SFT_RST_CFG_RSVD_ALIGN 0
385	#define HIF_SFT_RST_CFG_RSVD_BITS 2
386	#define HIF_SFT_RST_CFG_RSVD_SHIFT 6
387
388	/* HIF :: SFT_RST_CFG :: DS_TOPB [05:05] */
389	#define HIF_SFT_RST_CFG_DS_TOPB_MASK 0x20
390	#define HIF_SFT_RST_CFG_DS_TOPB_ALIGN 0
391	#define HIF_SFT_RST_CFG_DS_TOPB_BITS 1
392	#define HIF_SFT_RST_CFG_DS_TOPB_SHIFT 5
393
394	/* HIF :: SFT_RST_CFG :: DS_TOPA [04:04] */
395	#define HIF_SFT_RST_CFG_DS_TOPA_MASK 0x10
396	#define HIF_SFT_RST_CFG_DS_TOPA_ALIGN 0
397	#define HIF_SFT_RST_CFG_DS_TOPA_BITS 1
398	#define HIF_SFT_RST_CFG_DS_TOPA_SHIFT 4
399
400	/* HIF :: SFT_RST_CFG :: WFE [03:03] */
401	#define HIF_SFT_RST_CFG_WFE_MASK 0x08
402	#define HIF_SFT_RST_CFG_WFE_ALIGN 0
403	#define HIF_SFT_RST_CFG_WFE_BITS 1
404	#define HIF_SFT_RST_CFG_WFE_SHIFT 3
405
406	/* HIF :: SFT_RST_CFG :: CG [02:02] */
407	#define HIF_SFT_RST_CFG_CG_MASK 0x04
408	#define HIF_SFT_RST_CFG_CG_ALIGN 0
409	#define HIF_SFT_RST_CFG_CG_BITS 1
410	#define HIF_SFT_RST_CFG_CG_SHIFT 2
411
412	/* HIF :: SFT_RST_CFG :: PERIPH [01:01] */
413	#define HIF_SFT_RST_CFG_PERIPH_MASK 0x02
414	#define HIF_SFT_RST_CFG_PERIPH_ALIGN 0
415	#define HIF_SFT_RST_CFG_PERIPH_BITS 1
416	#define HIF_SFT_RST_CFG_PERIPH_SHIFT 1
417
418	/* HIF :: SFT_RST_CFG :: LEAP [00:00] */
419	#define HIF_SFT_RST_CFG_LEAP_MASK 0x01
420	#define HIF_SFT_RST_CFG_LEAP_ALIGN 0
421	#define HIF_SFT_RST_CFG_LEAP_BITS 1
422	#define HIF_SFT_RST_CFG_LEAP_SHIFT 0
423
424	/***************************************************************************
425	*PWRDN - Power Down Control Register
426	***************************************************************************/
427	/* HIF :: PWRDN :: PWRDN_07 [07:07] */
428	#define HIF_PWRDN_PWRDN_07_MASK 0x80
429	#define HIF_PWRDN_PWRDN_07_ALIGN 0
430	#define HIF_PWRDN_PWRDN_07_BITS 1
431	#define HIF_PWRDN_PWRDN_07_SHIFT 7
432
433	/* HIF :: PWRDN :: PWRDN_06 [06:06] */
434	#define HIF_PWRDN_PWRDN_06_MASK 0x40
435	#define HIF_PWRDN_PWRDN_06_ALIGN 0
436	#define HIF_PWRDN_PWRDN_06_BITS 1
437	#define HIF_PWRDN_PWRDN_06_SHIFT 6
438
439	/* HIF :: PWRDN :: PWRDN_05 [05:05] */
440	#define HIF_PWRDN_PWRDN_05_MASK 0x20
441	#define HIF_PWRDN_PWRDN_05_ALIGN 0
442	#define HIF_PWRDN_PWRDN_05_BITS 1
443	#define HIF_PWRDN_PWRDN_05_SHIFT 5
444
445	/* HIF :: PWRDN :: PWRDN_04 [04:04] */
446	#define HIF_PWRDN_PWRDN_04_MASK 0x10
447	#define HIF_PWRDN_PWRDN_04_ALIGN 0
448	#define HIF_PWRDN_PWRDN_04_BITS 1
449	#define HIF_PWRDN_PWRDN_04_SHIFT 4
450
451	/* HIF :: PWRDN :: PWRDN_03 [03:03] */
452	#define HIF_PWRDN_PWRDN_03_MASK 0x08
453	#define HIF_PWRDN_PWRDN_03_ALIGN 0
454	#define HIF_PWRDN_PWRDN_03_BITS 1
455	#define HIF_PWRDN_PWRDN_03_SHIFT 3
456
457	/* HIF :: PWRDN :: OSC_LDO [02:02] */
458	#define HIF_PWRDN_OSC_LDO_MASK 0x04
459	#define HIF_PWRDN_OSC_LDO_ALIGN 0
460	#define HIF_PWRDN_OSC_LDO_BITS 1
461	#define HIF_PWRDN_OSC_LDO_SHIFT 2
462
463	/* HIF :: PWRDN :: OSC_XTAL [01:01] */
464	#define HIF_PWRDN_OSC_XTAL_MASK 0x02
465	#define HIF_PWRDN_OSC_XTAL_ALIGN 0
466	#define HIF_PWRDN_OSC_XTAL_BITS 1
467	#define HIF_PWRDN_OSC_XTAL_SHIFT 1
468
469	/* HIF :: PWRDN :: REG_PLL [00:00] */
470	#define HIF_PWRDN_REG_PLL_MASK 0x01
471	#define HIF_PWRDN_REG_PLL_ALIGN 0
472	#define HIF_PWRDN_REG_PLL_BITS 1
473	#define HIF_PWRDN_REG_PLL_SHIFT 0
474
475	/***************************************************************************
476	*MEM_CTRL - Memory Power Control Register
477	***************************************************************************/
478	/* HIF :: MEM_CTRL :: RSVD [07:04] */
479	#define HIF_MEM_CTRL_RSVD_MASK 0xf0
480	#define HIF_MEM_CTRL_RSVD_ALIGN 0
481	#define HIF_MEM_CTRL_RSVD_BITS 4
482	#define HIF_MEM_CTRL_RSVD_SHIFT 4
483
484	/* HIF :: MEM_CTRL :: ROM_STBY_LEAP [03:03] */
485	#define HIF_MEM_CTRL_ROM_STBY_LEAP_MASK 0x08
486	#define HIF_MEM_CTRL_ROM_STBY_LEAP_ALIGN 0
487	#define HIF_MEM_CTRL_ROM_STBY_LEAP_BITS 1
488	#define HIF_MEM_CTRL_ROM_STBY_LEAP_SHIFT 3
489
490	/* HIF :: MEM_CTRL :: RAM_STBY_LEAP [02:02] */
491	#define HIF_MEM_CTRL_RAM_STBY_LEAP_MASK 0x04
492	#define HIF_MEM_CTRL_RAM_STBY_LEAP_ALIGN 0
493	#define HIF_MEM_CTRL_RAM_STBY_LEAP_BITS 1
494	#define HIF_MEM_CTRL_RAM_STBY_LEAP_SHIFT 2
495
496	/* HIF :: MEM_CTRL :: PSM_LEAP [01:00] */
497	#define HIF_MEM_CTRL_PSM_LEAP_MASK 0x03
498	#define HIF_MEM_CTRL_PSM_LEAP_ALIGN 0
499	#define HIF_MEM_CTRL_PSM_LEAP_BITS 2
500	#define HIF_MEM_CTRL_PSM_LEAP_SHIFT 0
501
502	/***************************************************************************
503	*OSC_LDO_CTRL - XTAL Oscillator LDO Control
504	***************************************************************************/
505	/* HIF :: OSC_LDO_CTRL :: RSVD [07:02] */
506	#define HIF_OSC_LDO_CTRL_RSVD_MASK 0xfc
507	#define HIF_OSC_LDO_CTRL_RSVD_ALIGN 0
508	#define HIF_OSC_LDO_CTRL_RSVD_BITS 6
509	#define HIF_OSC_LDO_CTRL_RSVD_SHIFT 2
510
511	/* HIF :: OSC_LDO_CTRL :: OUTPUT [01:00] */
512	#define HIF_OSC_LDO_CTRL_OUTPUT_MASK 0x03
513	#define HIF_OSC_LDO_CTRL_OUTPUT_ALIGN 0
514	#define HIF_OSC_LDO_CTRL_OUTPUT_BITS 2
515	#define HIF_OSC_LDO_CTRL_OUTPUT_SHIFT 0
516
517	/***************************************************************************
518	*OSC_BIAS_CTRL - XTAL Oscillator Bias Control
519	***************************************************************************/
520	/* HIF :: OSC_BIAS_CTRL :: RSVD_1 [07:07] */
521	#define HIF_OSC_BIAS_CTRL_RSVD_1_MASK 0x80
522	#define HIF_OSC_BIAS_CTRL_RSVD_1_ALIGN 0
523	#define HIF_OSC_BIAS_CTRL_RSVD_1_BITS 1
524	#define HIF_OSC_BIAS_CTRL_RSVD_1_SHIFT 7
525
526	/* HIF :: OSC_BIAS_CTRL :: D2C [06:04] */
527	#define HIF_OSC_BIAS_CTRL_D2C_MASK 0x70
528	#define HIF_OSC_BIAS_CTRL_D2C_ALIGN 0
529	#define HIF_OSC_BIAS_CTRL_D2C_BITS 3
530	#define HIF_OSC_BIAS_CTRL_D2C_SHIFT 4
531
532	/* HIF :: OSC_BIAS_CTRL :: RSVD_0 [03:03] */
533	#define HIF_OSC_BIAS_CTRL_RSVD_0_MASK 0x08
534	#define HIF_OSC_BIAS_CTRL_RSVD_0_ALIGN 0
535	#define HIF_OSC_BIAS_CTRL_RSVD_0_BITS 1
536	#define HIF_OSC_BIAS_CTRL_RSVD_0_SHIFT 3
537
538	/* HIF :: OSC_BIAS_CTRL :: MASTER [02:00] */
539	#define HIF_OSC_BIAS_CTRL_MASTER_MASK 0x07
540	#define HIF_OSC_BIAS_CTRL_MASTER_ALIGN 0
541	#define HIF_OSC_BIAS_CTRL_MASTER_BITS 3
542	#define HIF_OSC_BIAS_CTRL_MASTER_SHIFT 0
543
544	/***************************************************************************
545	*OSC_CML_CTRL - XTAL Oscillator CML Control
546	***************************************************************************/
547	/* HIF :: OSC_CML_CTRL :: RSVD_1 [07:05] */
548	#define HIF_OSC_CML_CTRL_RSVD_1_MASK 0xe0
549	#define HIF_OSC_CML_CTRL_RSVD_1_ALIGN 0
550	#define HIF_OSC_CML_CTRL_RSVD_1_BITS 3
551	#define HIF_OSC_CML_CTRL_RSVD_1_SHIFT 5
552
553	/* HIF :: OSC_CML_CTRL :: CUR [04:04] */
554	#define HIF_OSC_CML_CTRL_CUR_MASK 0x10
555	#define HIF_OSC_CML_CTRL_CUR_ALIGN 0
556	#define HIF_OSC_CML_CTRL_CUR_BITS 1
557	#define HIF_OSC_CML_CTRL_CUR_SHIFT 4
558
559	/* HIF :: OSC_CML_CTRL :: RSVD_0 [03:02] */
560	#define HIF_OSC_CML_CTRL_RSVD_0_MASK 0x0c
561	#define HIF_OSC_CML_CTRL_RSVD_0_ALIGN 0
562	#define HIF_OSC_CML_CTRL_RSVD_0_BITS 2
563	#define HIF_OSC_CML_CTRL_RSVD_0_SHIFT 2
564
565	/* HIF :: OSC_CML_CTRL :: DRIVE [01:00] */
566	#define HIF_OSC_CML_CTRL_DRIVE_MASK 0x03
567	#define HIF_OSC_CML_CTRL_DRIVE_ALIGN 0
568	#define HIF_OSC_CML_CTRL_DRIVE_BITS 2
569	#define HIF_OSC_CML_CTRL_DRIVE_SHIFT 0
570
571	/***************************************************************************
572	*OSC_MISC_CTRL - XTAL Oscillator Bias Control
573	***************************************************************************/
574	/* HIF :: OSC_MISC_CTRL :: RSVD_0 [07:01] */
575	#define HIF_OSC_MISC_CTRL_RSVD_0_MASK 0xfe
576	#define HIF_OSC_MISC_CTRL_RSVD_0_ALIGN 0
577	#define HIF_OSC_MISC_CTRL_RSVD_0_BITS 7
578	#define HIF_OSC_MISC_CTRL_RSVD_0_SHIFT 1
579
580	/* HIF :: OSC_MISC_CTRL :: LPG [00:00] */
581	#define HIF_OSC_MISC_CTRL_LPG_MASK 0x01
582	#define HIF_OSC_MISC_CTRL_LPG_ALIGN 0
583	#define HIF_OSC_MISC_CTRL_LPG_BITS 1
584	#define HIF_OSC_MISC_CTRL_LPG_SHIFT 0
585
586	/***************************************************************************
587	*OSC_STRAP_OVRD_XCORE_BIAS - XTAL Oscillator Stap Override Control for xcore_bias
588	***************************************************************************/
589	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: RSVD_0 [07:05] */
590	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_MASK 0xe0
591	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_ALIGN 0
592	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_BITS 3
593	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_SHIFT 5
594
595	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: EN [04:04] */
596	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_MASK 0x10
597	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_ALIGN 0
598	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_BITS 1
599	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_SHIFT 4
600
601	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: VAL [03:00] */
602	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_MASK 0x0f
603	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_ALIGN 0
604	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_BITS 4
605	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_SHIFT 0
606
607	/***************************************************************************
608	*OSC_STRAP_OVRD_HIGHPASS - XTAL Oscillator Stap Override Control for highpass
609	***************************************************************************/
610	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: RSVD_1 [07:05] */
611	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_MASK 0xe0
612	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_ALIGN 0
613	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_BITS 3
614	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_SHIFT 5
615
616	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: EN [04:04] */
617	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_MASK 0x10
618	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_ALIGN 0
619	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_BITS 1
620	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_SHIFT 4
621
622	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: RSVD_0 [03:01] */
623	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_MASK 0x0e
624	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_ALIGN 0
625	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_BITS 3
626	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_SHIFT 1
627
628	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: VAL [00:00] */
629	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_MASK 0x01
630	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_ALIGN 0
631	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_BITS 1
632	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_SHIFT 0
633
634	/***************************************************************************
635	*REG_PLL_RST - Register PLL Reset Control
636	***************************************************************************/
637	/* HIF :: REG_PLL_RST :: RSVD_0 [07:02] */
638	#define HIF_REG_PLL_RST_RSVD_0_MASK 0xfc
639	#define HIF_REG_PLL_RST_RSVD_0_ALIGN 0
640	#define HIF_REG_PLL_RST_RSVD_0_BITS 6
641	#define HIF_REG_PLL_RST_RSVD_0_SHIFT 2
642
643	/* HIF :: REG_PLL_RST :: POST [01:01] */
644	#define HIF_REG_PLL_RST_POST_MASK 0x02
645	#define HIF_REG_PLL_RST_POST_ALIGN 0
646	#define HIF_REG_PLL_RST_POST_BITS 1
647	#define HIF_REG_PLL_RST_POST_SHIFT 1
648
649	/* HIF :: REG_PLL_RST :: GLOBAL [00:00] */
650	#define HIF_REG_PLL_RST_GLOBAL_MASK 0x01
651	#define HIF_REG_PLL_RST_GLOBAL_ALIGN 0
652	#define HIF_REG_PLL_RST_GLOBAL_BITS 1
653	#define HIF_REG_PLL_RST_GLOBAL_SHIFT 0
654
655	/***************************************************************************
656	*REG_PLL_PDIV - Register PLL PDIV Divider Control
657	***************************************************************************/
658	/* HIF :: REG_PLL_PDIV :: RSVD [07:04] */
659	#define HIF_REG_PLL_PDIV_RSVD_MASK 0xf0
660	#define HIF_REG_PLL_PDIV_RSVD_ALIGN 0
661	#define HIF_REG_PLL_PDIV_RSVD_BITS 4
662	#define HIF_REG_PLL_PDIV_RSVD_SHIFT 4
663
664	/* HIF :: REG_PLL_PDIV :: DIV [03:00] */
665	#define HIF_REG_PLL_PDIV_DIV_MASK 0x0f
666	#define HIF_REG_PLL_PDIV_DIV_ALIGN 0
667	#define HIF_REG_PLL_PDIV_DIV_BITS 4
668	#define HIF_REG_PLL_PDIV_DIV_SHIFT 0
669
670	/***************************************************************************
671	*REG_PLL_NDIV_INT - Register PLL NDIV_INT Divider Control
672	***************************************************************************/
673	/* HIF :: REG_PLL_NDIV_INT :: DIV [07:00] */
674	#define HIF_REG_PLL_NDIV_INT_DIV_MASK 0xff
675	#define HIF_REG_PLL_NDIV_INT_DIV_ALIGN 0
676	#define HIF_REG_PLL_NDIV_INT_DIV_BITS 8
677	#define HIF_REG_PLL_NDIV_INT_DIV_SHIFT 0
678
679	/***************************************************************************
680	*REG_PLL_MDIV_CLK_108 - Register PLL 108 MHz Clock Divider Control
681	***************************************************************************/
682	/* HIF :: REG_PLL_MDIV_CLK_108 :: DIV [07:00] */
683	#define HIF_REG_PLL_MDIV_CLK_108_DIV_MASK 0xff
684	#define HIF_REG_PLL_MDIV_CLK_108_DIV_ALIGN 0
685	#define HIF_REG_PLL_MDIV_CLK_108_DIV_BITS 8
686	#define HIF_REG_PLL_MDIV_CLK_108_DIV_SHIFT 0
687
688	/***************************************************************************
689	*REG_PLL_MDIV_CLK_054 - Register PLL 54 MHz Clock Divider Control
690	***************************************************************************/
691	/* HIF :: REG_PLL_MDIV_CLK_054 :: DIV [07:00] */
692	#define HIF_REG_PLL_MDIV_CLK_054_DIV_MASK 0xff
693	#define HIF_REG_PLL_MDIV_CLK_054_DIV_ALIGN 0
694	#define HIF_REG_PLL_MDIV_CLK_054_DIV_BITS 8
695	#define HIF_REG_PLL_MDIV_CLK_054_DIV_SHIFT 0
696
697	/***************************************************************************
698	*REG_PLL_MDEL_CLK_108 - Register PLL Output Delay Control
699	***************************************************************************/
700	/* HIF :: REG_PLL_MDEL_CLK_108 :: RSVD [07:03] */
701	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_MASK 0xf8
702	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_ALIGN 0
703	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_BITS 5
704	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_SHIFT 3
705
706	/* HIF :: REG_PLL_MDEL_CLK_108 :: DLY [02:00] */
707	#define HIF_REG_PLL_MDEL_CLK_108_DLY_MASK 0x07
708	#define HIF_REG_PLL_MDEL_CLK_108_DLY_ALIGN 0
709	#define HIF_REG_PLL_MDEL_CLK_108_DLY_BITS 3
710	#define HIF_REG_PLL_MDEL_CLK_108_DLY_SHIFT 0
711
712	/***************************************************************************
713	*REG_PLL_MDEL_CLK_054 - Register PLL Output Delay Control
714	***************************************************************************/
715	/* HIF :: REG_PLL_MDEL_CLK_054 :: RSVD [07:03] */
716	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_MASK 0xf8
717	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_ALIGN 0
718	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_BITS 5
719	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_SHIFT 3
720
721	/* HIF :: REG_PLL_MDEL_CLK_054 :: DLY [02:00] */
722	#define HIF_REG_PLL_MDEL_CLK_054_DLY_MASK 0x07
723	#define HIF_REG_PLL_MDEL_CLK_054_DLY_ALIGN 0
724	#define HIF_REG_PLL_MDEL_CLK_054_DLY_BITS 3
725	#define HIF_REG_PLL_MDEL_CLK_054_DLY_SHIFT 0
726
727	/***************************************************************************
728	*REG_PLL_MISC_CLK_108 - Register PLL 108 MHz Clock Miscellaneous Control
729	***************************************************************************/
730	/* HIF :: REG_PLL_MISC_CLK_108 :: RSVD [07:03] */
731	#define HIF_REG_PLL_MISC_CLK_108_RSVD_MASK 0xf8
732	#define HIF_REG_PLL_MISC_CLK_108_RSVD_ALIGN 0
733	#define HIF_REG_PLL_MISC_CLK_108_RSVD_BITS 5
734	#define HIF_REG_PLL_MISC_CLK_108_RSVD_SHIFT 3
735
736	/* HIF :: REG_PLL_MISC_CLK_108 :: LOAD_DIS [02:02] */
737	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_MASK 0x04
738	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_ALIGN 0
739	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_BITS 1
740	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_SHIFT 2
741
742	/* HIF :: REG_PLL_MISC_CLK_108 :: PWRUP [01:01] */
743	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_MASK 0x02
744	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_ALIGN 0
745	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_BITS 1
746	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_SHIFT 1
747
748	/* HIF :: REG_PLL_MISC_CLK_108 :: EN [00:00] */
749	#define HIF_REG_PLL_MISC_CLK_108_EN_MASK 0x01
750	#define HIF_REG_PLL_MISC_CLK_108_EN_ALIGN 0
751	#define HIF_REG_PLL_MISC_CLK_108_EN_BITS 1
752	#define HIF_REG_PLL_MISC_CLK_108_EN_SHIFT 0
753
754	/***************************************************************************
755	*REG_PLL_MISC_CLK_054 - Register PLL 54 MHz Clock Miscellaneous Control
756	***************************************************************************/
757	/* HIF :: REG_PLL_MISC_CLK_054 :: RSVD [07:03] */
758	#define HIF_REG_PLL_MISC_CLK_054_RSVD_MASK 0xf8
759	#define HIF_REG_PLL_MISC_CLK_054_RSVD_ALIGN 0
760	#define HIF_REG_PLL_MISC_CLK_054_RSVD_BITS 5
761	#define HIF_REG_PLL_MISC_CLK_054_RSVD_SHIFT 3
762
763	/* HIF :: REG_PLL_MISC_CLK_054 :: LOAD_DIS [02:02] */
764	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_MASK 0x04
765	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_ALIGN 0
766	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_BITS 1
767	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_SHIFT 2
768
769	/* HIF :: REG_PLL_MISC_CLK_054 :: PWRUP [01:01] */
770	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_MASK 0x02
771	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_ALIGN 0
772	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_BITS 1
773	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_SHIFT 1
774
775	/* HIF :: REG_PLL_MISC_CLK_054 :: EN [00:00] */
776	#define HIF_REG_PLL_MISC_CLK_054_EN_MASK 0x01
777	#define HIF_REG_PLL_MISC_CLK_054_EN_ALIGN 0
778	#define HIF_REG_PLL_MISC_CLK_054_EN_BITS 1
779	#define HIF_REG_PLL_MISC_CLK_054_EN_SHIFT 0
780
781	/***************************************************************************
782	*REG_PLL_GAIN_KA - Register PLL Ka Gain Control
783	***************************************************************************/
784	/* HIF :: REG_PLL_GAIN_KA :: RSVD [07:03] */
785	#define HIF_REG_PLL_GAIN_KA_RSVD_MASK 0xf8
786	#define HIF_REG_PLL_GAIN_KA_RSVD_ALIGN 0
787	#define HIF_REG_PLL_GAIN_KA_RSVD_BITS 5
788	#define HIF_REG_PLL_GAIN_KA_RSVD_SHIFT 3
789
790	/* HIF :: REG_PLL_GAIN_KA :: KA [02:00] */
791	#define HIF_REG_PLL_GAIN_KA_KA_MASK 0x07
792	#define HIF_REG_PLL_GAIN_KA_KA_ALIGN 0
793	#define HIF_REG_PLL_GAIN_KA_KA_BITS 3
794	#define HIF_REG_PLL_GAIN_KA_KA_SHIFT 0
795
796	/***************************************************************************
797	*REG_PLL_GAIN_KI - Register PLL Ki Gain Control
798	***************************************************************************/
799	/* HIF :: REG_PLL_GAIN_KI :: RSVD [07:03] */
800	#define HIF_REG_PLL_GAIN_KI_RSVD_MASK 0xf8
801	#define HIF_REG_PLL_GAIN_KI_RSVD_ALIGN 0
802	#define HIF_REG_PLL_GAIN_KI_RSVD_BITS 5
803	#define HIF_REG_PLL_GAIN_KI_RSVD_SHIFT 3
804
805	/* HIF :: REG_PLL_GAIN_KI :: KI [02:00] */
806	#define HIF_REG_PLL_GAIN_KI_KI_MASK 0x07
807	#define HIF_REG_PLL_GAIN_KI_KI_ALIGN 0
808	#define HIF_REG_PLL_GAIN_KI_KI_BITS 3
809	#define HIF_REG_PLL_GAIN_KI_KI_SHIFT 0
810
811	/***************************************************************************
812	*REG_PLL_GAIN_KP - Register PLL Kp Gain Control
813	***************************************************************************/
814	/* HIF :: REG_PLL_GAIN_KP :: RSVD [07:04] */
815	#define HIF_REG_PLL_GAIN_KP_RSVD_MASK 0xf0
816	#define HIF_REG_PLL_GAIN_KP_RSVD_ALIGN 0
817	#define HIF_REG_PLL_GAIN_KP_RSVD_BITS 4
818	#define HIF_REG_PLL_GAIN_KP_RSVD_SHIFT 4
819
820	/* HIF :: REG_PLL_GAIN_KP :: KP [03:00] */
821	#define HIF_REG_PLL_GAIN_KP_KP_MASK 0x0f
822	#define HIF_REG_PLL_GAIN_KP_KP_ALIGN 0
823	#define HIF_REG_PLL_GAIN_KP_KP_BITS 4
824	#define HIF_REG_PLL_GAIN_KP_KP_SHIFT 0
825
826	/***************************************************************************
827	*REG_PLL_DCO_BYP_EN - Register PLL DCO Bypass Enable Control
828	***************************************************************************/
829	/* HIF :: REG_PLL_DCO_BYP_EN :: RSVD [07:01] */
830	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_MASK 0xfe
831	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_ALIGN 0
832	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_BITS 7
833	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_SHIFT 1
834
835	/* HIF :: REG_PLL_DCO_BYP_EN :: EN [00:00] */
836	#define HIF_REG_PLL_DCO_BYP_EN_EN_MASK 0x01
837	#define HIF_REG_PLL_DCO_BYP_EN_EN_ALIGN 0
838	#define HIF_REG_PLL_DCO_BYP_EN_EN_BITS 1
839	#define HIF_REG_PLL_DCO_BYP_EN_EN_SHIFT 0
840
841	/***************************************************************************
842	*REG_PLL_DCO_CTRL1 - Register PLL DCO Control
843	***************************************************************************/
844	/* HIF :: REG_PLL_DCO_CTRL1 :: RSVD [07:04] */
845	#define HIF_REG_PLL_DCO_CTRL1_RSVD_MASK 0xf0
846	#define HIF_REG_PLL_DCO_CTRL1_RSVD_ALIGN 0
847	#define HIF_REG_PLL_DCO_CTRL1_RSVD_BITS 4
848	#define HIF_REG_PLL_DCO_CTRL1_RSVD_SHIFT 4
849
850	/* HIF :: REG_PLL_DCO_CTRL1 :: VAL [03:00] */
851	#define HIF_REG_PLL_DCO_CTRL1_VAL_MASK 0x0f
852	#define HIF_REG_PLL_DCO_CTRL1_VAL_ALIGN 0
853	#define HIF_REG_PLL_DCO_CTRL1_VAL_BITS 4
854	#define HIF_REG_PLL_DCO_CTRL1_VAL_SHIFT 0
855
856	/***************************************************************************
857	*REG_PLL_DCO_CTRL0 - Register PLL DCO Control
858	***************************************************************************/
859	/* HIF :: REG_PLL_DCO_CTRL0 :: VAL [07:00] */
860	#define HIF_REG_PLL_DCO_CTRL0_VAL_MASK 0xff
861	#define HIF_REG_PLL_DCO_CTRL0_VAL_ALIGN 0
862	#define HIF_REG_PLL_DCO_CTRL0_VAL_BITS 8
863	#define HIF_REG_PLL_DCO_CTRL0_VAL_SHIFT 0
864
865	/***************************************************************************
866	*REG_PLL_FB_EN - Register PLL Feedback Enable Control
867	***************************************************************************/
868	/* HIF :: REG_PLL_FB_EN :: RSVD [07:01] */
869	#define HIF_REG_PLL_FB_EN_RSVD_MASK 0xfe
870	#define HIF_REG_PLL_FB_EN_RSVD_ALIGN 0
871	#define HIF_REG_PLL_FB_EN_RSVD_BITS 7
872	#define HIF_REG_PLL_FB_EN_RSVD_SHIFT 1
873
874	/* HIF :: REG_PLL_FB_EN :: EN [00:00] */
875	#define HIF_REG_PLL_FB_EN_EN_MASK 0x01
876	#define HIF_REG_PLL_FB_EN_EN_ALIGN 0
877	#define HIF_REG_PLL_FB_EN_EN_BITS 1
878	#define HIF_REG_PLL_FB_EN_EN_SHIFT 0
879
880	/***************************************************************************
881	*REG_PLL_FB_OFFSET1 - Register PLL Feedback Offset Control
882	***************************************************************************/
883	/* HIF :: REG_PLL_FB_OFFSET1 :: RSVD [07:04] */
884	#define HIF_REG_PLL_FB_OFFSET1_RSVD_MASK 0xf0
885	#define HIF_REG_PLL_FB_OFFSET1_RSVD_ALIGN 0
886	#define HIF_REG_PLL_FB_OFFSET1_RSVD_BITS 4
887	#define HIF_REG_PLL_FB_OFFSET1_RSVD_SHIFT 4
888
889	/* HIF :: REG_PLL_FB_OFFSET1 :: OFFSET [03:00] */
890	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_MASK 0x0f
891	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_ALIGN 0
892	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_BITS 4
893	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_SHIFT 0
894
895	/***************************************************************************
896	*REG_PLL_FB_OFFSET0 - Register PLL Feedback Offset Control
897	***************************************************************************/
898	/* HIF :: REG_PLL_FB_OFFSET0 :: OFFSET [07:00] */
899	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_MASK 0xff
900	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_ALIGN 0
901	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_BITS 8
902	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_SHIFT 0
903
904	/***************************************************************************
905	*REG_PLL_SS_CTRL - System PLL Spread Spectrum Control
906	***************************************************************************/
907	/* HIF :: REG_PLL_SS_CTRL :: RSVD [07:01] */
908	#define HIF_REG_PLL_SS_CTRL_RSVD_MASK 0xfe
909	#define HIF_REG_PLL_SS_CTRL_RSVD_ALIGN 0
910	#define HIF_REG_PLL_SS_CTRL_RSVD_BITS 7
911	#define HIF_REG_PLL_SS_CTRL_RSVD_SHIFT 1
912
913	/* HIF :: REG_PLL_SS_CTRL :: EN [00:00] */
914	#define HIF_REG_PLL_SS_CTRL_EN_MASK 0x01
915	#define HIF_REG_PLL_SS_CTRL_EN_ALIGN 0
916	#define HIF_REG_PLL_SS_CTRL_EN_BITS 1
917	#define HIF_REG_PLL_SS_CTRL_EN_SHIFT 0
918
919	/***************************************************************************
920	*REG_PLL_SS_STEP1 - System PLL Spread Spectrum Step Size Control
921	***************************************************************************/
922	/* HIF :: REG_PLL_SS_STEP1 :: SIZE [07:00] */
923	#define HIF_REG_PLL_SS_STEP1_SIZE_MASK 0xff
924	#define HIF_REG_PLL_SS_STEP1_SIZE_ALIGN 0
925	#define HIF_REG_PLL_SS_STEP1_SIZE_BITS 8
926	#define HIF_REG_PLL_SS_STEP1_SIZE_SHIFT 0
927
928	/***************************************************************************
929	*REG_PLL_SS_STEP0 - System PLL Spread Spectrum Step Size Control
930	***************************************************************************/
931	/* HIF :: REG_PLL_SS_STEP0 :: SIZE [07:00] */
932	#define HIF_REG_PLL_SS_STEP0_SIZE_MASK 0xff
933	#define HIF_REG_PLL_SS_STEP0_SIZE_ALIGN 0
934	#define HIF_REG_PLL_SS_STEP0_SIZE_BITS 8
935	#define HIF_REG_PLL_SS_STEP0_SIZE_SHIFT 0
936
937	/***************************************************************************
938	*REG_PLL_SS_LIMIT3 - System PLL Spread Spectrum Limit Control
939	***************************************************************************/
940	/* HIF :: REG_PLL_SS_LIMIT3 :: RSVD [07:02] */
941	#define HIF_REG_PLL_SS_LIMIT3_RSVD_MASK 0xfc
942	#define HIF_REG_PLL_SS_LIMIT3_RSVD_ALIGN 0
943	#define HIF_REG_PLL_SS_LIMIT3_RSVD_BITS 6
944	#define HIF_REG_PLL_SS_LIMIT3_RSVD_SHIFT 2
945
946	/* HIF :: REG_PLL_SS_LIMIT3 :: LIMIT [01:00] */
947	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_MASK 0x03
948	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_ALIGN 0
949	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_BITS 2
950	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_SHIFT 0
951
952	/***************************************************************************
953	*REG_PLL_SS_LIMIT2 - System PLL Spread Spectrum Limit Control
954	***************************************************************************/
955	/* HIF :: REG_PLL_SS_LIMIT2 :: LIMIT [07:00] */
956	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_MASK 0xff
957	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_ALIGN 0
958	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_BITS 8
959	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_SHIFT 0
960
961	/***************************************************************************
962	*REG_PLL_SS_LIMIT1 - System PLL Spread Spectrum Limit Control
963	***************************************************************************/
964	/* HIF :: REG_PLL_SS_LIMIT1 :: LIMIT [07:00] */
965	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_MASK 0xff
966	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_ALIGN 0
967	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_BITS 8
968	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_SHIFT 0
969
970	/***************************************************************************
971	*REG_PLL_SS_LIMIT0 - System PLL Spread Spectrum Limit Control
972	***************************************************************************/
973	/* HIF :: REG_PLL_SS_LIMIT0 :: LIMIT [07:00] */
974	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_MASK 0xff
975	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_ALIGN 0
976	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_BITS 8
977	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_SHIFT 0
978
979	/***************************************************************************
980	*REG_PLL_MISC_CTRL1 - Register PLL Miscellaneous Control
981	***************************************************************************/
982	/* HIF :: REG_PLL_MISC_CTRL1 :: RSVD_1 [07:04] */
983	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_MASK 0xf0
984	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_ALIGN 0
985	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_BITS 4
986	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_SHIFT 4
987
988	/* HIF :: REG_PLL_MISC_CTRL1 :: RSVD_0 [03:02] */
989	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_MASK 0x0c
990	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_ALIGN 0
991	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_BITS 2
992	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_SHIFT 2
993
994	/* HIF :: REG_PLL_MISC_CTRL1 :: NDIV_RELOCK [01:01] */
995	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_MASK 0x02
996	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_ALIGN 0
997	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_BITS 1
998	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_SHIFT 1
999
1000	/* HIF :: REG_PLL_MISC_CTRL1 :: FAST_LOCK [00:00] */
1001	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_MASK 0x01
1002	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_ALIGN 0
1003	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_BITS 1
1004	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_SHIFT 0
1005
1006	/***************************************************************************
1007	*REG_PLL_MISC_CTRL0 - Register PLL Miscellaneous Control
1008	***************************************************************************/
1009	/* HIF :: REG_PLL_MISC_CTRL0 :: PWM_RATE [07:06] */
1010	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_MASK 0xc0
1011	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_ALIGN 0
1012	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_BITS 2
1013	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_SHIFT 6
1014
1015	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DLY [05:04] */
1016	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_MASK 0x30
1017	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_ALIGN 0
1018	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_BITS 2
1019	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_SHIFT 4
1020
1021	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DIV2 [03:03] */
1022	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_MASK 0x08
1023	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_ALIGN 0
1024	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_BITS 1
1025	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_SHIFT 3
1026
1027	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DIV2_POST [02:02] */
1028	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_MASK 0x04
1029	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_ALIGN 0
1030	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_BITS 1
1031	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_SHIFT 2
1032
1033	/* HIF :: REG_PLL_MISC_CTRL0 :: AUX [01:01] */
1034	#define HIF_REG_PLL_MISC_CTRL0_AUX_MASK 0x02
1035	#define HIF_REG_PLL_MISC_CTRL0_AUX_ALIGN 0
1036	#define HIF_REG_PLL_MISC_CTRL0_AUX_BITS 1
1037	#define HIF_REG_PLL_MISC_CTRL0_AUX_SHIFT 1
1038
1039	/* HIF :: REG_PLL_MISC_CTRL0 :: EN_REF_OUT [00:00] */
1040	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_MASK 0x01
1041	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_ALIGN 0
1042	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_BITS 1
1043	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_SHIFT 0
1044
1045	/***************************************************************************
1046	*REG_PLL_STAT_CTRL - Register PLL Status Control
1047	***************************************************************************/
1048	/* HIF :: REG_PLL_STAT_CTRL :: UPDATE [07:07] */
1049	#define HIF_REG_PLL_STAT_CTRL_UPDATE_MASK 0x80
1050	#define HIF_REG_PLL_STAT_CTRL_UPDATE_ALIGN 0
1051	#define HIF_REG_PLL_STAT_CTRL_UPDATE_BITS 1
1052	#define HIF_REG_PLL_STAT_CTRL_UPDATE_SHIFT 7
1053
1054	/* HIF :: REG_PLL_STAT_CTRL :: MODE [06:05] */
1055	#define HIF_REG_PLL_STAT_CTRL_MODE_MASK 0x60
1056	#define HIF_REG_PLL_STAT_CTRL_MODE_ALIGN 0
1057	#define HIF_REG_PLL_STAT_CTRL_MODE_BITS 2
1058	#define HIF_REG_PLL_STAT_CTRL_MODE_SHIFT 5
1059
1060	/* HIF :: REG_PLL_STAT_CTRL :: RST [04:04] */
1061	#define HIF_REG_PLL_STAT_CTRL_RST_MASK 0x10
1062	#define HIF_REG_PLL_STAT_CTRL_RST_ALIGN 0
1063	#define HIF_REG_PLL_STAT_CTRL_RST_BITS 1
1064	#define HIF_REG_PLL_STAT_CTRL_RST_SHIFT 4
1065
1066	/* HIF :: REG_PLL_STAT_CTRL :: RSVD [03:03] */
1067	#define HIF_REG_PLL_STAT_CTRL_RSVD_MASK 0x08
1068	#define HIF_REG_PLL_STAT_CTRL_RSVD_ALIGN 0
1069	#define HIF_REG_PLL_STAT_CTRL_RSVD_BITS 1
1070	#define HIF_REG_PLL_STAT_CTRL_RSVD_SHIFT 3
1071
1072	/* HIF :: REG_PLL_STAT_CTRL :: SEL [02:00] */
1073	#define HIF_REG_PLL_STAT_CTRL_SEL_MASK 0x07
1074	#define HIF_REG_PLL_STAT_CTRL_SEL_ALIGN 0
1075	#define HIF_REG_PLL_STAT_CTRL_SEL_BITS 3
1076	#define HIF_REG_PLL_STAT_CTRL_SEL_SHIFT 0
1077
1078	/***************************************************************************
1079	*REG_PLL_STATUS2 - Register PLL Status
1080	***************************************************************************/
1081	/* HIF :: REG_PLL_STATUS2 :: RSVD_0 [07:01] */
1082	#define HIF_REG_PLL_STATUS2_RSVD_0_MASK 0xfe
1083	#define HIF_REG_PLL_STATUS2_RSVD_0_ALIGN 0
1084	#define HIF_REG_PLL_STATUS2_RSVD_0_BITS 7
1085	#define HIF_REG_PLL_STATUS2_RSVD_0_SHIFT 1
1086
1087	/* HIF :: REG_PLL_STATUS2 :: LOCK [00:00] */
1088	#define HIF_REG_PLL_STATUS2_LOCK_MASK 0x01
1089	#define HIF_REG_PLL_STATUS2_LOCK_ALIGN 0
1090	#define HIF_REG_PLL_STATUS2_LOCK_BITS 1
1091	#define HIF_REG_PLL_STATUS2_LOCK_SHIFT 0
1092
1093	/***************************************************************************
1094	*REG_PLL_STATUS1 - Register PLL Status
1095	***************************************************************************/
1096	/* HIF :: REG_PLL_STATUS1 :: RSVD_0 [07:04] */
1097	#define HIF_REG_PLL_STATUS1_RSVD_0_MASK 0xf0
1098	#define HIF_REG_PLL_STATUS1_RSVD_0_ALIGN 0
1099	#define HIF_REG_PLL_STATUS1_RSVD_0_BITS 4
1100	#define HIF_REG_PLL_STATUS1_RSVD_0_SHIFT 4
1101
1102	/* HIF :: REG_PLL_STATUS1 :: STAT_OUT [03:00] */
1103	#define HIF_REG_PLL_STATUS1_STAT_OUT_MASK 0x0f
1104	#define HIF_REG_PLL_STATUS1_STAT_OUT_ALIGN 0
1105	#define HIF_REG_PLL_STATUS1_STAT_OUT_BITS 4
1106	#define HIF_REG_PLL_STATUS1_STAT_OUT_SHIFT 0
1107
1108	/***************************************************************************
1109	*REG_PLL_STATUS0 - Register PLL Status
1110	***************************************************************************/
1111	/* HIF :: REG_PLL_STATUS0 :: STAT_OUT [07:00] */
1112	#define HIF_REG_PLL_STATUS0_STAT_OUT_MASK 0xff
1113	#define HIF_REG_PLL_STATUS0_STAT_OUT_ALIGN 0
1114	#define HIF_REG_PLL_STATUS0_STAT_OUT_BITS 8
1115	#define HIF_REG_PLL_STATUS0_STAT_OUT_SHIFT 0
1116
1117	/***************************************************************************
1118	*REG_CLK_EN - Register Clock Enable
1119	***************************************************************************/
1120	/* HIF :: REG_CLK_EN :: RSVD [07:02] */
1121	#define HIF_REG_CLK_EN_RSVD_MASK 0xfc
1122	#define HIF_REG_CLK_EN_RSVD_ALIGN 0
1123	#define HIF_REG_CLK_EN_RSVD_BITS 6
1124	#define HIF_REG_CLK_EN_RSVD_SHIFT 2
1125
1126	/* HIF :: REG_CLK_EN :: PERIPH [01:01] */
1127	#define HIF_REG_CLK_EN_PERIPH_MASK 0x02
1128	#define HIF_REG_CLK_EN_PERIPH_ALIGN 0
1129	#define HIF_REG_CLK_EN_PERIPH_BITS 1
1130	#define HIF_REG_CLK_EN_PERIPH_SHIFT 1
1131
1132	/* HIF :: REG_CLK_EN :: LEAP [00:00] */
1133	#define HIF_REG_CLK_EN_LEAP_MASK 0x01
1134	#define HIF_REG_CLK_EN_LEAP_ALIGN 0
1135	#define HIF_REG_CLK_EN_LEAP_BITS 1
1136	#define HIF_REG_CLK_EN_LEAP_SHIFT 0
1137
1138	/***************************************************************************
1139	*SYS_CLK_EN - System Clock Enable
1140	***************************************************************************/
1141	/* HIF :: SYS_CLK_EN :: RSVD [07:01] */
1142	#define HIF_SYS_CLK_EN_RSVD_MASK 0xfe
1143	#define HIF_SYS_CLK_EN_RSVD_ALIGN 0
1144	#define HIF_SYS_CLK_EN_RSVD_BITS 7
1145	#define HIF_SYS_CLK_EN_RSVD_SHIFT 1
1146
1147	/* HIF :: SYS_CLK_EN :: LEAP [00:00] */
1148	#define HIF_SYS_CLK_EN_LEAP_MASK 0x01
1149	#define HIF_SYS_CLK_EN_LEAP_ALIGN 0
1150	#define HIF_SYS_CLK_EN_LEAP_BITS 1
1151	#define HIF_SYS_CLK_EN_LEAP_SHIFT 0
1152
1153	/***************************************************************************
1154	*MISC_CTRL - Miscellaneous Control
1155	***************************************************************************/
1156	/* HIF :: MISC_CTRL :: RSVD [07:03] */
1157	#define HIF_MISC_CTRL_RSVD_MASK 0xf8
1158	#define HIF_MISC_CTRL_RSVD_ALIGN 0
1159	#define HIF_MISC_CTRL_RSVD_BITS 5
1160	#define HIF_MISC_CTRL_RSVD_SHIFT 3
1161
1162	/* HIF :: MISC_CTRL :: OSC_CML_CTRL_SRC [02:02] */
1163	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_MASK 0x04
1164	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_ALIGN 0
1165	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_BITS 1
1166	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_SHIFT 2
1167
1168	/* HIF :: MISC_CTRL :: RBUS_CLK_SRC [01:01] */
1169	#define HIF_MISC_CTRL_RBUS_CLK_SRC_MASK 0x02
1170	#define HIF_MISC_CTRL_RBUS_CLK_SRC_ALIGN 0
1171	#define HIF_MISC_CTRL_RBUS_CLK_SRC_BITS 1
1172	#define HIF_MISC_CTRL_RBUS_CLK_SRC_SHIFT 1
1173
1174	/* HIF :: MISC_CTRL :: REG_PLL_STAT_CTRL_SRC [00:00] */
1175	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_MASK 0x01
1176	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_ALIGN 0
1177	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_BITS 1
1178	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_SHIFT 0
1179
1180	/***************************************************************************
1181	*SPARE3 - Spare Register
1182	***************************************************************************/
1183	/* HIF :: SPARE3 :: SPARE [07:00] */
1184	#define HIF_SPARE3_SPARE_MASK 0xff
1185	#define HIF_SPARE3_SPARE_ALIGN 0
1186	#define HIF_SPARE3_SPARE_BITS 8
1187	#define HIF_SPARE3_SPARE_SHIFT 0
1188
1189	/***************************************************************************
1190	*SPARE2 - Spare Register
1191	***************************************************************************/
1192	/* HIF :: SPARE2 :: SPARE [07:00] */
1193	#define HIF_SPARE2_SPARE_MASK 0xff
1194	#define HIF_SPARE2_SPARE_ALIGN 0
1195	#define HIF_SPARE2_SPARE_BITS 8
1196	#define HIF_SPARE2_SPARE_SHIFT 0
1197
1198	/***************************************************************************
1199	*SPARE1 - Spare Register
1200	***************************************************************************/
1201	/* HIF :: SPARE1 :: SPARE [07:00] */
1202	#define HIF_SPARE1_SPARE_MASK 0xff
1203	#define HIF_SPARE1_SPARE_ALIGN 0
1204	#define HIF_SPARE1_SPARE_BITS 8
1205	#define HIF_SPARE1_SPARE_SHIFT 0
1206
1207	/***************************************************************************
1208	*SPARE0 - Spare Register
1209	***************************************************************************/
1210	/* HIF :: SPARE0 :: SPARE [07:00] */
1211	#define HIF_SPARE0_SPARE_MASK 0xff
1212	#define HIF_SPARE0_SPARE_ALIGN 0
1213	#define HIF_SPARE0_SPARE_BITS 8
1214	#define HIF_SPARE0_SPARE_SHIFT 0
1215
1216	/***************************************************************************
1217	*SFT3 - Software Register
1218	***************************************************************************/
1219	/* HIF :: SFT3 :: SFT [07:00] */
1220	#define HIF_SFT3_SFT_MASK 0xff
1221	#define HIF_SFT3_SFT_ALIGN 0
1222	#define HIF_SFT3_SFT_BITS 8
1223	#define HIF_SFT3_SFT_SHIFT 0
1224
1225	/***************************************************************************
1226	*SFT2 - Software Register
1227	***************************************************************************/
1228	/* HIF :: SFT2 :: SFT [07:00] */
1229	#define HIF_SFT2_SFT_MASK 0xff
1230	#define HIF_SFT2_SFT_ALIGN 0
1231	#define HIF_SFT2_SFT_BITS 8
1232	#define HIF_SFT2_SFT_SHIFT 0
1233
1234	/***************************************************************************
1235	*SFT1 - Software Register
1236	***************************************************************************/
1237	/* HIF :: SFT1 :: SFT [07:00] */
1238	#define HIF_SFT1_SFT_MASK 0xff
1239	#define HIF_SFT1_SFT_ALIGN 0
1240	#define HIF_SFT1_SFT_BITS 8
1241	#define HIF_SFT1_SFT_SHIFT 0
1242
1243	/***************************************************************************
1244	*SFT0 - Software Register
1245	***************************************************************************/
1246	/* HIF :: SFT0 :: SFT [07:00] */
1247	#define HIF_SFT0_SFT_MASK 0xff
1248	#define HIF_SFT0_SFT_ALIGN 0
1249	#define HIF_SFT0_SFT_BITS 8
1250	#define HIF_SFT0_SFT_SHIFT 0
1251
1252	#endif /* #ifndef HOST_SERIAL_INTERFACE_H__ */
1253
1254	/* End of File */

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source: svn/trunk/newcon3bcm2_21bu/magnum/basemodules/hab/3461/bhab_3461_bbsi.h

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