source: svn/trunk/newcon3bcm2_21bu/magnum/commonutils/afl/bafl_elf.h

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[2]1/***************************************************************************
2 * bafl_elf.h
3 *
4 * Standard (common) definitions for ELF structures/fields.
5 *
6 * All of this material comes out of the ELF 1.1 Specification.
7 * Metaware ARC-specific definitions are below.
8 *
9 * $brcm_Workfile: bafl_elf.h $
10 * $brcm_Revision: Hydra_Software_Devel/2 $
11 * $brcm_Date: 2/11/11 5:20p $
12 *
13 * Module Description:
14 *   See module
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/commonutils/afl/bafl_elf.h $
19 *
20 * Hydra_Software_Devel/2   2/11/11 5:20p davidp
21 * SW7422-22: Use uintXX_t types to typedef elf structure element
22 * datatypes.
23 *
24 * Hydra_Software_Devel/1   8/27/10 4:33p davidp
25 * SW7425-1: Merge from branch.
26 *
27 * Hydra_Software_Devel/SW7425-1/1   8/18/10 5:00p davidp
28 * SW7425-1: Initial checkin.
29 *
30 ***************************************************************************/
31
32#ifndef _BAFL_ELF_H__
33#define _BAFL_ELF_H__
34
35typedef uint32_t   Bafl_Elf32_Addr;
36typedef uint16_t   Bafl_Elf32_Half;
37typedef uint32_t   Bafl_Elf32_Off;
38typedef int32_t    Bafl_Elf32_Sword;
39typedef uint32_t   Bafl_Elf32_Word;
40
41#define ET_NIDENT       16
42
43typedef struct
44{
45      unsigned char   e_ident[ET_NIDENT];
46      Bafl_Elf32_Half e_type;
47      Bafl_Elf32_Half e_machine;
48      Bafl_Elf32_Word e_version;
49      Bafl_Elf32_Addr e_entry;
50      Bafl_Elf32_Off  e_phoff;
51      Bafl_Elf32_Off  e_shoff;
52      Bafl_Elf32_Word e_flags;
53      Bafl_Elf32_Half e_ehsize;
54      Bafl_Elf32_Half e_phentsize;
55      Bafl_Elf32_Half e_phnum;
56      Bafl_Elf32_Half e_shentsize;
57      Bafl_Elf32_Half e_shnum;
58      Bafl_Elf32_Half e_shstrndx;
59} BAFL_Elf32_Ehdr;
60
61        /* e_type definitions */
62#define BAFL_ET_NONE         0       /* No file type         */
63#define BAFL_ET_REL          1       /* Relocatable file     */
64#define BAFL_ET_EXEC         2       /* Executable file      */
65#define BAFL_ET_DYN          3       /* Shared object file   */
66#define BAFL_ET_CORE         4       /* Core file            */
67#define BAFL_ET_LOPROC       0xFF00  /* Processor-specific   */
68#define BAFL_ET_HIPROC       0xFFFF  /* Processor-specific   */
69
70        /* e_machine definitions */
71#define BAFL_EM_NONE         0       /* No machine           */
72#define BAFL_EM_M32          1       /* AT&T WE 32100        */
73#define BAFL_EM_SPARC        2       /* SPARC                */
74#define BAFL_EM_386          3       /* Intel 80386          */
75#define BAFL_EM_68K          4       /* Motorola 68000       */
76#define BAFL_EM_88K          5       /* Motorola 88000       */
77#define BAFL_EM_860          7       /* Intel 80860          */
78#define BAFL_EM_MIPS         8       /* MIPS RS3000          */
79#define BAFL_EM_ARC          45      /* Argonaut Risc Core   */
80
81        /* e_version definitions */
82#define BAFL_EV_NONE         0       /* Invalid version      */
83#define BAFL_EV_CURRENT      1       /* Current version      */
84
85        /* e_ident[] fields */
86#define BAFL_EI_MAG0         0       /* File identification  */
87#define BAFL_EI_MAG1         1       /* File identification  */
88#define BAFL_EI_MAG2         2       /* File identification  */
89#define BAFL_EI_MAG3         3       /* File identification  */
90#define BAFL_EI_CLASS        4       /* File class           */
91#define BAFL_EI_DATA         5       /* Data encoding        */
92#define BAFL_EI_VERSION      6       /* File version         */
93#define BAFL_EI_PAD          7       /* Start of padding     */
94
95#define BAFL_ELFMAG0         0x7F
96#define BAFL_ELFMAG1         'E'
97#define BAFL_ELFMAG2         'L'
98#define BAFL_ELFMAG3         'F'
99
100#define BAFL_ELFCLASSNONE    0       /* Invalid class        */
101#define BAFL_ELFCLASS32      1       /* 32-bit objects       */
102#define BAFL_ELFCLASS64      2       /* 64-bit objects       */
103
104#define BAFL_ELFDATANONE     0       /* Invalid data encoding        */
105#define BAFL_ELFDATA2LSB     1       /* Little-endian encoding       */
106#define BAFL_ELFDATA2MSB     2       /* Big-endian encoding          */
107
108#define BAFL_SHN_UNDEF     0
109#define BAFL_SHN_LORESERVE 0xff00
110#define BAFL_SHN_LOPROC    0xff00
111#define BAFL_SHN_HIPROC    0xff1f
112#define BAFL_SHN_ABS       0xfff1
113#define BAFL_SHN_COMMON    0xfff2
114#define BAFL_SHN_HIRESERVE 0xffff
115
116typedef struct
117{     
118      Bafl_Elf32_Word  sh_name;      /* Section name (string tbl index)      */
119      Bafl_Elf32_Word  sh_type;      /* Section type                         */
120      Bafl_Elf32_Word  sh_flags;     /* Section flags                        */
121      Bafl_Elf32_Addr  sh_addr;      /* Section virtual addr at execution    */
122      Bafl_Elf32_Off   sh_offset;    /* Section file offset                  */
123      Bafl_Elf32_Word  sh_size;      /* Section size in bytes                */
124      Bafl_Elf32_Word  sh_link;      /* Link to another section              */
125      Bafl_Elf32_Word  sh_info;      /* Additional section information       */
126      Bafl_Elf32_Word  sh_addralign; /* Section alignment                    */
127      Bafl_Elf32_Word  sh_entsize;   /* Entry size if section holds table    */
128} BAFL_Elf32_Shdr;
129
130#define BAFL_SHT_NULL        0
131#define BAFL_SHT_PROGBITS    1
132#define BAFL_SHT_SYMTAB      2
133#define BAFL_SHT_STRTAB      3
134#define BAFL_SHT_RELA        4
135#define BAFL_SHT_HASH        5
136#define BAFL_SHT_DYNAMIC     6
137#define BAFL_SHT_NOTE        7
138#define BAFL_SHT_NOBITS      8
139#define BAFL_SHT_REL         9
140#define BAFL_SHT_SHLIB       10
141#define BAFL_SHT_DYNSYM      11
142#define BAFL_SHT_LOPROC      0x70000000
143#define BAFL_SHT_HIPROC      0x7FFFFFFF
144#define BAFL_SHT_LOUSER      0x80000000
145#define BAFL_SHT_HIUSER      0xFFFFFFFF
146
147#define BAFL_SHF_WRITE       0x1
148#define BAFL_SHF_ALLOC       0x2
149#define BAFL_SHF_EXECINSTR   0x4
150#define BAFL_SHF_MASKPROC    0xF0000000
151
152
153typedef struct
154{ 
155      Bafl_Elf32_Word st_name;
156      Bafl_Elf32_Addr st_value;
157      Bafl_Elf32_Word st_size;
158      unsigned char   st_info;
159      unsigned char   st_other;
160      Bafl_Elf32_Half st_shndx;
161} Bafl_Elf32_Sym;
162
163#define BAFL_ELF32_ST_BIND(i)   ((i) >> 4)
164#define BAFL_ELF32_ST_TYPE(i)   ((i) & 0x0F)
165#define BAFL_ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0x0F))
166
167#define BAFL_STB_LOCAL       0
168#define BAFL_STB_GLOBAL      1
169#define BAFL_STB_WEAK        2
170#define BAFL_STB_LOPROC      13
171#define BAFL_STB_HIPROC      15
172
173#define BAFL_STT_NOTYPE      0
174#define BAFL_STT_OBJECT      1
175#define BAFL_STT_FUNC        2
176#define BAFL_STT_SECTION     3
177#define BAFL_STT_FILE        4
178#define BAFL_STT_LOPROC      13
179#define BAFL_STT_HIPROC      15
180
181typedef struct
182{ 
183      Bafl_Elf32_Addr r_offset;
184      Bafl_Elf32_Word r_info;
185} Bafl_Elf32_Rel;
186
187typedef struct
188{
189      Bafl_Elf32_Addr  r_offset;
190      Bafl_Elf32_Word  r_info;
191      Bafl_Elf32_Sword r_addend;
192} Bafl_Elf32_Rela;
193
194#define BAFL_ELF32_R_SYM(i)          ((i) >> 8)
195#define BAFL_ELF32_R_TYPE(i)         ((unsigned char)(i))
196#define BAFL_ELF32_R_INFO(s,t)       (((s) << 8) + (unsigned char)(t))
197
198
199typedef struct
200{ 
201      Bafl_Elf32_Word p_type;
202      Bafl_Elf32_Off  p_offset;
203      Bafl_Elf32_Addr p_vaddr;
204      Bafl_Elf32_Addr p_paddr;
205      Bafl_Elf32_Word p_filesz;
206      Bafl_Elf32_Word p_memsz;
207      Bafl_Elf32_Word p_flags;
208      Bafl_Elf32_Word p_align;
209} Bafl_Elf32_Phdr;
210
211#define BAFL_PT_NULL         0
212#define BAFL_PT_LOAD         1
213#define BAFL_PT_DYNAMIC      2
214#define BAFL_PT_INTERP       3
215#define BAFL_PT_NOTE         4
216#define BAFL_PT_SHLIB        5
217#define BAFL_PT_PHDR         6
218#define BAFL_PT_LOPROC       0x70000000
219#define BAFL_PT_HIPROC       0x7FFFFFFF
220
221/*----------------------------------------------------------------------*
222 *                                                                      *
223 * The following is the elf_arc.h file from Metaware.                   *
224 *                                                                      *
225 *----------------------------------------------------------------------*/
226
227
228/*********************************************************************
229 * THE SOFTWARE CONTAINED IN THIS FILE IS LICENSED TO BROADCOMS
230 * CUSTOMERS FOR USE SOLELY IN CONNECTION WITH ARC processors
231 * within BROADCOM'S PRODUCTS.
232 * (C) Copyright 2005; ARC International (ARC);  Santa Cruz, CA 95060
233 * This program is the unpublished property and trade secret of ARC.  It
234 * is to be  utilized  solely  under  license and it is to be maintained
235 * on a confidential basis. The security  and  protection  of  the program
236 * is paramount to maintenance of the trade secret status.  It is to be
237 * protected from disclosure to unauthorized parties, both within the
238 * Licensee company and outside, in a manner not less stringent than that
239 * utilized for Licensee's own proprietary internal information. 
240 *********************************************************************/
241
242/**********************************************************************
243* Relocation types for the ARC ELF object files
244*   A = addend used to compute the relocation
245*   S = The value of the symbol being relocated
246*   P = The place (addr/section offset) of the storage unit being relocated
247*       (computed using r_offset)
248*
249* Relocation Fields (note this is big-endian notation...)
250*   +--------------------------------+
251*   |31          bits31-0           0| word32 data in separate word
252*   +--------------------------------+
253*
254*   +------------------------+
255*   |23      bits23-0       0| bits24 data in separate 3-byte chunk
256*   +------------------------+
257*
258*   +----------------+
259*   |15  bits15-0   0| bits16 data in separate half-word
260*   +----------------+
261*
262*   +-----------+
263*   |7 bits7-0 0| bits8 data in separate byte
264*   +-----------+
265*
266*   +--------------------------------+
267*   |31     |23     bits25-2        0| targ26 data as part of an instruction
268*   +--------------------------------+
269*
270*   +--------------------------------+
271*   |31  |26    bits21-2     7|     0| disp22 data as part of an instruction
272*   +--------------------------------+
273*
274*   +--------------------------------------------+
275*   |31  |26 bits10-1  17| |15 bits20-11 6|     0| disp21h data in instruction
276*   +--------------------------------------------+ (half-word aligned)
277*
278*   +--------------------------------------------+
279*   |31  |26 bits10-2  18| |15 bits20-11 6|     0| disp21w data in instruction
280*   +--------------------------------------------+ (long-word aligned)
281*
282*   +------------------------------------------------------+
283*   |31  |26 bits10-1  17| |15 bits20-11 6|  |3 bits24-21 0| disp25h data
284*   +------------------------------------------------------+ (halfword aligned)
285*
286*   +------------------------------------------------------+
287*   |31  |26 bits10-2  18| |15 bits20-11 6|  |3 bits24-21 0| disp25w data
288*   +------------------------------------------------------+ (longword aligned)
289*
290*   +--------------------------------+
291*   |31                  9| bits8-0 0| disp9 as part of an instruction
292*   +--------------------------------+
293*
294*   +--------------------------------+
295*   |31 |23 bits7-0 16|15 bit8|14   0| disp9ls as part of an instruction
296*   +--------------------------------+
297*
298*   +-------------------+
299*   |15     9| bits8-0 0| disp9s as part of an instruction
300*   +-------------------+
301*
302*   +----------------==-+
303*   |15   11| bits10-0 0| disp13s as part of an instruction (longword aligned)
304*   +----------------==-+
305*
306*********************************************************************/
307
308/*      Relo Type Name        Value    Field    Calculation */
309#define R_ARC_NONE            0x0   /* none     None */
310#define R_ARC_8               0x1   /* bits8    S + A */
311#define R_ARC_16              0x2   /* bits16   S + A */
312#define R_ARC_24              0x3   /* bits24   S + A */
313#define R_ARC_32              0x4   /* word32   S + A */
314#define R_ARC_B26             0x5   /* targ26   (S + A) >> 2   
315                                     *(convert to longword displacement)
316                                     */
317#define R_ARC_B22_PCREL       0x6   /* disp22   (S + A - P) >> 2
318                                     *    (convert to longword displacement)
319                                     */
320#define R_ARC_H30             0x7   /* word32   (S + A) >> 2 */
321#define R_ARC_N8              0x8   /* bits8    S - A */
322#define R_ARC_N16             0x9   /* bits16   S - A */
323#define R_ARC_N24             0xA   /* bits24   S - A */
324#define R_ARC_N32             0xB   /* word32   S - A */
325#define R_ARC_SDA             0xC   /* disp9    S + A */
326#define R_ARC_SECTOFF         0xD   /* word32   (S - <start of section>) + A */
327
328/*************************************************************************
329 * following new relocations defined for the ARCompact ISA
330 *************************************************************************/
331
332/* for conditional branch. Example: bne   printf */
333#define R_ARC_S21H_PCREL  0xE   /* disp21h  (S + A - P) >> 1
334                                 * (convert to halfword displacement)
335                                 */
336
337/* for conditional branch and link. Example: blne  printf */
338#define R_ARC_S21W_PCREL  0xF   /* disp21w  (S + A - P) >> 2
339                                 * (convert to longword displacement)
340                                 */
341
342/* For unconditional branch.  Example: b  printf */
343#define R_ARC_S25H_PCREL  0x10   /* disp25h  (S + A - P) >> 1
344                                  * (convert to halfword displacement)
345                                  */
346
347/* For unconditional branch and link.  Example: bl  printf */
348#define R_ARC_S25W_PCREL  0x11   /* disp25w  (S + A - P) >> 2
349                                  * (convert to longword displacement)
350                                  */
351
352/* for 32-bit Small Data Area fixups.  Example: add   r0, gp, var@sda */
353#define R_ARC_SDA32       0x12   /* word32   (S + A) - _SDA_BASE_ */
354
355/* for small data fixups on loads and stores.  Examples:
356 *     ldb   r0,  [gp, var@sda]   ; R_ARC_SDA_LDST
357 *     stw   r0,  [gp, var@sda]   ; R_ARC_SDA_LDST1
358 *     ld    r0,  [gp, var@sda]   ; R_ARC_SDA_LDST2
359 */
360#define R_ARC_SDA_LDST   0x13   /* disp9ls (S + A - _SDA_BASE_)  (s9 range) */
361#define R_ARC_SDA_LDST1  0x14   /* disp9ls (S+A-_SDA_BASE_) >> 1 (s10 range) */
362#define R_ARC_SDA_LDST2  0x15   /* disp9ls (S+A-_SDA_BASE_) >> 2 (s11 range) */
363
364/* for 16-bit load gp-relative instruction. Example:
365 *     ldb_s  r0, [gp, var@sda]   ; R_ARC_SDA16_LD
366 *     ldw_s  r0, [gp, var@sda]   ; R_ARC_SDA16_LD1
367 *     ld_s   r0, [gp, var@sda]   ; R_ARC_SDA16_LD2
368 */
369#define R_ARC_SDA16_LD   0x16   /* disp9s  (S + A - _SDA_BASE)   (s9 range) */
370#define R_ARC_SDA16_LD1  0x17   /* disp9s  (S+A-_SDA_BASE_) >> 1 (s10 range) */
371#define R_ARC_SDA16_LD2  0x18   /* disp9s  (S+A-_SDA_BASE_) >> 2 (s11 range) */
372
373/* for 16-bit branch-and-link.  Example: bl_s  printf */
374#define R_ARC_S13_PCREL      0x19   /* disp13s  (S + A - P) >> 2 */
375
376/* for 32-bit alignment of the fixup value.  Examples:
377 *     mov   r0,  var@l
378 *     ld    r0, [pcl, lab - .@l]
379 */
380#define R_ARC_W              0x1a   /* word32   (S + A) & ~3   (word-align) */
381
382/*
383 * The following relocations are to support middle-endian storage, whereby
384 * a 32-bit word is stored in two halfwords, with bits 31-16 stored first
385 * in memory and bits 15-0 stored adjacently.  The individual half-words are
386 * stored in the native endian of the machine.  This is how all instructions
387 * and LIMMs are stored in the ARCompact architecture.
388 */
389#define R_ARC_32_ME          0x1b   /* Like ARC_32, but stored in ME format */
390#define R_ARC_N32_ME         0x1c   /* Like N32, but stored in ME format */
391#define R_ARC_SECTOFF_ME     0x1d   /* Like SECTOFF, but stored in ME format */
392#define R_ARC_SDA32_ME       0x1e   /* Like SDA32, but stored in ME format */
393#define R_ARC_W_ME           0x1f   /* Like W, but stored in ME format */
394#define R_ARC_H30_ME         0x20   /* Like H30, but stored in ME format */
395
396/*************************************************************************/
397
398/*
399 * for ARC4 ld/st instructions, allows a section-relative offset in the
400 * range 0-255 (the positive portion of the shimm range).  The base
401 * register must be loaded with the base address of the section. Example:
402 * ld   r0, [r20, var@sectoff_u8]
403 */
404
405#define R_ARC_SECTOFF_U8     0x21   / disp9 (S + A - <start of section>) */
406
407/* ARC4. range -256 to 255.  The base register must be loaded with base of
408 * section + 256. Example:
409 *   ld   r0, [r20, var@sectoff_s9]
410 */
411#define R_ARC_SECTOFF_S9  0x22   /* disp9 (S + A - <start of section> - 256) */
412
413/*
414 * Same semantics as R_ARC_SECTOFF_U8 above, but for ARCompact ISA
415 * Note, however that the assembler encodes these loads and stores with
416 * address scaling (.as) turned on so that the range for half-words is
417 * 0-510 and the range for full 32-bit word accesses is 0-1020
418 * The range for byte accesses remains 0-255
419 *    ldb  r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8
420 *    stw  r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8_1
421 *    ld   r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8_2
422 */
423#define R_AC_SECTOFF_U8   0x23   /* disp9ls (S + A - <start of section>) */
424#define R_AC_SECTOFF_U8_1 0x24   /* disp9ls (S +A - <start of section>) >> 1 */
425#define R_AC_SECTOFF_U8_2 0x25   /* disp9ls (S +A - <start of section>) >> 2 */
426
427/*
428 * Same semantics as R_ARC_SECTOFF_S9 above, but for ARCompact ISA
429 * Note, however that the assembler encodes these loads and stores with
430 * address scaling (.as) turned on so that the range for half-words is
431 * -256-510 and the range for full 32-bit word accesses is -256-1020
432 * The range for byte accesses remains -256-255
433 *    ldb  r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9
434 *    stw  r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9_1
435 *    ld   r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9_2
436 */
437#define R_AC_SECTOFF_S9   0x26   /* disp9ls (S + A - <start of section>) */
438#define R_AC_SECTOFF_S9_1 0x27   /* disp9ls (S +A - <start of section>) >> 1 */
439#define R_AC_SECTOFF_S9_2 0x28   /* disp9ls (S +A - <start of section>) >> 2 */
440
441/* X/Y memory relocations */
442#define R_ARC_SECTOFF_ME_1   0x29   /* word32  ((S - <start of section>) + A)
443                                     * >> 1 [ME format]
444                                     */
445
446#define R_ARC_SECTOFF_ME_2   0x2a   /* word32  ((S - <start of section>) + A)
447                                     * >> 2 [ME format]
448                                     */
449
450#define R_ARC_SECTOFF_1      0x2b   /* word32  ((S - <start of section>) + A)
451                                     * >> 1
452                                     */
453
454#define R_ARC_SECTOFF_2      0x2c   /* word32  ((S - <start of section>) + A)
455                                     * >> 2
456                                     */
457
458#endif
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