source: svn/trunk/newcon3bcm2_21bu/magnum/commonutils/rdc/7552/brdc_private.c

Last change on this file was 2, checked in by jglee, 11 years ago

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1/***************************************************************************
2 *     Copyright (c) 2003-2011, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: brdc_private.c $
11 * $brcm_Revision: Hydra_Software_Devel/31 $
12 * $brcm_Date: 11/1/11 9:55a $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/commonutils/rdc/7038/brdc_private.c $
19 *
20 * Hydra_Software_Devel/31   11/1/11 9:55a pntruong
21 * SW7435-23: Initial rdc support for 7435.
22 *
23 * Hydra_Software_Devel/30   12/15/10 12:33p erickson
24 * SW7420-941: add missing bstd.h
25 *
26 * Hydra_Software_Devel/29   6/22/10 3:03p pntruong
27 * SW7422-12: Fixed build errors.  Corrected naming to follow previous
28 * naming convention.
29 *
30 * Hydra_Software_Devel/28   6/22/10 11:40a vanessah
31 * SW7422-12:  To support appframework. Missing files added:
32 * magnum\portinginterface\pwr rockford\appframework\src\board\97422  To
33 * do list: 1. in framework_board.c, more initialization to be done.  2.
34 * More registers mapping, like clock generation as well as
35 * BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL etc
36 *
37 * Hydra_Software_Devel/27   1/22/09 1:05p pntruong
38 * PR51344: Change RDC delay from 600 to 1000.
39 *
40 * Hydra_Software_Devel/26   1/6/07 12:22a pntruong
41 * PR26943: Update documentation in RDMA - cannot access registers outside
42 * of BVN.
43 *
44 * Hydra_Software_Devel/25   8/15/06 6:37p pntruong
45 * PR23177:  Also need to map the unknown trigger for trigger_select.
46 *
47 * Hydra_Software_Devel/24   8/14/06 7:52p pntruong
48 * PR23177: RDC module bringup.
49 *
50 * Hydra_Software_Devel/23   8/7/06 3:29p pntruong
51 * PR23177: RDC module bringup.
52 *
53 * Hydra_Software_Devel/22   1/3/06 3:01p yuxiaz
54 * PR17593: Removed unused RDC task-context code. Use the _isr version of
55 * functions for the non-_isr version.
56 *
57 * Hydra_Software_Devel/21   11/23/04 8:53p pntruong
58 * PR13076, PR11749: Video jitter under heavy system load.  Added RUL
59 * execution check to reduce number of programmed registers.
60 *
61 * Hydra_Software_Devel/20   11/9/04 2:35p yuxiaz
62 * PR13108: Use BKNI_Delay(1) to respond as quick as possible. Fixed
63 * comment.
64 *
65 * Hydra_Software_Devel/19   10/28/04 4:07p yuxiaz
66 * PR13108: Remove BKNI_Sleep from critical section and _isr functions.
67 * Clean up _isr and non_isr functions.
68 *
69 * Hydra_Software_Devel/18   4/30/04 3:32p hongtaoz
70 * PR8761: fixed C++ compile error.
71 *
72 * Hydra_Software_Devel/17   3/16/04 2:52p yuxiaz
73 * PR 10095: Added code to enable RDC acess of  regsiters outside BVN.
74 * This code is disabled for A0.
75 *
76 * Hydra_Software_Devel/16   1/14/04 4:41p yuxiaz
77 * PR 9076: Change isr functions to _isr.
78 *
79 * Hydra_Software_Devel/15   12/31/03 11:09a yuxiaz
80 * PR 9142: fixed compile warning with "-W" option.
81 *
82 * Hydra_Software_Devel/14   12/22/03 11:54a jasonh
83 * PR 8861: Set reset to initialize registers to known state. Fixed forced
84 * execute to set trigger/repeat appropriately. Added new private
85 * routines to acquire/release semaphore and dump debugging slot
86 * information.
87 *
88 * Hydra_Software_Devel/13   10/30/03 2:45p yuxiaz
89 * Remove bInterrupt from BRDC_Slot_Execute and
90 * BRDC_Slot_ExecuteOnTrigger.
91 *
92 * Hydra_Software_Devel/12   10/27/03 3:13p yuxiaz
93 * Added soft reset.
94 *
95 * Hydra_Software_Devel/11   10/23/03 10:43a yuxiaz
96 * Don't clear repeat for BRDC_Slot_Execute.
97 *
98 * Hydra_Software_Devel/10   10/17/03 8:56a yuxiaz
99 * Fixed BDBG_ENTER and BDBG_LEAVE.
100 *
101 * Hydra_Software_Devel/9   9/24/03 10:28a yuxiaz
102 * Convert virtual address to physical address offset.
103 *
104 * Hydra_Software_Devel/8   9/23/03 2:25p yuxiaz
105 * Fixed count setting in RDC_desc_x_config.
106 *
107 * Hydra_Software_Devel/7   9/8/03 9:35a yuxiaz
108 * Change unsigned int to uint32_t.
109 *
110 * Hydra_Software_Devel/6   9/2/03 2:55p yuxiaz
111 * Added BRDC_Slot_GetId, moved BRDC_SlotId to brdc.h.
112 *
113 * Hydra_Software_Devel/5   7/25/03 12:12p yuxiaz
114 * Change BRDC_Trigger to use defines in RDB. Misc clean up.
115 *
116 * Hydra_Software_Devel/4   7/17/03 8:50a yuxiaz
117 * Added debug message.
118 *
119 * Hydra_Software_Devel/3   7/2/03 10:19a yuxiaz
120 * Fixed register write.
121 *
122 * Hydra_Software_Devel/2   6/30/03 1:15p yuxiaz
123 * Added BRDC_Trigger.
124 *
125 * Hydra_Software_Devel/1   6/27/03 2:55p yuxiaz
126 * Initial version.
127 *
128 ***************************************************************************/
129
130#include "bstd.h"                /* standard types */
131#include "brdc_private.h"
132#include "bchp_fmisc.h"
133#include "bkni.h"
134#include "bchp_sun_gisb_arb.h"
135
136BDBG_MODULE(BRDC);
137
138/* Internal constant */
139#define BRDC_P_SEMAPHORE_ACQUIRE_DELAY           (1000)
140
141/***************************************************************************
142Summary:
143        Reset RDC
144
145Description:
146
147Input:
148        hRdc - The RDC handle.
149
150Output:
151
152Returns:
153
154****************************************************************************/
155BERR_Code BRDC_P_SoftReset
156(
157        BRDC_Handle   hRdc
158)
159{
160        BERR_Code err = BERR_SUCCESS;
161        uint32_t  ulReg;
162        int       i;
163        uint32_t  ulRegAddr;
164        uint32_t  ulRegConfig;
165        uint32_t ulTrigSelect;
166
167        BDBG_ENTER(BRDC_P_SoftReset);
168
169#ifdef BCHP_FMISC_SW_INIT
170        /* Write a 1 to the reset bit.*/
171        ulReg  = BRDC_P_Read32(hRdc, BCHP_FMISC_SW_INIT);
172        ulReg |= BCHP_FIELD_DATA(FMISC_SW_INIT, RDC, 1);
173        BRDC_P_Write32(hRdc, BCHP_FMISC_SW_INIT, ulReg);
174
175        /* Write a 0 to reset. */
176        ulReg &= ~BCHP_FIELD_DATA(FMISC_SW_INIT, RDC, 1);
177        BRDC_P_Write32(hRdc, BCHP_FMISC_SW_INIT, ulReg);
178#else
179        /* Write a 1 to the reset bit.*/
180        ulReg  = BRDC_P_Read32(hRdc, BCHP_FMISC_SOFT_RESET);
181        ulReg |= BCHP_FIELD_DATA(FMISC_SOFT_RESET, RDC, 1);
182        BRDC_P_Write32(hRdc, BCHP_FMISC_SOFT_RESET, ulReg);
183
184        /* Write a 0 to reset. */
185        ulReg &= ~BCHP_FIELD_DATA(FMISC_SOFT_RESET, RDC, 1);
186        BRDC_P_Write32(hRdc, BCHP_FMISC_SOFT_RESET, ulReg);
187#endif
188
189        /******************
190         * Set known good values for all registers
191         */
192#if (!BRDC_P_SUPPORT_SEGMENTED_RUL)
193        ulReg = BCHP_FIELD_DATA(RDC_config, same_trigger, 0);
194#else
195        ulReg = BCHP_FIELD_DATA(RDC_config, trig_arbitration_mode, 0); /* 0 - convention ; 1 - segmented mode */
196#endif
197        BRDC_P_Write32(hRdc, BCHP_RDC_config, ulReg);
198
199        /* Get trigger select value. */
200        ulTrigSelect = hRdc->aTrigInfo[BRDC_Trigger_UNKNOWN].ulTrigVal;
201
202        /* setup known values for descriptors */
203        ulRegAddr = BCHP_FIELD_DATA(RDC_desc_0_addr, addr, 0x0);
204        ulRegConfig =
205                BCHP_FIELD_DATA(RDC_desc_0_config, count,           0x0          ) |
206                BCHP_FIELD_DATA(RDC_desc_0_config, trigger_select,  ulTrigSelect ) |
207                BCHP_FIELD_DATA(RDC_desc_0_config, repeat,          0            ) |
208                BCHP_FIELD_DATA(RDC_desc_0_config, enable,          0            ) |
209                BCHP_FIELD_DATA(RDC_desc_0_config, done,            1           ) |
210                BCHP_FIELD_DATA(RDC_desc_0_config, error,           1            ) |
211                BCHP_FIELD_DATA(RDC_desc_0_config, dropped_trigger, 1            );
212
213        /* set all descriptors */
214        for (i=0; i<32; ++i)
215        {
216                /* acquire semaphore */
217                BKNI_EnterCriticalSection();
218                err = BERR_TRACE(BRDC_P_AcquireSemaphore_isr(hRdc, (BRDC_SlotId)i));
219                if (err != BERR_SUCCESS)
220                {
221                        /* error */
222                        BKNI_LeaveCriticalSection();
223                        goto done;
224                }
225
226                /* write address and config */
227                BRDC_P_Write32(hRdc, BCHP_RDC_desc_0_addr + 16 * i,   ulRegAddr);
228                BRDC_P_Write32(hRdc, BCHP_RDC_desc_0_config + 16 * i, ulRegConfig);
229
230                /* release semaphore */
231                BRDC_P_ReleaseSemaphore_isr(hRdc, (BRDC_SlotId)i);
232                BKNI_LeaveCriticalSection();
233        }
234
235        /* PR 10095:
236         * RDC can only be used to program BVN registers by default (set at bootup).
237         * Need to enable it for B0 if need to access IFD registers. */
238        /* Unmask RDC so it can access registers outside BVN, such as IFD regs. */
239        BKNI_EnterCriticalSection();
240        ulReg  = BREG_Read32_isr(hRdc->hReg, BCHP_SUN_GISB_ARB_REQ_MASK);
241#ifdef BCHP_SUN_GISB_ARB_REQ_MASK_rdc_MASK
242        ulReg &= ~BCHP_SUN_GISB_ARB_REQ_MASK_rdc_MASK;
243#endif
244#ifdef BCHP_SUN_GISB_ARB_REQ_MASK_req_mask_5_MASK
245        ulReg &= ~BCHP_SUN_GISB_ARB_REQ_MASK_req_mask_5_MASK;
246#endif
247        BREG_Write32_isr(hRdc->hReg, BCHP_SUN_GISB_ARB_REQ_MASK, ulReg);
248        BKNI_LeaveCriticalSection();
249
250done:
251        BDBG_LEAVE(BRDC_P_SoftReset);
252        return err;
253}
254
255
256/***************************************************************************
257Summary:
258        Private function to get next available slot
259
260Description:
261
262Input:
263        hRdc - The RDC handle.
264
265Output:
266        pSlotID - The returned slot ID.
267
268Returns:
269
270****************************************************************************/
271BERR_Code BRDC_Slot_P_GetNextSlot
272(
273        BRDC_Handle   hRdc,
274        BRDC_SlotId  *pSlotId
275)
276{
277        BERR_Code    err = BERR_SUCCESS;
278        int          eSlotId;
279
280        BDBG_ENTER(BRDC_Slot_P_GetNextSlot);
281
282        for( eSlotId = BRDC_SlotId_eSlot0; eSlotId < BRDC_SlotId_eSlotMAX; eSlotId++ )
283        {
284                if( !hRdc->bSlotUsed[eSlotId] )
285                {
286                        *pSlotId = (BRDC_SlotId) eSlotId;
287                        goto done;
288                }
289        }
290
291        /* Can't find any slot available */
292        err = BERR_TRACE(BRDC_SLOT_ERR_ALL_USED);
293
294done:
295        BDBG_LEAVE(BRDC_Slot_P_GetNextSlot);
296        return err;
297}
298
299/***************************************************************************
300Summary:
301        Private function to fill in hardware registers for DMA
302
303        This function assumes DMA is already locked if necessary.
304
305Description:
306
307Input:
308        hSlot - The slot to activate.
309        ui32_trigger - The trigger used to fire the slot.
310        bRecurring - Whether to allow multiple firings of the trigger to execute
311                     the slot repeatedly.
312
313Output:
314        pSlotID - The returned slot ID.
315
316Returns:
317
318****************************************************************************/
319BERR_Code BRDC_Slot_P_Write_Registers_isr
320(
321        BRDC_Slot_Handle hSlot,
322        BRDC_Trigger     eRDCTrigger,
323        bool             bRecurring,
324        bool             ExecuteOnTrigger
325)
326{
327        uint32_t ulRegVal, ulAddrOffset, ulTrigSelect;
328
329        BDBG_ENTER(BRDC_Slot_P_Write_Registers_isr);
330
331        /* Convert address to device offset from the original device base.
332         * Address returned from BMEM_AllocAligned is the virtual address */
333        BMEM_ConvertAddressToOffset(hSlot->hRdc->hMem,
334                (void *)hSlot->hList->pulRULAddr, &ulAddrOffset);
335
336        /* Set RDC_desc_x_addr */
337        BRDC_Slot_P_Write32(hSlot, BCHP_RDC_desc_0_addr + hSlot->ulRegOffset, ulAddrOffset);
338
339        /* Set RDC_desc_x_config */
340        ulRegVal = BRDC_Slot_P_Read32(hSlot, BCHP_RDC_desc_0_config + hSlot->ulRegOffset);
341
342        /* Get trigger select value. */
343        ulTrigSelect = hSlot->hRdc->aTrigInfo[eRDCTrigger].ulTrigVal;
344
345        if( ExecuteOnTrigger )
346        {
347                ulRegVal &= ~(
348                        BCHP_MASK(RDC_desc_0_config, enable         ) |
349                        BCHP_MASK(RDC_desc_0_config, repeat         ) |
350                        BCHP_MASK(RDC_desc_0_config, trigger_select ) |
351                        BCHP_MASK(RDC_desc_0_config, count          ));
352
353                ulRegVal |= (
354                        BCHP_FIELD_DATA(RDC_desc_0_config, enable,         1                          ) |
355                        BCHP_FIELD_DATA(RDC_desc_0_config, repeat,         bRecurring                 ) |
356                        BCHP_FIELD_DATA(RDC_desc_0_config, trigger_select, ulTrigSelect               ) |
357                        BCHP_FIELD_DATA(RDC_desc_0_config, count,          hSlot->hList->ulEntries -1));
358
359                BRDC_Slot_P_Write32(hSlot, BCHP_RDC_desc_0_config + hSlot->ulRegOffset, ulRegVal);
360        }
361        else
362        {
363                /* previously not enabled? */
364                if (!BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, enable))
365                {
366                        /* we are forcing a descriptor that doesn't have a trigger
367                           so we should set the trigger to an undefined value (so
368                           we can later turn on the enable) and turn off the repeat so this
369                           slot is executed only once */
370                        /* Get trigger select value. */
371                        ulTrigSelect = hSlot->hRdc->aTrigInfo[BRDC_Trigger_UNKNOWN].ulTrigVal;
372
373                        ulRegVal &= ~(
374                                BCHP_MASK(RDC_desc_0_config, trigger_select ) |
375                                BCHP_MASK(RDC_desc_0_config, repeat         ));
376                        ulRegVal |= (
377                                BCHP_FIELD_DATA(RDC_desc_0_config, trigger_select, ulTrigSelect) |
378                                BCHP_FIELD_DATA(RDC_desc_0_config, repeat,         0));
379                }
380
381                /* enable descriptor and update count */
382                ulRegVal &= ~(
383                        BCHP_MASK(RDC_desc_0_config, enable ) |
384                        BCHP_MASK(RDC_desc_0_config, count  ));
385
386                ulRegVal |= (
387                        BCHP_FIELD_DATA(RDC_desc_0_config, enable, 1                          ) |
388                        BCHP_FIELD_DATA(RDC_desc_0_config, count,  hSlot->hList->ulEntries - 1));
389
390                BRDC_Slot_P_Write32(hSlot, BCHP_RDC_desc_0_config + hSlot->ulRegOffset, ulRegVal);
391
392                /* Set RDC_desc_x_immediate */
393                ulRegVal = BCHP_FIELD_DATA(RDC_desc_0_immediate, trigger, 1 );
394                BRDC_Slot_P_Write32(hSlot, BCHP_RDC_desc_0_immediate + hSlot->ulRegOffset, ulRegVal);
395        }
396
397        BDBG_LEAVE(BRDC_Slot_P_Write_Registers_isr);
398        return BERR_SUCCESS;
399
400}
401
402/***************************************************************************
403Summary:
404        Isr function to acquire semaphore from slot.
405
406Description:
407
408Input:
409        hSlot - The slot to acquire semaphore from.
410        ulRegOffset - Offset to the slot's registers.
411
412Output:
413
414Returns:
415
416****************************************************************************/
417BERR_Code BRDC_P_AcquireSemaphore_isr
418(
419        BRDC_Handle hRdc,
420        BRDC_SlotId eSlotId
421)
422{
423        int      iDMABusy = 0;
424        bool     bDMABusy;
425        uint32_t ulRegVal, ulRegOffset;
426
427        /* calculate offset for this slot */
428        ulRegOffset = 16 * (eSlotId - BRDC_SlotId_eSlot0);
429
430        /* If DMA is not busy, this read will acquire the semaphore */
431        ulRegVal = BRDC_P_Read32(hRdc, BCHP_RDC_desc_0_lock + ulRegOffset);
432
433        /* All RDC_desc_x_lock bit definitions are same */
434        bDMABusy = (bool)BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_lock, semaphore);
435
436        /* Wait to get semaphore to lock DMA */
437        while( bDMABusy )
438        {
439                /* PR13108: This is the very rare case that we can't acquire
440                 * semaphore for the slot.
441                 * The common belief is that a RUL execution time should be maxed by
442                 * 1/2000th of a second. Therefore the max delay caused by a loss of
443                 * semaphore should be the same plus some delta just in case.
444                 * In this case, choose total dealy = 1/2000 sec + 100 us (delta) =
445                 * 600 us, for BRDC_P_SEMAPHORE_ACQUIRE_DELAY tries. */
446                BKNI_Delay(1);
447
448                if (BRDC_P_SEMAPHORE_ACQUIRE_DELAY == ++iDMABusy)
449                {
450                        /* could not acquire semaphore within a reasonable amount of time */
451                        BDBG_ERR(( "Cannot acquire semaphore" ));
452                        BRDC_P_DumpSlot(hRdc, eSlotId);
453                        return BERR_TRACE(BERR_TIMEOUT);
454                }
455
456                /* If DMA is not busy, this read will acquire the semaphore */
457                ulRegVal = BRDC_P_Read32(hRdc, BCHP_RDC_desc_0_lock + ulRegOffset);
458
459                /* All RDC_desc_x_lock bit definitions are same */
460                bDMABusy = (bool)BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_lock, semaphore);
461
462        }
463
464        /* semaphore acquired */
465        return BERR_SUCCESS;
466}
467
468/***************************************************************************
469Summary:
470        Release semaphore to hardware
471
472Description:
473
474Input:
475        hSlot - The slot to release semaphore.
476        ulRegOffset - Offset to the slot's registers.
477
478Output:
479
480Returns:
481
482****************************************************************************/
483void BRDC_P_ReleaseSemaphore_isr
484(
485        BRDC_Handle hRdc,
486        BRDC_SlotId eSlotId
487)
488{
489        uint32_t ulRegVal;
490        uint32_t ulRegOffset;
491
492        /* calculate offset for this slot */
493        ulRegOffset = 16 * (eSlotId - BRDC_SlotId_eSlot0);
494
495        /* Release semaphore. Write 1 to clear. */
496        ulRegVal = BCHP_MASK(RDC_desc_0_lock, semaphore);
497        BRDC_P_Write32(hRdc, BCHP_RDC_desc_0_lock + ulRegOffset, ulRegVal);
498}
499
500void BRDC_P_DumpSlot
501(
502        BRDC_Handle hRdc,
503        BRDC_SlotId eSlotId
504)
505{
506        uint32_t  ulRegOffset;
507        uint32_t  ulRegVal;
508        uint32_t  ulAddr, *pulAddr;
509        void     *pvAddr;
510        uint32_t  ulCount, ulIndex;
511
512        /* determine offset of registers for this slot */
513        ulRegOffset = 16 * (eSlotId - BRDC_SlotId_eSlot0);
514
515        /* header */
516        BDBG_MSG(("-------------------------------\n"));
517
518        /* read and display address register */
519        ulRegVal = BRDC_P_Read32(hRdc, BCHP_RDC_desc_0_addr + ulRegOffset);
520        ulAddr = BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_addr, addr);
521        BDBG_MSG(("RDC_desc_%d_addr\n"
522                "\taddr: 0x%08x\n",
523                eSlotId,
524                ulAddr ));
525
526        /* read and display config register */
527        ulRegVal = BRDC_P_Read32(hRdc, BCHP_RDC_desc_0_config + ulRegOffset);
528        ulCount = BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, count);
529        BDBG_MSG(("RDC_desc_%d_config\n"
530                "\tcount:           %d\n"
531                "\ttrigger_select:  %d\n"
532                "\trepeat:          %d\n"
533                "\tenable:          %d\n"
534                "\tdone:            %d\n"
535                "\tbusy:            %d\n"
536                "\terror:           %d\n"
537                "\tdropped_trigger: %d\n"
538                "\tlock_rd:         %d\n",
539                eSlotId,
540                ulCount,
541                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, trigger_select),
542                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, repeat),
543                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, enable),
544                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, done),
545                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, busy),
546                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, error),
547                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, dropped_trigger),
548                BCHP_GET_FIELD_DATA(ulRegVal, RDC_desc_0_config, lock_rd)));
549
550        /* contents of RUL */
551        BDBG_MSG(("RUL contents\n"));
552        BMEM_ConvertOffsetToAddress(hRdc->hMem, ulAddr, &pvAddr);
553        pulAddr = (uint32_t *)pvAddr;
554        for (ulIndex=0; ulIndex<=ulCount; ++ulIndex)
555        {
556                BDBG_MSG(("0x%08x\n", *(pulAddr++)));
557        }
558}
559
560/* end of file */
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