source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/hdm/7552/bhdm_priv.h

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1/***************************************************************************
2 *     Copyright (c) 2003-2012, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bhdm_priv.h $
11 * $brcm_Revision: Hydra_Software_Devel/84 $
12 * $brcm_Date: 3/19/12 11:35a $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: Q:/projects/7425/latest/magnum/portinginterface/hdm/7038/bhdm_priv.h $
19 *
20 * Hydra_Software_Devel/84   3/19/12 11:35a rgreen
21 * SW7425-2650: Fix memory leak in HDM PI; Delcare/store supported Video
22 * ID Codes in hdm handlle vs mallocing to build list each time
23 *
24 * Hydra_Software_Devel/83   3/14/12 6:59p vle
25 * SW7425-2515: Remove references to bhdm_cec files
26 *
27 * Hydra_Software_Devel/82   3/1/12 2:50p rgreen
28 * SW7425-2515: Remove unused CEC code which is now located in CEC pi;
29 * Remove CEC from BHDM interrupt table
30 *
31 * Hydra_Software_Devel/81   3/1/12 1:20p rgreen
32 * SW7425-2515: Remove unused CEC code which is now located in CEC pi;
33 * remove CEC EventHandle
34 *
35 * Hydra_Software_Devel/80   2/23/12 10:50a rgreen
36 * SW7125-1146,SW7408-317: Merge changes
37 *
38 * Hydra_Software_Devel/SW7408-317/1   2/21/12 6:33p rgreen
39 * SW7125-1146,SW7408-317: Treat RxSense and HP events separately.  Update
40 * processing of both events
41 *
42 * Hydra_Software_Devel/79   2/9/12 3:59p rgreen
43 * SW7231-345,SW7125-1146,SW7425-2361: Refactor HDMI Power Management;
44 * separate TMDS power from clock
45 *
46 * Hydra_Software_Devel/78   1/27/12 2:10p vle
47 * SW7125-1146: merge to mainline
48 *
49 * Hydra_Software_Devel/SW7125-1146/2   1/26/12 5:35p vle
50 * SW7125-1146: Get RSEN setting at isr vs event time for applicable
51 * platforms
52 *
53 * Hydra_Software_Devel/77   1/23/12 11:25a rgreen
54 * SW7125-1146: Merge Changes
55 *
56 * Hydra_Software_Devel/SW7125-1146/1   1/19/12 2:35p rgreen
57 * SW7125-1146: Enable TMDS at open to fix interrupt issue; Get RSEN
58 * setting at isr vs event time;
59 *
60 * Hydra_Software_Devel/76   1/6/12 6:03p vle
61 * SW7435-11: implement support for check/clearHotplugInterrupt for 7435
62 *
63 * Hydra_Software_Devel/75   1/6/12 2:59p vle
64 * SW7435-11: Add support for 7435
65 *
66 * Hydra_Software_Devel/74   11/22/11 6:01p vle
67 * SW7425-1140: Merge to mainline.  Remove all CEC functionality out of
68 * HDM PI.
69 *
70 * Hydra_Software_Devel/SW7425-1140/2   11/22/11 5:48p vle
71 * SW7425-1140: Add BHDM_CONFIG_CEC_LEGACY_SUPPORT for backward compatible
72 * for CEC legacy platforms.
73 *
74 * Hydra_Software_Devel/SW7425-1140/1   11/16/11 12:16p vle
75 * SW7425-1140: Remove all CEC functionalities out of HDM PI
76 *
77 * Hydra_Software_Devel/73   11/14/11 2:15p rgreen
78 * SW7425-1710: Update BHDM_CONFIG macro usage.  Describe specific
79 * functionality vs chip process
80 *
81 * Hydra_Software_Devel/72   10/11/11 4:50p vle
82 * SW7429-5: Add support for 7429.
83 *
84 * Hydra_Software_Devel/71   6/7/11 6:44p vle
85 * SW7425-532: Add HDMI CEC support for 40nm chip. Use correct CEC
86 * interrupt.
87 *
88 * Hydra_Software_Devel/70   2/17/11 7:38p jtna
89 * SW7420-1141: rework HDMI power management. break public API to allow
90 * for StandbySettings
91 *
92 * Hydra_Software_Devel/69   10/18/10 4:37p vle
93 * SW7420-1177: Add DVO support for 7420
94 *
95 * Hydra_Software_Devel/68   10/7/10 6:47p jtna
96 * SW7420-972: merge hdmi power management
97 *
98 * Hydra_Software_Devel/SW7420-972/1   10/6/10 7:01p jtna
99 * SW7420-972: BCHP_PWR power management for HDM
100 *
101 * Hydra_Software_Devel/67   9/29/10 4:14p vle
102 * SW7422-23: Fix build issues without CEC enable
103 *
104 * Hydra_Software_Devel/66   9/28/10 7:19p vle
105 * SW7422-23: Refactor HDMI code to isolate platform dependent code
106 * furthermore. Add support for 7422 and other 40nm platforms.
107 *
108 * Hydra_Software_Devel/65   9/24/10 5:38p vle
109 * SW7342-238: Take 2 The VEC will only operate double the rate (54Mhz) in
110 * 480p format, not 480i. Make sure audio parameters for all other 27Mhz
111 * pixel clock format are programmed correctly.
112 *
113 * Hydra_Software_Devel/64   9/24/10 2:25p vle
114 * SW7342-238: The VEC will only operate double the rate (54Mhz) in 480p
115 * format, not 480i. Make sure audio parameters for all other 27Mhz pixel
116 * clock format are programmed correctly.
117 *
118 * Hydra_Software_Devel/63   8/27/10 7:48p vle
119 * SW7400-2868: Fix potential EDID parser issue when parsing 3D supports
120 * on the first 16 video descriptor
121 *
122 * Hydra_Software_Devel/62   6/22/10 6:57p vle
123 * SW7405-3994: Add support to parse all Shorthand and additional 3D
124 * Timing/Structure support indication in HDMI 1.4a
125 *
126 * Hydra_Software_Devel/61   6/4/10 6:09p vle
127 * SW7405-3994: Merge to main branch
128 *
129 * Hydra_Software_Devel/SW7405-3994/1   5/14/10 6:12p vle
130 * SW7405-3994: Add support to check for supported 3D formats.
131 *
132 * Hydra_Software_Devel/60   5/26/10 2:48p vle
133 * SW7405-4333: Add support for 40, 65, and 65/1.001 Mhz pixel clock rate
134 *
135 * Hydra_Software_Devel/59   4/23/10 10:43a vle
136 * SW7420-676: merge to main branch
137 *
138 * Hydra_Software_Devel/SW7420-676/1   4/21/10 2:27p vle
139 * SW7420-676: Add API to return supported video info
140 *
141 * Hydra_Software_Devel/58   4/16/10 6:50p vle
142 * SW7420-543: BHDM_InputPixelClock enum should be private
143 *
144 * Hydra_Software_Devel/57   4/2/10 6:40p vle
145 * SW7601-172: Rename to clearly indicate SetGamutMetadataPacket is a
146 * private API.
147 *
148 * Hydra_Software_Devel/56   4/2/10 5:59p rgreen
149 * SW7405-3994: Merge Update HDMI 1.4 parsing for 3D Structure fields in
150 * the VSDB
151 *
152 * Hydra_Software_Devel/SW7401-4363/1   3/5/10 4:11p rgreen
153 * JIRA:SW7405-3994: Update HDMI 1.4 parsing for 3D Structure fields in
154 * the VSDB
155 *
156 * Hydra_Software_Devel/55   3/26/10 4:34p vle
157 * SW7601-172: Merge xvYCC support with Gamut Metadata Packet transmission
158 * from bdvd branch
159 *
160 * Hydra_Software_Devel/54   3/1/10 11:32a rgreen
161 * SW7420-579: Rename DetailedTiming to SupportedDetailTiming to eliminate
162 * confusion when reading code
163 *
164 * Hydra_Software_Devel/53   2/23/10 12:49a vle
165 * SW7420-579: Refactor HDMI PI.
166 *
167 * Hydra_Software_Devel/9   1/8/10 5:19p vle
168 * SW7405-3740: Port changes to 7420, 7468, and other platforms.
169 * Add isr callback to provide immediate notifcation of HP changes vs
170 * waiting for event processing
171 *
172 * Hydra_Software_Devel/8   1/6/10 4:38p vle
173 * SW3548-2670: Centralize all CEC timing configurations
174 *
175 * Hydra_Software_Devel/7   9/23/09 2:15p vle
176 * SW7601-165: Merge changes in bdvd_v3.0 branch to main branch.
177 *
178 * Hydra_Software_Devel/bdvd_v3.0/2   9/2/09 3:31p rbshah
179 * PR16468[DVD]:[ see HiDef-DVD bug tracking system for more info ].
180 * Merged with the latest portinginterface/hdm and syslib/hdcplib files.
181 *
182 * Hydra_Software_Devel/bdvd_v2.0/bdvd_v2.1/2   7/14/09 1:30p rbshah
183 * PR_15413[DVD]:[ see HiDef-DVD bug tracking system for more info ].
184 * Merge work from the HDMI certification branch. Also addresses PR15437
185 * and PR15220 (merged from v2.0). Plus coverity PR15782.
186 *
187 * Hydra_Software_Devel/bdvd_v2.0/bdvd_v2.1/bdvd_hdmi_cert_v2.1/1   7/8/09 12:18p rbshah
188 * Various fixes for Auto Hardware Ri,Pj checking. I2C changes are
189 * temporary. Switch from software to hardware Ri checking by default.
190 *
191 * Hydra_Software_Devel/bdvd_v2.0/bdvd_v2.1/1   4/3/09 6:12p rbshah
192 * PR_13071[DVD]:[ see HiDef-DVD bug tracking system for more info ].  Add
193 * CEC support at the BDVD/Display API. This is really a back port
194 * from bdvd_v2.0 and dev_pr13071 branches.
195 *
196 * Hydra_Software_Devel/6   8/26/09 3:41p vle
197 * SW7405-2670:
198 * Add implementation of interrupt based receiver sense
199 *
200 * Hydra_Software_Devel/5   7/22/09 7:35p vle
201 * PR56776: Prevent HDCP An Timeout
202 *
203 * Hydra_Software_Devel/4   3/9/09 3:21p vle
204 * PR50570, PR50918, PR49277, PR49652, PR52873:
205 * Add API to mute/unmute audio, update pixel repitition support, add
206 * SetPixelDataOverride API for transmission of black video. Merge
207 * changes/updates from bdvd_v2.0 to main branch.
208 *
209 * Hydra_Software_Devel/3   3/3/09 8:23p vle
210 * PR50569: Add HW Ri/Pj checking feature. Merged from bdvd branch after
211 * Rajul's testing effort.
212 *
213 * Hydra_Software_Devel/bdvd_v2.0/2   1/23/09 10:14a rbshah
214 * PR_10346 [ see HiDef-DVD bug tracking system for more info ].  Checkin
215 * code drop from Anthony Le for Auto Ri,Pj feature in the
216 * 7601B0 (Digital Video PR50569).
217 *
218 * This is disabled by default and will be turned on once it has
219 * been tested and soaked.
220 *
221 * Did verify the A0 build!
222 *
223 * Hydra_Software_Devel/bdvd_v2.0/1   1/21/09 11:56a rbshah
224 * PR_10346 [ see HiDef-DVD bug tracking system for more info ].  Enhance
225 * Display/HDMI API to allow application to mute/unmute just
226 * audio (Digital Video PR50570).
227 *
228 * This feature is only available on the 7601B0.
229 * Hydra_Software_Devel/2   12/2/08 11:11a vle
230 * PR49651: Fix CEC compiling issue for 7601/7420
231 *
232 * Hydra_Software_Devel/1   10/9/08 4:40p vle
233 * PR44535: Merge to main Hydra dev. branch
234 *
235 * Hydra_Software_Devel/PR44535/1   8/6/08 7:46p vle
236 * PR44535: Initial version
237 *
238 ***************************************************************************/
239
240#ifndef BHDM_PRIV_H__
241#define BHDM_PRIV_H__
242
243#include "blst_queue.h"
244#include "bhdm_config.h"
245#include "bhdm_hdcp.h"
246#include "bhdm_edid.h"
247
248#include "bchp.h"       /* Chip Info */
249#include "bchp_sun_top_ctrl.h"
250#include "breg_mem.h"   /* Chip register access. */
251#include "bkni.h"       /* Kernel Interface */
252#include "bint.h"       /* Interrupt */
253#include "breg_i2c.h"   /* I2C */
254
255
256#include "bchp_hdmi.h"
257#include "bchp_hdmi_rm.h"  /* HDMI Rate Manager */
258#include "bchp_hdmi_ram.h" /* HDMI Packet RAM */
259#if BHDM_CONFIG_40NM_SUPPORT
260#include "bchp_aon_hdmi_tx.h"
261#include "bchp_hdmi_tx_intr2.h"
262#include "bchp_int_id_hdmi_tx_intr2.h"
263#include "bchp_int_id_aon_pm_l2.h"
264#include "bchp_int_id_aon_l2.h"
265#else
266#include "bchp_hdmi_intr2.h"
267#include "bchp_int_id_hdmi_intr2.h"
268#endif
269
270#if BHDM_CONFIG_65NM_SUPPORT || BHDM_CONFIG_40NM_SUPPORT
271#include "bchp_hdmi_tx_phy.h"
272#endif
273
274#if BHDM_CONFIG_HDMI_1_3_SUPPORT
275#include "bchp_dvp_ht.h"
276#endif
277
278
279#ifdef __cplusplus
280extern "C" {
281#endif
282
283
284#define MAKE_INTR_ENUM(IntName) BHDM_INTR_e##IntName
285#define MAKE_INTR_NAME(IntName) "BHDM_" #IntName
286
287                                                         
288/******************************************************************************
289Summary:
290Enumeration of BHDM_Interrupts
291*******************************************************************************/
292typedef enum
293{
294#if BHDM_CONFIG_DUAL_HPD_SUPPORT
295        /* 00 */ MAKE_INTR_ENUM(HOTPLUG_REMOVED),
296        /* 01 */ MAKE_INTR_ENUM(HOTPLUG_CONNECTED),
297#else
298        /* 00 */ MAKE_INTR_ENUM(HOTPLUG),
299#endif 
300
301        /* 01 */ MAKE_INTR_ENUM(DF_FULL_MINUS),
302        /* 02 */ MAKE_INTR_ENUM(DF_ALMOST_FULL), 
303        /* 03 */ MAKE_INTR_ENUM(DF_EMPTY_MINUS),
304        /* 04 */ MAKE_INTR_ENUM(DF_ALMOST_EMPTY), 
305
306        /* 05 */ MAKE_INTR_ENUM(PKT_WRITE_ERR),
307               
308        /* 07 */ MAKE_INTR_ENUM(HDCP_REPEATER_ERR),
309        /* 08 */ MAKE_INTR_ENUM(HDCP_V_MISMATCH),
310        /* 09 */ MAKE_INTR_ENUM(HDCP_V_MATCH),
311        /* 10 */ MAKE_INTR_ENUM(HDCP_RI),
312        /* 11 */ MAKE_INTR_ENUM(HDCP_AN),
313        /* 12 */ MAKE_INTR_ENUM(PKT_OVERFLOW),
314        /* 13 */ MAKE_INTR_ENUM(HDCP_PJ),
315       
316#if BHDM_CONFIG_HDCP_AUTO_RI_PJ_CHECKING_SUPPORT
317        /* 14 */ MAKE_INTR_ENUM(HDCP_PJ_MISMATCH),
318        /* 15 */ MAKE_INTR_ENUM(HDCP_RI_A_MISMATCH),
319        /* 16 */ MAKE_INTR_ENUM(HDCP_RI_B_MISMATCH),
320#endif
321
322#if BHDM_CONFIG_RECEIVER_SENSE_SUPPORT
323        /* 17 */ MAKE_INTR_ENUM(RSEN),
324#endif 
325        /* 18 */ MAKE_INTR_ENUM(LAST)
326} BHDM_P_InterruptMask ;
327
328
329/******************************************************************************
330Summary:
331Enumerated Type of pre-configured Video Rates from the VEC to the HDMI core
332
333Description:
334The HDMI Rate Manager must be configured to match the input clock to the HDMI
335core.  This table enumerates those types
336
337*******************************************************************************/
338typedef enum
339{
340        /* 8bit standard mode */
341        BHDM_PixelClock_e25_2                   ,
342        BHDM_PixelClock_e25_2_DIV_1_001 ,
343       
344        BHDM_PixelClock_e27                     ,
345        BHDM_PixelClock_e27_MUL_1_001   ,
346
347#if BHDM_CONFIG_HDMI_1_3_SUPPORT
348        /**************************
349        * This entry is specific for 480p format.
350        * Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format
351        ***********************/
352        BHDM_PixelClock_e27_480p = BHDM_PixelClock_e27, 
353        BHDM_PixelClock_e27_MUL_1_001_480p = BHDM_PixelClock_e27_MUL_1_001,
354#endif
355
356        BHDM_PixelClock_e54                     , /* 2 times pixel repetition 2x27 Mhz */
357        BHDM_PixelClock_e54_MUL_1_001   ,
358       
359        BHDM_PixelClock_e74_25                  ,
360        BHDM_PixelClock_e74_25_DIV_1_001,
361
362#if BHDM_CONFIG_HDMI_1_3_SUPPORT
363        BHDM_PixelClock_e108                     , /* 4 times pixel repetition 4x27 Mhz */
364        BHDM_PixelClock_e108_MUL_1_001   ,
365
366        BHDM_PixelClock_e148_5                  ,
367        BHDM_PixelClock_e148_5_DIV_1_001,
368
369
370        /* 10bit deep color mode */
371        BHDM_PixelClock_e31_5,
372        BHDM_PixelClock_e31_5_DIV_1_001,
373       
374        BHDM_PixelClock_e33_75,
375        BHDM_PixelClock_e33_75_MUL_1_001,
376
377        /**************************
378        * This entry is specific for 480p format.
379        * Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format
380        ***********************/
381        BHDM_PixelClock_e33_75_480p = BHDM_PixelClock_e33_75, /* 27Mhz x 1.25 */
382        BHDM_PixelClock_e33_75_MUL_1_001_480p = BHDM_PixelClock_e33_75_MUL_1_001,
383
384        BHDM_PixelClock_e67_5                     , /* 2 times pixel repetition 2x33.75 Mhz */
385        BHDM_PixelClock_e67_5_MUL_1_001   ,
386
387        BHDM_PixelClock_e92_8125,
388        BHDM_PixelClock_e92_8125_DIV_1_001,
389
390        BHDM_PixelClock_e135                     , /* 4 times pixel repetition 4x33.75 Mhz */
391        BHDM_PixelClock_e135_MUL_1_001   ,
392
393        BHDM_PixelClock_e185_625,
394        BHDM_PixelClock_e185_625_DIV_1_001,
395
396
397        /* 12bit deep color mode */
398        BHDM_PixelClock_e37_8,
399        BHDM_PixelClock_e37_8_DIV_1_001,
400
401        BHDM_PixelClock_e40_5,
402        BHDM_PixelClock_e40_5_MUL_1_001,
403
404        /**************************
405        * This entry is specific for 480p format.
406        * Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format
407        ***********************/
408        BHDM_PixelClock_e40_5_480p = BHDM_PixelClock_e40_5,                     /* 27Mhz x 1.5 */
409        BHDM_PixelClock_e40_5_MUL_1_001_480p = BHDM_PixelClock_e40_5_MUL_1_001,
410
411        BHDM_PixelClock_e81                     , /* 2 times pixel repetition 2x40.5 Mhz */
412        BHDM_PixelClock_e81_MUL_1_001   ,
413
414        BHDM_PixelClock_e111_375,
415        BHDM_PixelClock_e111_375_DIV_1_001,
416
417        BHDM_PixelClock_e162                     , /* 4 times pixel repetition 4x40.5 Mhz */
418        BHDM_PixelClock_e162_MUL_1_001   ,
419
420        BHDM_PixelClock_e222_75,
421        BHDM_PixelClock_e222_75_DIV_1_001,
422#endif
423
424        /* DVI/PC/custom clock rates */
425       
426        BHDM_PixelClock_e40,
427        BHDM_PixelClock_e65,
428        BHDM_PixelClock_e65_DIV_1_001,
429
430        BHDM_PixelClock_e60_375,
431        BHDM_PixelClock_e74_375,
432        BHDM_PixelClock_e64,
433
434        BHDM_PixelClock_eCUSTOM_1366x768p_50,   /* Custom 1366x768 mode @ 60 */
435        BHDM_PixelClock_eCUSTOM_1366x768p_5994, /* Custom 1366x768 mode @ 59.94 */
436        BHDM_PixelClock_eCUSTOM_1366x768p_60,   /* Custom 1366x768 mode @ 60 */
437
438
439        BHDM_PixelClock_eCount
440} BHDM_InputPixelClock ;
441
442#define BHDM_PixelClock_eUnused                 BHDM_PixelClock_eCount
443#define BHDM_PixelClock_eDviClockRate   BHDM_PixelClock_e54
444
445
446typedef struct BHDM_EDID_P_VideoDescriptor
447{
448        BLST_Q_ENTRY(BHDM_EDID_P_VideoDescriptor ) link ;
449        BFMT_VideoFmt eVideoFmt  ; /* BCM Video Format */
450        uint8_t VideoIdCode ;      /* CEA-861B Video Id Code */
451        uint8_t NativeFormat ;     /* Native Format for Monitor */
452} BHDM_EDID_P_VideoDescriptor ;
453
454
455/* declaration of the head type for Video Descriptor list */
456typedef struct BHDM_EDID_VideoDescriptorHead BHDM_EDID_VideoDescriptorHead;
457BLST_Q_HEAD(BHDM_EDID_VideoDescriptorHead, BHDM_EDID_P_VideoDescriptor );
458
459
460typedef struct _BHDM_EDID_DATA_
461{
462        uint8_t Block[BHDM_EDID_BLOCKSIZE] ;
463        uint8_t CachedBlock ;
464       
465        BHDM_EDID_BasicData        BasicData ;
466        BHDM_EDID_MonitorRange MonitorRange ;
467        uint8_t                MonitorName[BHDM_EDID_DESC_ASCII_STRING_LEN] ;
468        BHDM_EDID_DetailTiming SupportedDetailTimings[2] ; /* keep two most preferred timings */
469        uint8_t                SupportedDetailTimingsIn1stBlock ;
470        uint8_t                RxHasHdmiSupport ;
471        BHDM_EDID_RxVendorSpecificDB RxVSDB ;
472       
473        BHDM_EDID_VideoDescriptorHead   VideoDescriptorList ;
474        uint8_t NumBcmSupportedVideoDescriptors;
475        uint8_t BcmSupportedVideoIdCodes[BHDM_EDID_MAX_CEA_VIDEO_ID_CODES] ;
476       
477        uint16_t First16VideoDescriptorsMask;
478       
479        uint8_t DescriptorHeader[BHDM_EDID_DESC_HEADER_LEN] ;
480       
481        /* keep track of Broadcom Audio/Video Formats supported by the EDID/monitor */
482        bool BcmVideoFormatsChecked ;
483        bool BcmSupportedVideoFormats[BFMT_VideoFmt_eMaxCount] ;
484
485        BHDM_EDID_3D_Structure_ALL BcmSupported3DStructureAll;
486        bool Bcm3DFormatsChecked ;
487        BHDM_EDID_3D_Structure_ALL BcmSupported3DFormats[BFMT_VideoFmt_eMaxCount] ;
488       
489        bool BcmAudioFormatsChecked ;
490        BHDM_EDID_AudioDescriptor BcmSupportedAudioFormats[BAVC_AudioFormat_eMaxCount] ;
491
492       
493        BHDM_EDID_ColorimetryDataBlock ColorimetryData;
494       
495} BHDM_EDID_DATA ;
496
497typedef enum
498{
499        BHDM_EDID_STATE_eInvalid,
500        BHDM_EDID_STATE_eInitialize,
501        BHDM_EDID_STATE_eProcessing,
502        BHDM_EDID_STATE_eOK
503} BHDM_EDID_STATE;
504
505
506/*******************************************************************************
507Private HDMI Handle Declaration
508*******************************************************************************/
509typedef struct BHDM_P_Handle
510{
511        BCHP_Handle   hChip ;
512        BREG_Handle   hRegister ;
513        BINT_Handle   hInterrupt ;
514        BREG_I2C_Handle hI2cRegHandle ;
515        BINT_CallbackHandle hCallback[MAKE_INTR_ENUM(LAST)] ;
516
517        BKNI_EventHandle BHDM_EventHDCP ;
518        BKNI_EventHandle BHDM_EventHDCPRiValue ;
519        BKNI_EventHandle BHDM_EventHDCPPjValue ;
520        BKNI_EventHandle BHDM_EventHDCPRepeater;       
521        BKNI_EventHandle BHDM_EventRxSense ;   
522        BKNI_EventHandle BHDM_EventHotPlug ;
523        BKNI_EventHandle BHDM_EventRAM ;   /* debugging events */
524        BKNI_EventHandle BHDM_EventFIFO ;  /* debugging events */
525
526        BHDM_Settings DeviceSettings ;
527
528        /* moved from Device Settings */       
529        BHDM_InputPixelClock    eInputPixelClock ;
530
531        /* selected output port DVO12/DVO24/HDMI ; set once */
532        BHDM_OutputPort eOutputPort ;
533
534        uint8_t RxDeviceAttached ;
535        bool tmdsEnabled;
536        bool AvMuteState ;
537        bool AudioMuteState ;
538        bool hotplugInterruptFired;
539        bool rxSensePowerDetected ;
540
541        uint8_t PacketBytes[BHDM_NUM_PACKET_BYTES] ;
542
543        bool standby; /* true if in standby */
544        bool enableWakeup; /* true if standby wakeup from CEC is enabled */
545
546   
547        /******************/
548        /* HDCP variables */
549        /******************/
550        uint32_t HDCP_RiCount ;
551        uint8_t HDCP_PjMismatchCount ;
552
553        uint8_t HDCP_AutoRiMismatch_A;
554        uint8_t HDCP_AutoRiMismatch_B;
555        uint8_t HDCP_AutoPjMismatch;
556
557        uint16_t 
558                HDCP_Ri2SecsAgo, 
559                HDCP_Ri4SecsAgo,
560                HDCP_Ri6SecsAgo ;
561
562        uint16_t 
563                HDCP_TxRi, 
564                HDCP_RxRi ;
565               
566        uint8_t
567                HDCP_TxPj,
568                HDCP_RxPj ;
569
570        uint8_t HDCP_AuthenticatedLink ;
571
572        BHDM_HDCP_Version
573                HdcpVersion ;  /* HDCP Version to Use */
574
575        uint8_t RxBCaps ;
576        uint16_t RxStatus ;
577       
578        /* store copy of Attached KSV and Repeater KSV List */
579        uint8_t HDCP_RxKsv[BHDM_HDCP_KSV_LENGTH] ;
580       
581        uint8_t HDCP_RepeaterDeviceCount ;
582        uint8_t *HDCP_RepeaterKsvList ;
583
584        BHDM_HDCP_OPTIONS HdcpOptions  ;
585        bool bHdcpAnRequest ;
586        bool bAutoRiPjCheckingEnabled  ;
587        uint8_t AbortHdcpAuthRequest ;
588       
589       
590        /******************/
591        /* EDID variables */
592        /******************/
593        BHDM_EDID_STATE edidStatus;
594        BHDM_EDID_DATA AttachedEDID ;
595
596#if BHDM_CONFIG_PLL_KICKSTART_WORKAROUND
597        uint32_t uiPllKickStartCount ;
598#endif
599
600        BHDM_CallbackFunc pfHotplugChangeCallback ;
601        void *pvHotplugChangeParm1 ;
602        int iHotplugChangeParm2 ;
603
604#if BHDM_CONFIG_RECEIVER_SENSE_SUPPORT
605        BHDM_CallbackFunc pfRxSenseChangeCallback ;
606        void *pvRxSenseChangeParm1 ;
607        int iRxSenseChangeParm2 ;
608#endif
609
610 } BHDM_P_Handle ;
611
612
613/**********************************
614 *      PRIVATE FUNCTIONS
615 **********************************/
616
617/******************************************************************************
618Summary:
619Handle interrupts from the HDMI core.
620
621Description:
622Interrupts received from the HDMI core must be handled.  The following
623is a list of possible interrupts.
624
625        o  HDCP_PJ_MISMATCH_INTR
626        o  HDCP_RI_A_MISMATCH_INTR
627        o  HDCP_RI_B_MISMATCH_INTR
628
629        o  HDCP_PJ_INTR
630
631        o  PKT_OVERFLOW_INTR
632
633        o  HDCP_AN_READY_INTR
634        o  HDCP_RI_INTR
635        o  HDCP_V_MATCH_INTR
636        o  HDCP_V_MISMATCH_INTR
637        o  HDCP_REPEATER_ERR_INTR
638
639        o  CEC_INTR
640
641        o  ILLEGAL_WRITE_TO_ACTIVE_RAM_PACKET_INTR
642
643        o  DRIFT_FIFO_ALMOST_EMPTY_INTR
644        o  DRIFT_FIFO_EMPTY_MINUS_INTR
645        o  DRIFT_FIFO_ALMOST_FULL_INTR
646        o  DRIFT_FIFO_FULL_MINUS_INTR
647
648        o  HOTPLUG_INTR
649
650Input:
651        pParameter - pointer to interrupt specific information BHDM_Open.
652
653Output:
654        <None>
655       
656Returns:
657        <None>
658
659See Also:
660
661*******************************************************************************/
662void BHDM_P_HandleInterrupt_isr
663(
664        void *pParam1,                                          /* Device channel handle */
665        int parm2                                                       /* not used */
666) ;
667                                                               
668#if BHDM_CONFIG_DVO_SUPPORT
669BERR_Code BHDM_DVO_P_EnableDvoPort(
670        BHDM_Handle hHDMI,              /* [in] HDMI handle */
671        BHDM_OutputFormat eOutputFormat /* [in] format to use on Output Port */
672) ;
673#endif
674
675void BHDM_P_ConfigureInputAudioFmt(
676        BHDM_Handle hHDMI,                                                      /* [in] HDMI handle */
677        BAVC_HDMI_AudioInfoFrame *stAudioInfoFrame      /* [in] audio Info Frame settings */
678) ;
679
680BERR_Code BHDM_P_WritePacket(
681        BHDM_Handle hHDMI, 
682        BHDM_Packet PhysicalHdmiRamPacketId,
683        uint8_t PacketType, 
684        uint8_t PacketVersion, 
685        uint8_t PacketLength, 
686        uint8_t *PacketBytes
687) ;
688
689void BHDM_P_VideoFmt2CEA861Code(
690        BFMT_VideoFmt eVideoFmt, 
691        BFMT_AspectRatio eAspectRatio, 
692        BAVC_HDMI_PixelRepetition ePixelRepetition, 
693        uint8_t *VideoID
694) ;
695
696
697#if BHDM_CONFIG_HDMI_1_3_SUPPORT
698BERR_Code BHDM_P_SetGamutMetadataPacket(
699        BHDM_Handle hHDMI               /* [in] HDMI Handle */
700) ;
701
702BERR_Code BHDM_P_ConfigurePhy(
703        BHDM_Handle hHDMI,                              /* [in] HDMI handle */
704        BHDM_Settings *NewHdmiSettings  /* [in] New HDMI settings */
705);
706#endif
707
708void BHDM_P_ResetHdmiCore (BHDM_Handle hHDMI);
709
710void BHDM_P_PowerOnPhy (BHDM_Handle hHDMI);
711
712void BHDM_P_SetPreEmphasisMode (
713        BHDM_Handle hHDMI, 
714        uint8_t uValue, 
715        uint8_t uDriverAmp
716);
717
718BERR_Code BHDM_P_GetPreEmphasisConfiguration (
719        BHDM_Handle hHDMI,
720        BHDM_PreEmphasis_Configuration *stPreEmphasisConfig
721);
722
723
724BERR_Code BHDM_P_SetPreEmphasisConfiguration(
725        BHDM_Handle hHDMI,
726        BHDM_PreEmphasis_Configuration *stPreEmphasisConfig
727);
728
729void BHDM_P_GetReceiverSense(
730        BHDM_Handle hHDMI, 
731        uint8_t *ReceiverSense
732) ;
733
734void BHDM_P_ClearHotPlugInterrupt(
735   BHDM_Handle hHDMI            /* [in] HDMI handle */
736);
737
738void BHDM_P_CheckHotPlugInterrupt(
739        BHDM_Handle hHDMI,               /* [in] HDMI handle */
740        uint8_t *bHotPlugInterrupt      /* [out] Interrupt asserted or not */
741);
742
743void BHDM_P_RxDeviceAttached(
744        BHDM_Handle hHDMI,               /* [in] HDMI handle */
745        uint8_t *bDeviceAttached        /* [out] Device Attached Status  */
746) ;
747
748#if BHDM_CONFIG_DEBUG_FIFO
749BERR_Code BHDM_P_EnableFIFOInterrupts(
750        BHDM_Handle hHDMI, bool on) ;
751#endif
752
753void BHDM_P_EnableTmdsOutput_isr(
754        BHDM_Handle hHDMI, bool bEnableTmdsOutput) ;
755
756
757#ifdef __cplusplus
758}
759#endif
760 
761#endif /* BHDM_PRIV_H__ */
762/* end bhdm_priv.h */
763
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