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bvbi_ve.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_ve.c $
11	* $brcm_Revision: Hydra_Software_Devel/27 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_ve.c $
19	*
20	* Hydra_Software_Devel/27 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/26 2/20/12 12:56p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/25 11/18/11 1:04p darnstein
28	* SW7125-1163: last check-in was not consistent with chips that lack ITU-
29	* R 656 digital video output.
30	*
31	* Hydra_Software_Devel/24 11/17/11 4:50p darnstein
32	* SW7125-1163: disconnect unused crossbar entries every time.
33	*
34	* Hydra_Software_Devel/23 10/28/11 2:40p darnstein
35	* SW7435-14: port to 7435. Same software behavior as for 7425.
36	*
37	* Hydra_Software_Devel/22 9/9/11 7:12p darnstein
38	* SW7429-15: trivial adaptation to 7429 chipset.
39	*
40	* Hydra_Software_Devel/21 6/14/11 2:28p darnstein
41	* SWDTV-7525: back out previous check-in.
42	*
43	* Hydra_Software_Devel/20 6/13/11 4:30p darnstein
44	* SWDTV-7525: trivially add support for 35330 chipset.
45	*
46	* Hydra_Software_Devel/19 3/24/11 5:25p darnstein
47	* SWDTV-6195: Add references to new 35233 chipset.
48	*
49	* Hydra_Software_Devel/18 1/12/11 6:15p darnstein
50	* SW3548-3123: adjustment for 35125 and 35230 chipsets.
51	*
52	* Hydra_Software_Devel/17 1/12/11 4:42p darnstein
53	* SW3548-3123: New function BVBI_Encode_GetInterruptName().
54	*
55	* Hydra_Software_Devel/16 10/1/10 2:43p darnstein
56	* SW7422-46: Adapt to 7422 and 7425 chipsets.
57	*
58	* Hydra_Software_Devel/14 4/26/10 1:05p darnstein
59	* SW7125-274: previous fix did not work.
60	*
61	* Hydra_Software_Devel/13 4/13/10 2:06p darnstein
62	* SW7125-274: Coverity problem resolved with conventional comment. Any
63	* other solution would be complex.
64	*
65	* Hydra_Software_Devel/12 12/21/09 7:01p darnstein
66	* SW7550-120: Add support for SECAM variants.
67	*
68	* Hydra_Software_Devel/11 11/24/09 4:34p darnstein
69	* SW35230-16: first cut at 35230 support.
70	*
71	* Hydra_Software_Devel/10 11/16/09 5:58p darnstein
72	* SW7468-24: first step towards support of 7468 chipset.
73	*
74	* Hydra_Software_Devel/9 8/25/09 2:57p darnstein
75	* SW7340-30: fix silly error in counting SCTEE cores.
76	*
77	* Hydra_Software_Devel/8 8/21/09 2:38p darnstein
78	* PR47900: port to new 7125 chipset.
79	*
80	* Hydra_Software_Devel/7 6/24/09 5:39p darnstein
81	* PR56342: BVBI compiles for 7550 chipset now.
82	*
83	* Hydra_Software_Devel/6 6/24/09 4:58p darnstein
84	* PR56290: BVBI now compiles for 7342 chipset.
85	*
86	* Hydra_Software_Devel/5 6/24/09 4:38p darnstein
87	* PR56289: BVBI compiles for 7340 chipset now.
88	*
89	* Hydra_Software_Devel/4 12/11/08 4:22p darnstein
90	* PR45819: program VBI_ENC and VEC_CFG cores.
91	*
92	* Hydra_Software_Devel/3 12/5/08 11:21a darnstein
93	* PR45819: these functions compile, but do not work properly.
94	*
95	* Hydra_Software_Devel/2 12/4/08 6:07p darnstein
96	* PR45819: 7420 software will now compile, but not link.
97	*
98	* Hydra_Software_Devel/2 12/3/08 7:58p darnstein
99	* PR45819: New, more modular form of most BVBI source files.
100	*
101	* Hydra_Software_Devel/43 7/17/08 8:45p darnstein
102	* PR44539: compilation now possible for 7601.
103	*
104	* Hydra_Software_Devel/42 6/6/08 5:36p darnstein
105	* PR38956: compile in support for SCTE and AMOL in 93548.
106	*
107	* Hydra_Software_Devel/41 4/28/08 7:49p darnstein
108	* PR38956: CGMS-B encoding ready for bring-up. Need accurate register
109	* settings for tuning.
110	*
111	* Hydra_Software_Devel/40 4/15/08 3:17p darnstein
112	* PR41844: increase delay before VEC VBI interrupts fire. The new
113	* settings might have to be refined further.
114	*
115	* Hydra_Software_Devel/39 12/4/07 1:20p darnstein
116	* PR36897: VBI software is ready for testing with 97335 chipset.
117	*
118	* Hydra_Software_Devel/38 10/31/07 3:50p darnstein
119	* PR34528: BVBI is ready for testing on 7325.
120	*
121	* Hydra_Software_Devel/37 10/10/07 8:10p darnstein
122	* PR35440: Some RDB adaptations were still not correct.
123	*
124	* Hydra_Software_Devel/36 10/10/07 6:08p darnstein
125	* PR35440: Some RDB adaptations were not correct.
126	*
127	* Hydra_Software_Devel/35 9/11/07 6:03p darnstein
128	* PR25708: Fix ClearCase merge errors. More to come.
129	*
130	* Hydra_Software_Devel/34 9/11/07 5:17p darnstein
131	* PR25708: First release of SCTE encoder software.
132	*
133	* Hydra_Software_Devel/24 10/31/06 6:19p darnstein
134	* PR15780: correct a typo in initializing for AMOL encoding.
135	*
136	* Hydra_Software_Devel/23 9/13/06 6:34p darnstein
137	* PR21688: Can now compile for 97118-A0 chipset. Correct operation is not
138	* guaranteed.
139	*
140	* Hydra_Software_Devel/22 8/18/06 6:51p darnstein
141	* PR23178: basic compile on 93563 is possible.
142	*
143	* Hydra_Software_Devel/33 6/26/07 11:07a darnstein
144	* PR32462: Update "alias central" wankage to account for 7400-C0 RDB
145	* creative writing efforts.
146	*
147	* Hydra_Software_Devel/32 6/6/07 12:49p darnstein
148	* PR30411: multi-line closed caption encoding is ready for test.
149	*
150	* Hydra_Software_Devel/31 4/20/07 3:35p darnstein
151	* PR29723: Compilation for 7405 chipset.
152	*
153	* Hydra_Software_Devel/30 3/6/07 5:32p darnstein
154	* PR28456: Undefined macros prevented compilation for VxWorks on 7400-B0.
155	* I don't understand why compilation worked for ANY tool chain.
156	*
157	* Hydra_Software_Devel/28 2/26/07 2:28p darnstein
158	* PR25990: Some minor changes were required for compiling on 7400-B0.
159	*
160	* Hydra_Software_Devel/27 1/2/07 4:19p darnstein
161	* PR26872: Mechanically add SECAM to all cases where PAL formats are
162	* accepted.
163	*
164	* Hydra_Software_Devel/26 12/14/06 7:19p darnstein
165	* PR25990: Can compile for BCM97400-B0 now.
166	*
167	* Hydra_Software_Devel/25 11/16/06 4:43p darnstein
168	* PR25668: Mechanical changes to support the 97403 chipset.
169	*
170	* Hydra_Software_Devel/24 10/31/06 6:19p darnstein
171	* PR15780: correct a typo in initializing for AMOL encoding.
172	*
173	* Hydra_Software_Devel/23 9/13/06 6:34p darnstein
174	* PR21688: Can now compile for 97118-A0 chipset. Correct operation is not
175	* guaranteed.
176	*
177	* Hydra_Software_Devel/22 8/18/06 6:51p darnstein
178	* PR23178: basic compile on 93563 is possible.
179	*
180	* Hydra_Software_Devel/21 5/12/06 11:49a darnstein
181	* PR20429: Program the bits for AMOL encoder core.
182	*
183	* Hydra_Software_Devel/20 3/20/06 1:08p darnstein
184	* PR19719: After changing BCHP_VBI_ENC_PRIM_Control (indirectly), poll
185	* register until it has really changed. This enforces the one transition
186	* that is critical to this PR: when disabling a VBI encoder core, the
187	* appropriate bit in BCHP_VBI_ENC_PRIM_Control must be zeroed before the
188	* individual VBI core is disabled.
189	*
190	* Hydra_Software_Devel/19 1/18/06 2:19p darnstein
191	* PR19133: Fix two problems that were preventing VPS output.
192	*
193	* Hydra_Software_Devel/18 10/21/05 7:11p darnstein
194	* PR17732: Gemstar encoder can output a waveform, but I can't make it
195	* change yet.
196	*
197	* Hydra_Software_Devel/17 9/23/05 2:47p darnstein
198	* PR13750: Proper use of BERR_TRACE and BERR_CODEs.
199	*
200	* Hydra_Software_Devel/16 8/22/05 8:11p darnstein
201	* PR16057: To support many different chips, use private #defines that
202	* specify number of VECs, VDECs, and (separately) pass-through VECs.
203	*
204	* Hydra_Software_Devel/15 7/22/05 3:53p darnstein
205	* PR15630, PR16218: removed chip-dependency from bavc.h
206	*
207	* Hydra_Software_Devel/14 7/19/05 3:06p darnstein
208	* PR 15630: Use scratch register defined in bavc.h. Writing to this
209	* register will cause the BVDC module to write to VBI_ENC_aaa_CONTROL
210	* register at the next field trigger, using a RUL.
211	*
212	* Hydra_Software_Devel/13 5/26/05 3:29p jasonh
213	* PR 9338: Added some more comments to describe reason behind critical
214	* section.
215	*
216	* Hydra_Software_Devel/12 3/17/05 7:39p darnstein
217	* PR 14472: Eliminate references to secondary VEC if chip is 3560.
218	*
219	* Hydra_Software_Devel/11 3/9/05 3:43p darnstein
220	* PR 14383: Fix errors in BVBI_P_VE_Enc_Program(). Discovered by Perrier
221	* at the source.
222	*
223	* Hydra_Software_Devel/10 7/16/04 7:07p darnstein
224	* PR 9080: merge in 656 input and output work. Some testing and debugging
225	* remains to be done.
226	*
227	* Hydra_Software_Devel/I656/2 7/15/04 3:56p darnstein
228	* Access to registers BCHP_VBI_ENC_PRIM_Control and
229	* BCHP_VBI_ENC_SEC_Control are now in a critical section. This is
230	* because VDC code can also access this register at initialization time.
231	*
232	* Hydra_Software_Devel/I656/1 6/28/04 1:09p darnstein
233	* 656 output is ready for testing.
234	*
235	* Hydra_Software_Devel/9 6/21/04 3:14p darnstein
236	* PR 9080: The interrupt for VBI encoding occurs now occurs about 10
237	* lines into the active video area. I found this to be necessary.
238	* Otherwise, the teletext encoder will still be busy encoding the
239	* previous field of data when the interrupt fires.
240	*
241	* Hydra_Software_Devel/8 5/6/04 6:16p darnstein
242	* PR 9080: choose video line for interrupt, even if no VBI data is to be
243	* processed. Useful for testing.
244	*
245	* Hydra_Software_Devel/7 4/2/04 6:42p darnstein
246	* PR 9080: Allow NTSC-J video format.
247	*
248	* Hydra_Software_Devel/6 3/4/04 4:30p darnstein
249	* PR 9080: add support for HDTV video formats.
250	*
251	* Hydra_Software_Devel/5 2/27/04 6:09p darnstein
252	* PR 9080: handle ALL of the PAL formats.
253	*
254	* Hydra_Software_Devel/4 2/19/04 2:52p darnstein
255	* PR 9493: Use new PAL format enums.
256	*
257	* Hydra_Software_Devel/3 1/20/04 1:20p darnstein
258	* PR 9338: Don't fiddle with VBI_ENC_xxx_Control registers. The VDC
259	* module owns them now.
260	*
261	* Hydra_Software_Devel/2 1/15/04 4:31p darnstein
262	* PR 9080: remove some debugging code.
263	*
264	* Hydra_Software_Devel/1 12/19/03 4:51p darnstein
265	* PR 9080: Initial version
266	*
267	***************************************************************************/
268
269	/* For bavc.h. This is a bit of an ugly hack. */
270	#include "bchp_gfd_0.h"
271	#include "bchp_gfd_1.h"
272	#include "bstd.h" /* standard types */
273	#include "bint.h"
274	#include "bdbg.h" /* Dbglib */
275	#include "bvbi.h" /* VBI processing, this module. */
276	#include "bkni.h" /* For critical sections */
277	#include "bvbi_priv.h" /* VBI internal data structures */
278	#include "bchp_vbi_enc.h" /* RDB info for VBI_ENC registers */
279	#include "bchp_int_id_video_enc_intr2.h"
280
281	/* Older chips. This should not have to be modified for newer ones */
282	#if (BCHP_CHIP == 3548) \|\| (BCHP_CHIP == 3556)
283	#else
284	#define P_HAS_MODULAR_VEC (1)
285	#endif
286
287	BDBG_MODULE(BVBI);
288
289	/* This will make code more legible, in special cases. Like, chipsets that do
290	* not support 656 output.
291	*/
292	#if (BVBI_P_NUM_CCE_656 == 0)
293	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_CCE_ANCIL_0 0xFFFFFFFF
294	#endif
295	#if (BVBI_P_NUM_WSE_656 == 0)
296	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_WSE_ANCIL_0 0xFFFFFFFF
297	#endif
298	#if (BVBI_P_NUM_TTE_656 == 0)
299	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_TTE_ANCIL_0 0xFFFFFFFF
300	#endif
301	#if (BVBI_P_NUM_GSE_656 == 0)
302	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_GSE_ANCIL_0 0xFFFFFFFF
303	#endif
304	#if (BVBI_P_NUM_AMOLE_656 == 0)
305	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_AMOLE_ANCIL_0 0xFFFFFFFF
306	#endif
307
308	#if (BVBI_P_NUM_CCE_656 < 2)
309	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_CCE_ANCIL_1 0xFFFFFFFF
310	#endif
311	#if (BVBI_P_NUM_WSE_656 < 2)
312	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_WSE_ANCIL_1 0xFFFFFFFF
313	#endif
314	#if (BVBI_P_NUM_TTE_656 < 2)
315	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_TTE_ANCIL_1 0xFFFFFFFF
316	#endif
317	#if (BVBI_P_NUM_GSE_656 < 2)
318	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_GSE_ANCIL_1 0xFFFFFFFF
319	#endif
320	#if (BVBI_P_NUM_AMOLE_656 < 2)
321	#define BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_AMOLE_ANCIL_1 0xFFFFFFFF
322	#endif
323
324	/***************************************************************************
325	* Forward declarations of static (private) functions
326	***************************************************************************/
327	static void BVBI_P_VE_Enc_Init (BREG_Handle hReg, uint32_t ulRegAddr);
328
329
330	/***************************************************************************
331	* Implementation of "BVBI_" API functions
332	***************************************************************************/
333
334	BERR_Code BVBI_Encode_GetInterruptName(
335	BAVC_VbiPath eVbiPath,
336	BAVC_Polarity eFieldPolarity,
337	BINT_Id* pInterruptName
338	)
339	{
340	int index;
341	BERR_Code eErr = BERR_SUCCESS;
342	BINT_Id aEncodeInterruptName[2] = {0, 0};
343
344	BDBG_ENTER(BVBI_Encode_GetInterruptName);
345
346	/* Check for some obvious errors */
347	if(!pInterruptName)
348	{
349	BDBG_ERR(("Invalid parameter\n"));
350	eErr = BERR_TRACE(BERR_INVALID_PARAMETER);
351	goto BVBI_Encode_GetInterruptName_Done;
352	}
353	switch (eFieldPolarity)
354	{
355	case BAVC_Polarity_eFrame:
356	case BAVC_Polarity_eTopField:
357	case BAVC_Polarity_eBotField:
358	break;
359	default:
360	BDBG_ERR(("Invalid parameter\n"));
361	eErr = BERR_TRACE(BERR_INVALID_PARAMETER);
362	goto BVBI_Encode_GetInterruptName_Done;
363	break;
364	}
365	/* Interrupts to use according to VEC path */
366	switch (eVbiPath)
367	{
368	case BAVC_VbiPath_eVec0:
369	#if (BCHP_CHIP == 7420) \|\| (BCHP_CHIP == 7340) \|\| \
370	(BCHP_CHIP == 7342) \|\| (BCHP_CHIP == 7550) \|\| \
371	(BCHP_CHIP == 7125) \|\| (BCHP_CHIP == 7408) \|\| \
372	(BCHP_CHIP == 7422) \|\| (BCHP_CHIP == 7425) \|\| (BCHP_CHIP == 7435) \|\| \
373	(BCHP_CHIP == 7468) \|\| (BCHP_CHIP == 7358) \|\| (BCHP_CHIP == 7552) \|\| \
374	(BCHP_CHIP == 7344) \|\| (BCHP_CHIP == 7346) \|\| (BCHP_CHIP == 7429) \|\| \
375	(BCHP_CHIP == 7231) \|\| (BCHP_CHIP == 7552) \|\| \
376	(BCHP_CHIP == 35125) \|\| (BCHP_CHIP == 35230) \|\| (BCHP_CHIP == 35233)
377	aEncodeInterruptName[0] = BCHP_INT_ID_VBI_0_0_INTR;
378	aEncodeInterruptName[1] = BCHP_INT_ID_VBI_0_1_INTR;
379	#else
380	aEncodeInterruptName[0] = BCHP_INT_ID_PRIM_VBI_0_INTR;
381	aEncodeInterruptName[1] = BCHP_INT_ID_PRIM_VBI_1_INTR;
382	#endif
383	break;
384	#if (BVBI_P_NUM_VEC >= 2) / { /
385	case BAVC_VbiPath_eVec1:
386	#if (BCHP_CHIP == 7420) \|\| (BCHP_CHIP == 7340) \|\| \
387	(BCHP_CHIP == 7342) \|\| (BCHP_CHIP == 7550) \|\| \
388	(BCHP_CHIP == 7125) \|\| (BCHP_CHIP == 7408) \|\| \
389	(BCHP_CHIP == 7422) \|\| (BCHP_CHIP == 7425) \|\| (BCHP_CHIP == 7435) \|\| \
390	(BCHP_CHIP == 7344) \|\| (BCHP_CHIP == 7346) \|\| \
391	(BCHP_CHIP == 7231) \|\| (BCHP_CHIP == 7429) \|\| \
392	(BCHP_CHIP == 7468) \|\| (BCHP_CHIP == 7358) \|\| (BCHP_CHIP == 7552)
393	aEncodeInterruptName[0] = BCHP_INT_ID_VBI_1_0_INTR;
394	aEncodeInterruptName[1] = BCHP_INT_ID_VBI_1_1_INTR;
395	#else
396	aEncodeInterruptName[0] = BCHP_INT_ID_SEC_VBI_0_INTR;
397	aEncodeInterruptName[1] = BCHP_INT_ID_SEC_VBI_1_INTR;
398	#endif
399	break;
400	#endif / } (BVBI_P_NUM_VEC >= 2) /
401	#if (BVBI_P_NUM_VEC >= 3) / { /
402	case BAVC_VbiPath_eVec2:
403	#if (BCHP_CHIP == 7420) \|\| (BCHP_CHIP == 7340) \|\| \
404	(BCHP_CHIP == 7342) \|\| (BCHP_CHIP == 7550) \|\| \
405	(BCHP_CHIP == 7125) \|\| (BCHP_CHIP == 7408) \|\| \
406	(BCHP_CHIP == 7468)
407	aEncodeInterruptName[0] = BCHP_INT_ID_VBI_2_0_INTR;
408	aEncodeInterruptName[1] = BCHP_INT_ID_VBI_2_1_INTR;
409	#else
410	aEncodeInterruptName[0] = BCHP_INT_ID_TERT_VBI_0_INTR;
411	aEncodeInterruptName[1] = BCHP_INT_ID_TERT_VBI_1_INTR;
412	#endif
413	break;
414	#endif / } (BVBI_P_NUM_VEC >= 3) /
415	#if (BVBI_P_NUM_PTVEC > 0) / { /
416	case BAVC_VbiPath_eBypass0:
417	#ifdef P_HAS_MODULAR_VEC
418	#if (BCHP_CHIP == 7422) \|\| (BCHP_CHIP == 7425) \|\| (BCHP_CHIP == 7435)
419	aEncodeInterruptName[0] = BCHP_INT_ID_ANCIL_VBI_0_0_INTR;
420	aEncodeInterruptName[1] = BCHP_INT_ID_ANCIL_VBI_1_0_INTR;
421	#elif (BCHP_CHIP == 7344) \|\| (BCHP_CHIP == 7346) \|\| \
422	(BCHP_CHIP == 7231) \|\| (BCHP_CHIP == 7429)
423	/* Weird */
424	aEncodeInterruptName[0] = BCHP_INT_ID_ANCIL_VBI_0_0_INTR;
425	aEncodeInterruptName[1] = BCHP_INT_ID_ANCIL_VBI_0_1_INTR;
426	#else
427	aEncodeInterruptName[0] = BCHP_INT_ID_ANCIL_VBI_0_INTR;
428	aEncodeInterruptName[1] = BCHP_INT_ID_ANCIL_VBI_1_INTR;
429	#endif
430	#else
431	aEncodeInterruptName[0] = BCHP_INT_ID_BYPASS_VBI_0_INTR;
432	aEncodeInterruptName[1] = BCHP_INT_ID_BYPASS_VBI_1_INTR;
433	#endif
434	break;
435	#endif / } (BVBI_P_NUM_PTVEC > 0) /
436	default:
437	aEncodeInterruptName[0] = 0;
438	aEncodeInterruptName[1] = 0;
439	BDBG_ERR (("ERROR: failed to find VEC/VBI interrupts. %s: %d\n",
440	__FILE__, __LINE__));
441	eErr = BERR_TRACE(BERR_INVALID_PARAMETER);
442	goto BVBI_Encode_GetInterruptName_Done;
443	break;
444	}
445
446	/* Finally, apply field polarity */
447	index = (eFieldPolarity == BAVC_Polarity_eBotField ? 1 : 0);
448	*pInterruptName = aEncodeInterruptName[index];
449
450	BVBI_Encode_GetInterruptName_Done:
451	BDBG_LEAVE(BVBI_Encode_GetInterruptName);
452	return eErr;
453	}
454
455
456	/***************************************************************************
457	* Implementation of supporting VBI_ENC functions that are not in API
458	***************************************************************************/
459
460
461	BERR_Code BVBI_P_VE_Init( BVBI_P_Handle *pVbi )
462	{
463	int iCore;
464	uint8_t hwCoreIndex[BVBI_P_EncCoreType_eLAST];
465
466	BDBG_ENTER(BVBI_P_VE_Init);
467
468	for (iCore = 0 ; iCore < BVBI_P_EncCoreType_eLAST ; ++iCore)
469	hwCoreIndex[iCore] = 0xFF;
470
471	BVBI_P_VE_Enc_Init (pVbi->hReg, BCHP_VBI_ENC_VBI_0_INTR_CTRL);
472	BVBI_P_VE_Crossbar_Program (pVbi->hReg, BAVC_VbiPath_eVec0, hwCoreIndex);
473	#if (BVBI_P_NUM_VEC >= 2)
474	BVBI_P_VE_Enc_Init (pVbi->hReg, BCHP_VBI_ENC_VBI_1_INTR_CTRL);
475	BVBI_P_VE_Crossbar_Program (pVbi->hReg, BAVC_VbiPath_eVec1, hwCoreIndex);
476	#endif
477	#if (BVBI_P_NUM_VEC >= 3)
478	BVBI_P_VE_Enc_Init (pVbi->hReg, BCHP_VBI_ENC_VBI_2_INTR_CTRL);
479	BVBI_P_VE_Crossbar_Program (pVbi->hReg, BAVC_VbiPath_eVec2, hwCoreIndex);
480	#endif
481	#if (BVBI_P_NUM_PTVEC >= 1)
482	BVBI_P_VE_Enc_Init (pVbi->hReg, BCHP_VBI_ENC_VBI_ANCIL_0_INTR_CTRL);
483	BVBI_P_VE_Crossbar_Program (pVbi->hReg, BAVC_VbiPath_eBypass0, hwCoreIndex);
484	#endif
485	#if (BVBI_P_NUM_PTVEC >= 2)
486	BVBI_P_VE_Enc_Init (pVbi->hReg, BCHP_VBI_ENC_VBI_ANCIL_1_INTR_CTRL);
487	BVBI_P_VE_Crossbar_Program (pVbi->hReg, BAVC_VbiPath_eBypass1, hwCoreIndex);
488	#endif
489
490	BDBG_LEAVE(BVBI_P_VE_Init);
491	return BERR_SUCCESS;
492	}
493
494
495	BERR_Code BVBI_P_VE_Enc_Program (
496	BREG_Handle hReg,
497	bool is656,
498	uint8_t hwCoreIndex,
499	uint32_t ulActive_Standards,
500	uint32_t ulActive_656_Standards,
501	BFMT_VideoFmt eVideoFormat)
502	{
503	uint32_t topLine;
504	uint32_t botLine;
505	uint32_t ulReg;
506	uint32_t ulRegAddr = 0xFFFFFFFF;
507
508	BDBG_ENTER(BVBI_P_VE_Enc_Program);
509
510	BSTD_UNUSED (ulActive_Standards);
511	BSTD_UNUSED (ulActive_656_Standards);
512
513	/* Figure out which core register to use */
514	switch (hwCoreIndex)
515	{
516	case 0:
517	if (is656)
518	{
519	#if (BVBI_P_NUM_PTVEC >= 1)
520	ulRegAddr = BCHP_VBI_ENC_VBI_ANCIL_0_INTR_CTRL;
521	#endif
522	}
523	else
524	{
525	ulRegAddr = BCHP_VBI_ENC_VBI_0_INTR_CTRL;
526	}
527	break;
528	case 1:
529	if (is656)
530	{
531	#if (BVBI_P_NUM_PTVEC >= 2)
532	ulRegAddr = BCHP_VBI_ENC_VBI_ANCIL_1_INTR_CTRL;
533	#endif
534	}
535	else
536	{
537	#if (BVBI_P_NUM_VEC >= 2)
538	ulRegAddr = BCHP_VBI_ENC_VBI_1_INTR_CTRL;
539	#endif
540	}
541	break;
542	case 2:
543	if (is656)
544	{
545	#if (BVBI_P_NUM_PTVEC >= 3)
546	ulRegAddr = BCHP_VBI_ENC_VBI_ANCIL_2_INTR_CTRL;
547	#endif
548	}
549	else
550	{
551	#if (BVBI_P_NUM_VEC >= 3)
552	ulRegAddr = BCHP_VBI_ENC_VBI_2_INTR_CTRL;
553	#endif
554	}
555	break;
556	default:
557	break;
558	}
559	if (ulRegAddr == 0xFFFFFFFF)
560	{
561	/* This should never happen! This parameter was checked by
562	BVBI_Encode_Create() */
563	BDBG_LEAVE(BVBI_P_VE_Enc_Program);
564	return BERR_TRACE(BERR_INVALID_PARAMETER);
565	}
566
567	/* Prepare to program the interrupt control register */
568	ulReg = BREG_Read32 ( hReg, ulRegAddr );
569
570	/* Select video format */
571	switch (eVideoFormat)
572	{
573	case BFMT_VideoFmt_eNTSC:
574	case BFMT_VideoFmt_eNTSC_J:
575	case BFMT_VideoFmt_ePAL_M:
576	/* NTSC specific settings */
577	topLine = 37;
578	botLine = 300;
579	break;
580
581	case BFMT_VideoFmt_e1080i:
582	case BFMT_VideoFmt_e1080i_50Hz:
583	topLine = 21;
584	botLine = 584;
585	break;
586
587	case BFMT_VideoFmt_e720p:
588	case BFMT_VideoFmt_e720p_50Hz:
589	topLine = 26;
590	botLine = 0;
591	break;
592
593	case BFMT_VideoFmt_e480p:
594	topLine = 46;
595	botLine = 0;
596	break;
597
598	case BFMT_VideoFmt_ePAL_B:
599	case BFMT_VideoFmt_ePAL_B1:
600	case BFMT_VideoFmt_ePAL_D:
601	case BFMT_VideoFmt_ePAL_D1:
602	case BFMT_VideoFmt_ePAL_G:
603	case BFMT_VideoFmt_ePAL_H:
604	case BFMT_VideoFmt_ePAL_K:
605	case BFMT_VideoFmt_ePAL_I:
606	case BFMT_VideoFmt_ePAL_N:
607	case BFMT_VideoFmt_ePAL_NC:
608	case BFMT_VideoFmt_eSECAM_L:
609	case BFMT_VideoFmt_eSECAM_B:
610	case BFMT_VideoFmt_eSECAM_G:
611	case BFMT_VideoFmt_eSECAM_D:
612	case BFMT_VideoFmt_eSECAM_K:
613	case BFMT_VideoFmt_eSECAM_H:
614	topLine = 47;
615	botLine = 360;
616	break;
617
618	case BFMT_VideoFmt_e576p_50Hz:
619	topLine = 23;
620	botLine = 0;
621	break;
622
623	default:
624	BDBG_LEAVE(BVBI_P_VE_Enc_Program);
625	BDBG_ERR(("BVBI_VE: video format %d not supported", eVideoFormat));
626	return BERR_TRACE (BERR_NOT_SUPPORTED);
627	break;
628	}
629
630	/* Finish programming the interrupt control register */
631	ulReg &= ~(
632	BCHP_MASK (VBI_ENC_VBI_0_INTR_CTRL, INTR1_LINE ) \|
633	BCHP_MASK (VBI_ENC_VBI_0_INTR_CTRL, INTR0_LINE )
634	);
635	ulReg \|= (
636	BCHP_FIELD_DATA(VBI_ENC_VBI_0_INTR_CTRL, INTR1_LINE, botLine) \|
637	BCHP_FIELD_DATA(VBI_ENC_VBI_0_INTR_CTRL, INTR0_LINE, topLine)
638	);
639	BREG_Write32 (hReg, ulRegAddr, ulReg);
640
641	BDBG_LEAVE(BVBI_P_VE_Enc_Program);
642	return BERR_SUCCESS;
643	}
644
645
646	/***************************************************************************
647	*
648	*/
649	void BVBI_P_VE_Crossbar_Program (
650	BREG_Handle hReg,
651	BAVC_VbiPath eDest,
652	uint8_t hwCoreIndex[BVBI_P_EncCoreType_eLAST])
653	{
654	bool is656;
655	uint32_t ulRegMax;
656	uint32_t ulRegBase;
657	uint32_t ulRegAddr;
658	uint32_t iReg;
659	uint32_t ulBit;
660	int iCore;
661	uint8_t coreIndex;
662
663	BDBG_ENTER (BVBI_P_VE_Crossbar_Program);
664
665	switch (eDest)
666	{
667	#if (BVBI_P_NUM_VEC >= 1)
668	case BAVC_VbiPath_eVec0:
669	ulRegBase = BCHP_VBI_ENC_VBI_0_CORE_0_SEL;
670	is656 = false;
671	break;
672	#endif
673	#if (BVBI_P_NUM_VEC >= 2)
674	case BAVC_VbiPath_eVec1:
675	ulRegBase = BCHP_VBI_ENC_VBI_1_CORE_0_SEL;
676	is656 = false;
677	break;
678	#endif
679	#if (BVBI_P_NUM_VEC >= 3)
680	case BAVC_VbiPath_eVec2:
681	ulRegBase = BCHP_VBI_ENC_VBI_2_CORE_0_SEL;
682	is656 = false;
683	break;
684	#endif
685	#if (BVBI_P_NUM_PTVEC >= 1)
686	case BAVC_VbiPath_eBypass0:
687	ulRegBase = BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL;
688	is656 = true;
689	break;
690	#endif
691	#if (BVBI_P_NUM_PTVEC >= 2)
692	case BAVC_VbiPath_eBypass1:
693	ulRegBase = BCHP_VBI_ENC_VBI_ANCIL_1_CORE_0_SEL;
694	is656 = true;
695	break;
696	#endif
697	default:
698	ulRegBase = 0xFFFFFFFF;
699	is656 = false;
700	break;
701	}
702	BDBG_ASSERT (ulRegBase != 0xFFFFFFFF);
703	/* coverity[dead_error_condition: FALSE] */
704	if (is656)
705	{
706	/* coverity[dead_error_line: FALSE] */
707	ulRegMax = BVBI_P_ENC_NUM_CROSSBAR_REG_656;
708	}
709	else
710	{
711	ulRegMax = BVBI_P_ENC_NUM_CROSSBAR_REG;
712	}
713
714	iReg = 0;
715	for (iCore = 0 ; iCore < BVBI_P_EncCoreType_eLAST ; ++iCore)
716	{
717	coreIndex = hwCoreIndex[iCore];
718	switch (iCore)
719	{
720	case BVBI_P_EncCoreType_eCCE:
721	switch (coreIndex)
722	{
723	case 0:
724	ulBit =
725	(is656 ?
726	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_CCE_ANCIL_0 :
727	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CCE_0);
728	break;
729	#if (BVBI_P_NUM_CCE >= 2)
730	case 1:
731	ulBit =
732	(is656 ?
733	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_CCE_ANCIL_1 :
734	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CCE_1);
735	break;
736	#endif
737	#if (BVBI_P_NUM_CCE >= 3)
738	case 2:
739	ulBit =
740	(is656 ?
741	0xFFFFFFFF : BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CCE_2);
742	break;
743	#endif
744	default:
745	ulBit = 0xFFFFFFFF;
746	break;
747	}
748	break;
749	case BVBI_P_EncCoreType_eCGMSAE:
750	switch (coreIndex)
751	{
752	case 0:
753	ulBit =
754	(is656 ?
755	0xFFFFFFFF :
756	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CGMSAE_0);
757	break;
758	#if (BVBI_P_NUM_CGMSAE >= 2)
759	case 1:
760	ulBit =
761	(is656 ?
762	0xFFFFFFFF :
763	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CGMSAE_1);
764	break;
765	#endif
766	#if (BVBI_P_NUM_CGMSAE >= 3)
767	case 2:
768	ulBit =
769	(is656 ?
770	0xFFFFFFFF :
771	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_CGMSAE_2);
772	break;
773	#endif
774	default:
775	ulBit = 0xFFFFFFFF;
776	break;
777	}
778	break;
779	case BVBI_P_EncCoreType_eWSE:
780	switch (coreIndex)
781	{
782	case 0:
783	ulBit =
784	(is656 ?
785	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_WSE_ANCIL_0 :
786	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_WSE_0);
787	break;
788	#if (BVBI_P_NUM_WSE >= 2)
789	case 1:
790	ulBit =
791	(is656 ?
792	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_WSE_ANCIL_1 :
793	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_WSE_1);
794	break;
795	#endif
796	#if (BVBI_P_NUM_WSE >= 3)
797	case 2:
798	ulBit =
799	(is656 ?
800	0xFFFFFFFF :
801	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_WSE_2);
802	break;
803	#endif
804	default:
805	ulBit = 0xFFFFFFFF;
806	break;
807	}
808	break;
809	case BVBI_P_EncCoreType_eTTE:
810	switch (coreIndex)
811	{
812	#if (BVBI_P_NUM_TTE >= 1)
813	case 0:
814	ulBit =
815	(is656 ?
816	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_TTE_ANCIL_0 :
817	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_TTE_0);
818	break;
819	#endif
820	#if (BVBI_P_NUM_TTE >= 2)
821	case 1:
822	ulBit =
823	(is656 ?
824	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_TTE_ANCIL_1 :
825	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_TTE_1);
826	break;
827	#endif
828	#if (BVBI_P_NUM_TTE >= 3)
829	case 2:
830	ulBit =
831	(is656 ?
832	0xFFFFFFFF :
833	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_TTE_2);
834	break;
835	#endif
836	default:
837	ulBit = 0xFFFFFFFF;
838	break;
839	}
840	break;
841	case BVBI_P_EncCoreType_eGSE:
842	switch (coreIndex)
843	{
844	#if (BVBI_P_NUM_GSE >= 1)
845	case 0:
846	ulBit =
847	(is656 ?
848	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_GSE_ANCIL_0 :
849	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_GSE_0);
850	break;
851	#endif
852	#if (BVBI_P_NUM_GSE >= 2)
853	case 1:
854	ulBit =
855	(is656 ?
856	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_GSE_ANCIL_1 :
857	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_GSE_1);
858	break;
859	#endif
860	#if (BVBI_P_NUM_GSE >= 3)
861	case 2:
862	ulBit =
863	(is656 ?
864	0xFFFFFFFF :
865	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_GSE_2);
866	break;
867	#endif
868	default:
869	ulBit = 0xFFFFFFFF;
870	break;
871	}
872	break;
873	case BVBI_P_EncCoreType_eAMOLE:
874	switch (coreIndex)
875	{
876	#if (BVBI_P_NUM_AMOLE >= 1)
877	case 0:
878	ulBit =
879	(is656 ?
880	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_AMOLE_ANCIL_0 :
881	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_AMOLE_0);
882	break;
883	#endif
884	#if (BVBI_P_NUM_AMOLE >= 2)
885	case 1:
886	ulBit =
887	(is656 ?
888	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_AMOLE_ANCIL_1 :
889	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_AMOLE_1);
890	break;
891	#endif
892	#if (BVBI_P_NUM_AMOLE >= 3)
893	case 2:
894	ulBit =
895	(is656 ?
896	0xFFFFFFFF :
897	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_AMOLE_2);
898	break;
899	#endif
900	default:
901	ulBit = 0xFFFFFFFF;
902	break;
903	}
904	break;
905	case BVBI_P_EncCoreType_eSCTE:
906	switch (coreIndex)
907	{
908	#if (BVBI_P_NUM_SCTEE >= 1)
909	case 0:
910	ulBit =
911	(is656 ?
912	0xFFFFFFFF :
913	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_SCTE_0);
914	break;
915	#endif
916	#if (BVBI_P_NUM_SCTEE >= 2)
917	case 1:
918	ulBit =
919	(is656 ?
920	0xFFFFFFFF :
921	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_SCTE_1);
922	break;
923	#endif
924	default:
925	ulBit = 0xFFFFFFFF;
926	break;
927	}
928	break;
929	default:
930	ulBit = 0xFFFFFFFF;
931	break;
932	}
933	if (iReg >= ulRegMax)
934	{
935	/* Note: this is a silent failure. TODO. */
936	break;
937	}
938	if (ulBit != 0xFFFFFFFF)
939	{
940	ulRegAddr = ulRegBase + 4 * iReg;
941	BREG_Write32 (hReg, ulRegAddr, ulBit);
942	++iReg;
943	}
944	}
945
946	/* Zero out unused crossbar entries */
947	#if (BVBI_P_NUM_PTVEC >= 1)
948	ulBit =
949	(is656 ?
950	BCHP_VBI_ENC_VBI_ANCIL_0_CORE_0_SEL_SEL_DISABLE :
951	BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_DISABLE);
952	#else
953	BDBG_ASSERT (!is656);
954	ulBit = BCHP_VBI_ENC_VBI_0_CORE_0_SEL_SEL_DISABLE;
955	#endif
956	while (iReg < ulRegMax)
957	{
958	ulRegAddr = ulRegBase + 4 * iReg;
959	BREG_Write32 (hReg, ulRegAddr, ulBit);
960	++iReg;
961	}
962
963	BDBG_LEAVE (BVBI_P_VE_Crossbar_Program);
964	}
965
966	/***************************************************************************
967	* Static (private) functions
968	***************************************************************************/
969
970	/***************************************************************************
971	*
972	*/
973	static void BVBI_P_VE_Enc_Init (BREG_Handle hReg, uint32_t ulRegAddr)
974	{
975	uint32_t topLine;
976	uint32_t botLine;
977	uint32_t ulReg;
978
979	BDBG_ENTER(BVBI_P_VE_Enc_Init);
980
981	/* Cause interrupts to occur according to start of NTSC active video
982	(default) */
983	ulReg = BREG_Read32 ( hReg, ulRegAddr );
984	topLine = 23;
985	botLine = 286;
986	ulReg &= ~(
987	BCHP_MASK (VBI_ENC_VBI_0_INTR_CTRL, INTR1_LINE ) \|
988	BCHP_MASK (VBI_ENC_VBI_0_INTR_CTRL, INTR0_LINE )
989	);
990	ulReg \|= (
991	BCHP_FIELD_DATA(VBI_ENC_VBI_0_INTR_CTRL, INTR1_LINE, botLine) \|
992	BCHP_FIELD_DATA(VBI_ENC_VBI_0_INTR_CTRL, INTR0_LINE, topLine)
993	);
994	BREG_Write32 (hReg, ulRegAddr, ulReg);
995
996	BDBG_LEAVE(BVBI_P_VE_Enc_Init);
997	}
998
999	/* End of file */

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_ve.c

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