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bvbi_vpsd.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2009, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_vpsd.c $
11	* $brcm_Revision: Hydra_Software_Devel/2 $
12	* $brcm_Date: 12/21/09 7:07p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7400/bvbi_vpsd.c $
19	*
20	* Hydra_Software_Devel/2 12/21/09 7:07p darnstein
21	* SW7550-120: Add support for SECAM variants.
22	*
23	* Hydra_Software_Devel/1 12/3/08 8:03p darnstein
24	* PR45819:
25	*
26	***************************************************************************/
27
28	#include "bstd.h" /* standard types */
29	#include "bdbg.h" /* Dbglib */
30	#include "bkni.h" /* For critical sections */
31	#include "bvbi.h" /* VBI processing, this module. */
32	#include "bvbi_priv.h" /* VBI internal data structures */
33	#if defined(BVBI_P_HAS_VPSD)
34	#include "bchp_vpsd_0.h"
35	#if (BVBI_P_NUM_VDEC >= 2)
36	#include "bchp_vpsd_1.h"
37	#endif
38	#endif
39
40	BDBG_MODULE(BVBI);
41
42
43	/***************************************************************************
44	* Forward declarations of static (private) functions
45	***************************************************************************/
46
47
48	/***************************************************************************
49	* Implementation of supporting VPS functions that are not in API
50	***************************************************************************/
51
52	#if defined(BVBI_P_HAS_VPSD) / { /
53
54	/***************************************************************************
55	*
56	*/
57	void BVBI_P_VPS_Dec_Init (BREG_Handle hReg, uint32_t ulCoreOffset)
58	{
59	uint32_t ulControlReg;
60
61	BDBG_ENTER(BVBI_P_VPS_Dec_Init);
62
63	/* No reset here. */
64
65	BKNI_EnterCriticalSection();
66
67	/* Program the control register (all default values) */
68	ulControlReg = (
69	BCHP_FIELD_DATA (VPSD_0_CONTROL, BIPHASE_MIN_01, 1) \|
70	BCHP_FIELD_DATA (VPSD_0_CONTROL, STATUS_OVERWRITE, 0) \|
71	BCHP_FIELD_DATA (VPSD_0_CONTROL, DATA_OVERWRITE, 0) \|
72	BCHP_FIELD_DATA (VPSD_0_CONTROL, CORR_WIN_DIS, 0) \|
73	BCHP_FIELD_DATA (VPSD_0_CONTROL, RUNIN_DET_WIN_DIS, 0) \|
74	BCHP_FIELD_DATA (VPSD_0_CONTROL, VPS_DECODE_TYPE, 0) \|
75	BCHP_FIELD_ENUM (VPSD_0_CONTROL, DECODE, DISABLED) );
76	BREG_Write32 (hReg, BCHP_VPSD_0_CONTROL + ulCoreOffset, ulControlReg);
77
78	/* Program the first config register */
79	ulControlReg = (
80	BCHP_FIELD_DATA (VPSD_0_CONFIG_0, VPS_FIELD, 0) \|
81	BCHP_FIELD_DATA (VPSD_0_CONFIG_0, VPS_LINE_CNT, 16) );
82	BREG_Write32 (hReg, BCHP_VPSD_0_CONFIG_0 + ulCoreOffset, ulControlReg);
83
84	/* Program the second config register */
85	ulControlReg = (
86	BCHP_FIELD_DATA (VPSD_0_CONFIG_1, CORR_PEAK_START_TIME, 0x76) \|
87	BCHP_FIELD_DATA (VPSD_0_CONFIG_1, RUN_IN_START_TIME, 0x10) );
88	BREG_Write32 (hReg, BCHP_VPSD_0_CONFIG_1 + ulCoreOffset, ulControlReg);
89
90	/* Program the threshold register */
91	ulControlReg = (
92	BCHP_FIELD_DATA (VPSD_0_THRESHOLD, CORR_THRESHOLD, 0x02c) \|
93	BCHP_FIELD_DATA (VPSD_0_THRESHOLD, AVG_LEVEL_THRESHOLD, 0x150) );
94	BREG_Write32 (hReg, BCHP_VPSD_0_THRESHOLD + ulCoreOffset, ulControlReg);
95
96	BKNI_LeaveCriticalSection();
97
98	BDBG_LEAVE(BVBI_P_VPS_Dec_Init);
99	}
100
101
102	/***************************************************************************
103	*
104	*/
105	BERR_Code BVBI_P_VPS_Dec_Program (
106	BREG_Handle hReg,
107	BAVC_SourceId eSource,
108	bool bActive,
109	BFMT_VideoFmt eVideoFormat)
110	{
111	/*
112	Programming note: the implementation here assumes that the bitfield layout
113	within registers is the same for all VPS decoder cores in the chip.
114
115	If a chip is built that has multiple VPS decoder cores that are not
116	identical, then this routine will have to be redesigned.
117	*/
118	uint32_t ulControlReg;
119	uint32_t ulStatusReg;
120	uint32_t ulOffset;
121
122	BDBG_ENTER(BVBI_P_VPS_Dec_Program);
123
124	/* Complain if video format is not supported */
125	switch (eVideoFormat)
126	{
127	case BFMT_VideoFmt_ePAL_B:
128	case BFMT_VideoFmt_ePAL_B1:
129	case BFMT_VideoFmt_ePAL_D:
130	case BFMT_VideoFmt_ePAL_D1:
131	case BFMT_VideoFmt_ePAL_G:
132	case BFMT_VideoFmt_ePAL_H:
133	case BFMT_VideoFmt_ePAL_K:
134	case BFMT_VideoFmt_ePAL_I:
135	case BFMT_VideoFmt_ePAL_M:
136	case BFMT_VideoFmt_ePAL_N:
137	case BFMT_VideoFmt_ePAL_NC:
138	case BFMT_VideoFmt_eSECAM_L:
139	case BFMT_VideoFmt_eSECAM_B:
140	case BFMT_VideoFmt_eSECAM_G:
141	case BFMT_VideoFmt_eSECAM_D:
142	case BFMT_VideoFmt_eSECAM_K:
143	case BFMT_VideoFmt_eSECAM_H:
144	break;
145
146	default:
147	if (bActive)
148	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
149	}
150
151	/* Figure out which decoder core to use */
152	switch (eSource)
153	{
154	case BAVC_SourceId_eVdec0:
155	ulOffset = 0;
156	break;
157	#if (BVBI_P_NUM_VDEC > 1)
158	case BAVC_SourceId_eVdec1:
159	ulOffset = BCHP_VPSD_1_CONTROL - BCHP_VPSD_0_CONTROL;
160	break;
161	#endif
162	default:
163	/* This should never happen! This parameter was checked by
164	BVBI_Decode_Create() */
165	BDBG_LEAVE(BVBI_P_VPS_Dec_Program);
166	return BERR_TRACE(BERR_INVALID_PARAMETER);
167	break;
168	}
169
170	BKNI_EnterCriticalSection();
171
172	/* Program the control register */
173	ulControlReg = BREG_Read32 (hReg, BCHP_VPSD_0_CONTROL + ulOffset);
174	ulControlReg &= ~BCHP_MASK (VPSD_0_CONTROL, DECODE);
175	if (bActive)
176	{
177	/* Will enable decoding */
178	ulControlReg \|= BCHP_FIELD_ENUM (VPSD_0_CONTROL, DECODE, ENABLED);
179
180	/* Clear the status register */
181	ulStatusReg = (
182	BCHP_FIELD_DATA (VPSD_0_STATUS, START_CODE_II_DET, 1) \|
183	BCHP_FIELD_DATA (VPSD_0_STATUS, PEAK_CORR_DET, 1) \|
184	BCHP_FIELD_DATA (VPSD_0_STATUS, SIGNAL_AVG_DET, 1) \|
185	BCHP_FIELD_DATA (VPSD_0_STATUS, RUN_IN_DET, 1) \|
186	BCHP_FIELD_DATA (VPSD_0_STATUS, DATA_OVERRUN, 1) \|
187	BCHP_FIELD_DATA (VPSD_0_STATUS, BIPHASE_ERROR, 1) \|
188	BCHP_FIELD_DATA (VPSD_0_STATUS, VPS_DATA_VALID, 1) );
189	BREG_Write32 (hReg, BCHP_VPSD_0_STATUS + ulOffset, ulStatusReg);
190	}
191	else
192	{
193	/* Will disable decoding */
194	ulControlReg \|= (
195	BCHP_FIELD_ENUM (VPSD_0_CONTROL, DECODE, DISABLED) );
196	}
197
198	/* Finish programming the control register */
199	BREG_Write32 (hReg, BCHP_VPSD_0_CONTROL + ulOffset, ulControlReg);
200
201	BKNI_LeaveCriticalSection();
202
203	BDBG_LEAVE(BVBI_P_VPS_Dec_Program);
204	return BERR_SUCCESS;
205	}
206
207
208	/***************************************************************************
209	*
210	*/
211	uint32_t BVBI_P_VPS_Decode_Data_isr (
212	BREG_Handle hReg,
213	BAVC_SourceId eSource,
214	BAVC_Polarity polarity,
215	BVBI_VPSData *pVPSData)
216	{
217	/*
218	Programming note: the implementation here assumes that the bitfield layout
219	within registers is the same for all VPS decoder cores in the chip.
220
221	If a chip is built that has multiple VPS decoder cores that are not
222	identical, then this routine will have to be redesigned.
223	*/
224	uint32_t ulOffset;
225	uint32_t ulStatusReg;
226	uint8_t ucBiphaseBit;
227	uint8_t ucOverrunBit;
228	uint8_t ucValidBit;
229	uint32_t ulDataReg;
230	uint32_t ulErrInfo = 0;
231
232	BDBG_ENTER(BVBI_P_VPS_Decode_Data_isr);
233
234	/* Figure out which decoder core to use */
235	switch (eSource)
236	{
237	case BAVC_SourceId_eVdec0:
238	ulOffset = 0x0;
239	break;
240	#if (BVBI_P_NUM_VDEC > 1)
241	case BAVC_SourceId_eVdec1:
242	ulOffset = BCHP_VPSD_1_CONTROL - BCHP_VPSD_0_CONTROL;
243	break;
244	#endif
245	default:
246	/* This should never happen! This parameter was checked by
247	BVBI_Decode_Create() */
248	ulOffset = 0x0;
249	BDBG_LEAVE(BVBI_P_VPS_Decode_Data_isr);
250	return (-1);
251	break;
252	}
253
254	/* VPS is for top field only */
255	if (polarity != BAVC_Polarity_eTopField)
256	{
257	return BVBI_LINE_ERROR_PARITY_CONFLICT \| BVBI_LINE_ERROR_VPS_NODATA;
258	}
259
260	/* Verify that field handle data pointer is valid (allocated) */
261	if (pVPSData == 0x0)
262	{
263	ulErrInfo \|=
264	(BVBI_LINE_ERROR_FLDH_CONFLICT \| BVBI_LINE_ERROR_VPS_NODATA);
265	BDBG_LEAVE(BVBI_P_VPS_Decode_Data_isr);
266	return ulErrInfo;
267	}
268
269
270	/* Pull status info out of the hardware */
271	ulStatusReg = BREG_Read32 ( hReg, BCHP_VPSD_0_STATUS + ulOffset );
272	ucBiphaseBit =
273	(uint8_t)BCHP_GET_FIELD_DATA (
274	ulStatusReg, VPSD_0_STATUS, BIPHASE_ERROR);
275	ucOverrunBit =
276	(uint8_t)BCHP_GET_FIELD_DATA (
277	ulStatusReg, VPSD_0_STATUS, DATA_OVERRUN);
278	ucValidBit =
279	(uint8_t)BCHP_GET_FIELD_DATA (
280	ulStatusReg, VPSD_0_STATUS, VPS_DATA_VALID);
281
282	/* Got data? */
283	if (ucValidBit == 1)
284	{
285	/* read the data */
286	ulDataReg = BREG_Read32 (hReg, BCHP_VPSD_0_DATA3_0 + ulOffset);
287	pVPSData->ucByte05 = (uint8_t)((ulDataReg & 0x00FF0000) >> 16);
288	ulDataReg = BREG_Read32 (hReg, BCHP_VPSD_0_DATA11_8 + ulOffset);
289	pVPSData->ucByte11 = (uint8_t)(ulDataReg & 0x000000FF);
290	ulDataReg >>= 8;
291	pVPSData->ucByte12 = (uint8_t)(ulDataReg & 0x000000FF);
292	ulDataReg >>= 8;
293	pVPSData->ucByte13 = (uint8_t)(ulDataReg & 0x000000FF);
294	ulDataReg >>= 8;
295	pVPSData->ucByte14 = (uint8_t)(ulDataReg & 0x000000FF);
296	ulDataReg = BREG_Read32 (hReg, BCHP_VPSD_0_DATA12 + ulOffset);
297	pVPSData->ucByte15 = (uint8_t)(ulDataReg & 0x000000FF);
298	}
299	else /* No data */
300	{
301	ulErrInfo \|= BVBI_LINE_ERROR_VPS_NODATA;
302	}
303
304	/* Report other error conditions */
305	if (ucOverrunBit == 1)
306	{
307	ulErrInfo \|= BVBI_LINE_ERROR_VPS_OVERRUN;
308	}
309	if (ucBiphaseBit == 1)
310	{
311	ulErrInfo \|= BVBI_LINE_ERROR_VPS_BIPHASE;
312	}
313
314	/* Clear status bits in hardware */
315	BREG_Write32 ( hReg, BCHP_VPSD_0_STATUS + ulOffset, ulStatusReg );
316
317	BDBG_LEAVE(BVBI_P_VPS_Decode_Data_isr);
318	return ulErrInfo;
319	}
320
321	#endif / } BVBI_P_HAS_VPSD /
322
323
324	/***************************************************************************
325	* Static (private) functions
326	***************************************************************************/

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_vpsd.c

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