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bvbi_wsse.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_wsse.c $
11	* $brcm_Revision: Hydra_Software_Devel/8 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_wsse.c $
19	*
20	* Hydra_Software_Devel/8 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/7 2/20/12 12:56p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/6 12/21/09 7:03p darnstein
28	* SW7550-120: Add support for SECAM variants.
29	*
30	* Hydra_Software_Devel/5 6/24/09 7:10p darnstein
31	* PR53956: 7420-B0 has a new WSE core.
32	*
33	* Hydra_Software_Devel/4 5/13/09 1:18p darnstein
34	* PR53956: 7420-Bx has fixed WSE core.
35	*
36	* Hydra_Software_Devel/3 3/27/09 7:43p darnstein
37	* PR53635: Remove internal ConfigForOthers code. It is obsolete, and it
38	* was causing a problem (this PR).
39	*
40	* Hydra_Software_Devel/2 12/4/08 6:07p darnstein
41	* PR45819: 7420 software will now compile, but not link.
42	*
43	* Hydra_Software_Devel/1 12/3/08 8:03p darnstein
44	* PR45819:
45	*
46	***************************************************************************/
47
48	#include "bstd.h" /* standard types */
49	#include "bdbg.h" /* Dbglib */
50	#include "bvbi.h" /* VBI processing, this module. */
51	#include "bkni.h" /* For critical sections */
52	#include "bvbi_priv.h" /* VBI internal data structures */
53	#if (BVBI_P_NUM_WSE >= 1)
54	#include "bchp_wse_0.h" /* RDB info for primary WSSE core */
55	#endif
56	#if (BVBI_P_NUM_WSE >= 2)
57	#include "bchp_wse_1.h" /* RDB info for secondary WSSE core */
58	#endif
59	#if (BVBI_P_NUM_WSE >= 3)
60	#include "bchp_wse_2.h" /* RDB info for tertiary WSSE core */
61	#endif
62	#if (BVBI_P_NUM_WSE_656 >= 1)
63	#include "bchp_wse_ancil_0.h" /* RDB info for ITU-R 656 "bypass" WSSE core */
64	#endif
65
66	BDBG_MODULE(BVBI);
67
68
69	/***************************************************************************
70	* Forward declarations of static (private) functions
71	***************************************************************************/
72	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex);
73
74
75	/***************************************************************************
76	* Implementation of supporting WSS functions that are not in API
77	***************************************************************************/
78
79	/***************************************************************************
80	*
81	*/
82	void BVBI_P_WSS_Enc_Init (BREG_Handle hReg, uint8_t hwCoreIndex)
83	{
84	uint32_t ulCoreOffset;
85	uint32_t ulDataReg;
86	uint32_t ulControlReg;
87
88	BDBG_ENTER(BVBI_P_WSS_Enc_Init);
89
90	BVBI_P_VIE_SoftReset (hReg, false, hwCoreIndex, BVBI_P_SELECT_WSS);
91
92	/* Determine which core to access */
93	ulCoreOffset = P_GetCoreOffset (false, hwCoreIndex);
94	if (ulCoreOffset == 0xFFFFFFFF)
95	{
96	/* This should never happen! This parameter was checked by
97	BVBI_Encode_Create() */
98	BDBG_ASSERT (0);
99	}
100
101	BKNI_EnterCriticalSection();
102
103	/* Program the control register */
104	ulControlReg = BREG_Read32 (hReg, BCHP_WSE_0_control + ulCoreOffset);
105	ulControlReg &= ~(
106	BCHP_MASK (WSE_0_control, output_attenuation ) \|
107	BCHP_MASK (WSE_0_control, OUTPUT_ORDER ) \|
108	BCHP_MASK (WSE_0_control, anci656_enable ) \|
109	BCHP_MASK (WSE_0_control, invert_data ) \|
110	BCHP_MASK (WSE_0_control, active_line ) \|
111	BCHP_MASK (WSE_0_control, enable ) );
112	ulControlReg \|= (
113	BCHP_FIELD_DATA (WSE_0_control, output_attenuation, 0x64) \|
114	BCHP_FIELD_ENUM (WSE_0_control, OUTPUT_ORDER, Low_Pad_2nd) \|
115	BCHP_FIELD_DATA (WSE_0_control, anci656_enable, 1) \|
116	BCHP_FIELD_ENUM (WSE_0_control, invert_data, Off) \|
117	BCHP_FIELD_DATA (WSE_0_control, active_line, 22) \|
118	BCHP_FIELD_DATA (WSE_0_control, enable, 0) );
119	BREG_Write32 (hReg, BCHP_WSE_0_control + ulCoreOffset, ulControlReg);
120
121	/* Clear burst lock status */
122	ulDataReg = BREG_Read32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset);
123	ulDataReg &= ~BCHP_MASK (WSE_0_wss_data, wss_data );
124	ulDataReg \|= BCHP_FIELD_DATA (WSE_0_wss_data, wss_data, 0x0);
125	BREG_Write32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset, ulDataReg);
126
127	BKNI_LeaveCriticalSection();
128
129	BDBG_LEAVE(BVBI_P_WSS_Enc_Init);
130	}
131
132	#if (BVBI_P_NUM_WSE_656 >= 1)
133	/***************************************************************************
134	*
135	*/
136	void BVBI_P_WSS_656_Enc_Init (BREG_Handle hReg, uint8_t hwCoreIndex)
137	{
138	uint32_t ulDataReg;
139	uint32_t ulControlReg;
140
141	/* This is just a little sloppy */
142	BSTD_UNUSED (hwCoreIndex);
143
144	BDBG_ENTER(BVBI_P_WSS_656_Enc_Init);
145
146	BKNI_EnterCriticalSection();
147
148	/* Start by doing a reset */
149
150	BVBI_P_VIE_SoftReset (hReg, true, hwCoreIndex, BVBI_P_SELECT_WSS);
151
152	/* Program the control register */
153	ulControlReg = BREG_Read32 (hReg, BCHP_WSE_ANCIL_0_control);
154	ulControlReg &= ~(
155	BCHP_MASK (WSE_ANCIL_0_control, OUTPUT_ORDER ) \|
156	BCHP_MASK (WSE_ANCIL_0_control, anci656_enable ) \|
157	BCHP_MASK (WSE_ANCIL_0_control, active_line ) );
158	ulControlReg \|= (
159	BCHP_FIELD_ENUM (WSE_ANCIL_0_control, OUTPUT_ORDER, Low_Pad_2nd) \|
160	BCHP_FIELD_DATA (WSE_ANCIL_0_control, anci656_enable, 1) \|
161	BCHP_FIELD_DATA (WSE_ANCIL_0_control, active_line, 22) );
162	BREG_Write32 (hReg, BCHP_WSE_ANCIL_0_control, ulControlReg);
163
164	/* Clear burst lock status */
165	ulDataReg = BREG_Read32 (hReg, BCHP_WSE_ANCIL_0_wss_data);
166	ulDataReg &= ~BCHP_MASK (WSE_ANCIL_0_wss_data, wss_data );
167	ulDataReg \|= BCHP_FIELD_DATA (WSE_ANCIL_0_wss_data, wss_data, 0x0);
168	BREG_Write32 (hReg, BCHP_WSE_ANCIL_0_wss_data, ulDataReg);
169
170	BKNI_LeaveCriticalSection();
171
172	BDBG_LEAVE(BVBI_P_WSS_656_Enc_Init);
173	}
174	#endif / } (BVBI_P_NUM_WSE_656 >= 1) /
175
176	BERR_Code BVBI_P_WSS_Enc_Program (
177	BREG_Handle hReg,
178	bool is656,
179	uint8_t hwCoreIndex,
180	bool bActive,
181	bool bPR18010_bad_line_number,
182	BFMT_VideoFmt eVideoFormat)
183	{
184	/*
185	Programming note: the implementation here assumes that the bitfield layout
186	within registers is the same for all WSS encoder cores in the chip.
187
188	If a chip is built that has multiple WSS encoder cores that are not
189	identical, then this routine will have to be redesigned.
190	*/
191	BERR_Code eErr;
192	uint32_t ulCoreOffset;
193	uint32_t ulControlReg;
194	uint32_t start_delay;
195	uint32_t ulActiveLine;
196	#if defined(BVBI_P_WSE_VER3) \|\| defined(BVBI_P_WSE_VER4) \|\| \
197	defined(BVBI_P_WSE_VER5)
198	uint32_t iDecimate = BCHP_WSE_0_control_DECIMATOR_EN_DISABLE;
199	#endif
200	#if (BVBI_P_NUM_WSE_656 >= 1)
201	#else
202	BSTD_UNUSED (bPR18010_bad_line_number);
203	#endif
204
205	BDBG_ENTER(BVBI_P_WSS_Enc_Program);
206
207	/* Figure out which encoder core to use */
208	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
209	if (ulCoreOffset == 0xFFFFFFFF)
210	{
211	/* This should never happen! This parameter was checked by
212	BVBI_Encode_Create() */
213	BDBG_LEAVE(BVBI_P_WSE_Enc_Program);
214	return BERR_TRACE(BERR_INVALID_PARAMETER);
215	}
216
217	/* Complain if video format is not supported */
218	switch (eVideoFormat)
219	{
220	/* NTSC case is just for testing */
221	case BFMT_VideoFmt_eNTSC:
222	case BFMT_VideoFmt_ePAL_B:
223	case BFMT_VideoFmt_ePAL_B1:
224	case BFMT_VideoFmt_ePAL_D:
225	case BFMT_VideoFmt_ePAL_D1:
226	case BFMT_VideoFmt_ePAL_G:
227	case BFMT_VideoFmt_ePAL_H:
228	case BFMT_VideoFmt_ePAL_K:
229	case BFMT_VideoFmt_ePAL_I:
230	case BFMT_VideoFmt_ePAL_M:
231	case BFMT_VideoFmt_ePAL_N:
232	case BFMT_VideoFmt_ePAL_NC:
233	start_delay = 0xE;
234	ulActiveLine = 22;
235	break;
236	case BFMT_VideoFmt_e576p_50Hz:
237	/* Assumes use of special 54 MHz VEC IT microcode */
238	start_delay = 0x7;
239	ulActiveLine = 42;
240	#if defined(BVBI_P_WSE_VER3) \|\| defined(BVBI_P_WSE_VER4) \|\| \
241	defined(BVBI_P_WSE_VER5)
242	iDecimate = BCHP_WSE_0_control_DECIMATOR_EN_ENABLE;
243	#endif
244	break;
245	case BFMT_VideoFmt_eSECAM_L:
246	case BFMT_VideoFmt_eSECAM_B:
247	case BFMT_VideoFmt_eSECAM_G:
248	case BFMT_VideoFmt_eSECAM_D:
249	case BFMT_VideoFmt_eSECAM_K:
250	case BFMT_VideoFmt_eSECAM_H:
251	start_delay = 0x18;
252	ulActiveLine = 22;
253	break;
254
255	default:
256	start_delay = 0x0;
257	ulActiveLine = 0;
258	if (bActive)
259	{
260	BDBG_ERR(("BVBI_WSSE: video format %d not supported",
261	eVideoFormat));
262	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
263	}
264	}
265	if (is656)
266	{
267	#if (BVBI_P_NUM_WSE_656 >= 1)
268	/* PR18010 workaround, with exception. */
269	if (!bPR18010_bad_line_number)
270	{
271	ulActiveLine -= 1;
272	}
273	#endif
274	}
275
276	/* Program the active line in the control register */
277	ulControlReg = BREG_Read32 (hReg, BCHP_WSE_0_control + ulCoreOffset);
278	if (is656)
279	{
280	#if (BVBI_P_NUM_WSE_656 >= 1)
281	ulControlReg &=
282	~BCHP_MASK (WSE_ANCIL_0_control, active_line );
283	ulControlReg \|=
284	BCHP_FIELD_DATA (WSE_ANCIL_0_control, active_line, ulActiveLine);
285	#ifdef BVBI_P_HAS_WSE_PARITY
286	#if defined(BVBI_P_WSE_VER1)
287	ulControlReg &=
288	~BCHP_MASK (WSE_ANCIL_0_control, AUTO_PARITY_TYP_656 );
289	ulControlReg \|=
290	BCHP_FIELD_ENUM (WSE_ANCIL_0_control, AUTO_PARITY_TYP_656, ODD);
291	#endif
292	ulControlReg &=
293	~BCHP_MASK (WSE_ANCIL_0_control, AUTO_PARITY_EN_656 );
294	ulControlReg \|=
295	BCHP_FIELD_DATA (WSE_ANCIL_0_control, AUTO_PARITY_EN_656, 1);
296	#endif
297	#endif
298	}
299	else
300	{
301	ulControlReg &=
302	~BCHP_MASK (WSE_0_control, active_line );
303	ulControlReg \|=
304	BCHP_FIELD_DATA (WSE_0_control, active_line, ulActiveLine);
305	ulControlReg &=
306	~BCHP_MASK (WSE_0_control, start_delay );
307	ulControlReg \|=
308	BCHP_FIELD_DATA (WSE_0_control, start_delay, start_delay);
309	#ifdef BVBI_P_HAS_WSE_PARITY
310	ulControlReg &=
311	~BCHP_MASK (WSE_0_control, AUTO_PARITY_TYP );
312	ulControlReg \|=
313	BCHP_FIELD_ENUM (WSE_0_control, AUTO_PARITY_TYP, ODD);
314	#if defined(BVBI_P_WSE_VER1)
315	ulControlReg &=
316	~BCHP_MASK (WSE_0_control, AUTO_PARITY_TYP_656 );
317	ulControlReg \|=
318	BCHP_FIELD_ENUM (WSE_0_control, AUTO_PARITY_TYP_656, ODD);
319	#endif
320	ulControlReg &=
321	~BCHP_MASK (WSE_0_control, AUTO_PARITY_EN );
322	ulControlReg \|=
323	BCHP_FIELD_DATA (WSE_0_control, AUTO_PARITY_EN , 1);
324	ulControlReg &=
325	~BCHP_MASK (WSE_0_control, AUTO_PARITY_EN_656 );
326	ulControlReg \|=
327	BCHP_FIELD_DATA (WSE_0_control, AUTO_PARITY_EN_656, 1);
328	#endif
329	#if defined(BVBI_P_WSE_VER3) \|\| defined(BVBI_P_WSE_VER4) \|\| \
330	defined(BVBI_P_WSE_VER5)
331	ulControlReg &=
332	~BCHP_MASK (WSE_0_control, DECIMATOR_EN );
333	ulControlReg \|=
334	BCHP_FIELD_DATA (WSE_0_control, DECIMATOR_EN, iDecimate);
335	#endif
336	}
337	BREG_Write32 (hReg, BCHP_WSE_0_control + ulCoreOffset, ulControlReg);
338
339	eErr = BERR_TRACE (BVBI_P_WSS_Encode_Enable_isr (
340	hReg, is656, hwCoreIndex, BFMT_VideoFmt_ePAL_G, bActive));
341	if (eErr != BERR_SUCCESS)
342	goto done;
343
344	done:
345	BDBG_LEAVE(BVBI_P_WSS_Enc_Program);
346	return eErr;
347	}
348
349	uint32_t BVBI_P_WSS_Encode_Data_isr (
350	BREG_Handle hReg,
351	bool is656,
352	uint8_t hwCoreIndex,
353	BAVC_Polarity polarity,
354	uint16_t usData)
355	{
356	uint32_t ulCoreOffset;
357	uint32_t ulDataReg;
358	uint32_t ulErrInfo = 0;
359
360	BDBG_ENTER(BVBI_P_WSS_Encode_Data_isr);
361
362	/* WSS is for top field only */
363	if ((polarity != BAVC_Polarity_eTopField) &&
364	(polarity != BAVC_Polarity_eFrame))
365	{
366	return BVBI_LINE_ERROR_PARITY_CONFLICT;
367	}
368
369	/* Figure out which encoder core to use */
370	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
371	if (ulCoreOffset == 0xFFFFFFFF)
372	{
373	/* This should never happen! This parameter was checked by
374	BVBI_Encode_Create() */
375	BDBG_LEAVE(BVBI_P_WSS_Encode_Data_isr);
376	return (uint32_t)(-1);
377	}
378
379	/* Apply the WSS parity bit */
380	#ifndef BVBI_P_HAS_WSE_PARITY
381	usData = BVBI_P_AddWSSparity (usData);
382	#endif
383
384	/* Write new register value */
385	ulDataReg = BREG_Read32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset);
386	ulDataReg &=
387	~BCHP_MASK (WSE_0_wss_data, wss_data );
388	ulDataReg \|=
389	BCHP_FIELD_DATA (WSE_0_wss_data, wss_data, (uint32_t)usData);
390	BREG_Write32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset, ulDataReg);
391
392	BDBG_LEAVE(BVBI_P_WSS_Encode_Data_isr);
393	return ulErrInfo;
394	}
395
396	BERR_Code BVBI_P_WSS_Encode_Enable_isr (
397	BREG_Handle hReg,
398	bool is656,
399	uint8_t hwCoreIndex,
400	BFMT_VideoFmt eVideoFormat,
401	bool bActive)
402	{
403	/*
404	Programming note: the implementation here assumes that the bitfield layout
405	within registers is the same for all WSS encoder cores in the chip.
406
407	If a chip is built that has multiple WSS encoder cores that are not
408	identical, then this routine will have to be redesigned.
409	*/
410	uint32_t ulCoreOffset;
411	uint32_t ulControlReg;
412
413	/* TODO: handle progressive video */
414	BSTD_UNUSED (eVideoFormat);
415
416	BDBG_ENTER(BVBI_P_WSS_Encode_Enable_isr);
417
418	/* Figure out which encoder core to use */
419	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
420	if (ulCoreOffset == 0xFFFFFFFF)
421	{
422	/* This should never happen! This parameter was checked by
423	BVBI_Encode_Create() */
424	BDBG_LEAVE(BVBI_P_WSS_Encode_Enable_isr);
425	return BERR_TRACE(BERR_INVALID_PARAMETER);
426	}
427
428	#if (BVBI_P_NUM_WSE_656 >= 1)
429	if (!is656)
430	#endif
431	{
432	ulControlReg = BREG_Read32 (hReg, BCHP_WSE_0_control + ulCoreOffset);
433	ulControlReg &= ~BCHP_MASK (WSE_0_control, enable );
434	if (bActive)
435	{
436	ulControlReg \|= BCHP_FIELD_DATA (WSE_0_control, enable, 1);
437	}
438	else
439	{
440	ulControlReg \|= BCHP_FIELD_DATA (WSE_0_control, enable, 0);
441	}
442	BREG_Write32 (hReg, BCHP_WSE_0_control + ulCoreOffset, ulControlReg);
443	}
444
445	BDBG_LEAVE(BVBI_P_WSS_Encode_Enable_isr);
446	return BERR_SUCCESS;
447	}
448
449
450	/***************************************************************************
451	* Static (private) functions
452	***************************************************************************/
453
454	/***************************************************************************
455	*
456	*/
457	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex)
458	{
459	uint32_t ulCoreOffset = 0xFFFFFFFF;
460
461	if (is656)
462	{
463	#if (BVBI_P_NUM_WSE_656 >= 1)
464	ulCoreOffset = (BCHP_WSE_ANCIL_0_control - BCHP_WSE_0_control);
465	#endif
466	}
467	else
468	{
469	switch (hwCoreIndex)
470	{
471	#if (BVBI_P_NUM_WSE >= 1)
472	case 0:
473	ulCoreOffset = 0;
474	break;
475	#endif
476	#if (BVBI_P_NUM_WSE >= 2)
477	case 1:
478	ulCoreOffset = (BCHP_WSE_1_control - BCHP_WSE_0_control);
479	break;
480	#endif
481	#if (BVBI_P_NUM_WSE >= 3)
482	case 2:
483	ulCoreOffset = (BCHP_WSE_2_control - BCHP_WSE_0_control);
484	break;
485	#endif
486	default:
487	break;
488	}
489	}
490
491	return ulCoreOffset;
492	}

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_wsse.c

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