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bvdc_priv.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvdc_priv.c $
11	* $brcm_Revision: Hydra_Software_Devel/145 $
12	* $brcm_Date: 3/1/12 11:46a $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vdc/7038/bvdc_priv.c $
19	*
20	* Hydra_Software_Devel/145 3/1/12 11:46a yuxiaz
21	* SW7425-2526, SW7425-1182: Added runtime query capabilities for source
22	* in VDC.
23	*
24	* Hydra_Software_Devel/144 1/11/12 3:06p darnstein
25	* SW7125-1124: merge DCS Hybrid+ to main branch. DCS almost ready for
26	* production.
27	*
28	* Hydra_Software_Devel/SW7125-1124/1 12/1/11 6:39p darnstein
29	* SW7125-1124: change definition of IT_VER to identify early version of
30	* IT hardware that has PCL_6, PCL_7, and PCL_8 registers.
31	*
32	* Hydra_Software_Devel/143 12/1/11 4:33p yuxiaz
33	* SW7425-968, SW7344-95: Merged into mainline.: added independent source
34	* clipping of right window in 3D mode.
35	*
36	* Hydra_Software_Devel/142 11/23/11 4:25p tdo
37	* SW7435-9: Add support for CMP4-5, GFD4-5, MFD3, VFD5
38	*
39	* Hydra_Software_Devel/141 10/14/11 11:25p vanessah
40	* SW7425-1027: add gcd calculation for transcoding
41	*
42	* Hydra_Software_Devel/140 9/15/11 11:29a vanessah
43	* SW7425-923: B0 STG NRT mode
44	*
45	* Hydra_Software_Devel/139 8/31/11 11:19a syang
46	* SW7425-1170: pxlAspRatio passed to ViCE2 is corrected to x<<16 \| y
47	* format
48	*
49	* Hydra_Software_Devel/138 8/27/11 7:22p hongtaoz
50	* SW7425-1132: replaced slip2lock boolean flag with integer counter to
51	* fix a timing sensitive hang conditiion when NRT sync-locked window is
52	* brought up;
53	*
54	* Hydra_Software_Devel/137 8/26/11 5:38p syang
55	* SW7425-1170: merge from branch SW7572-1170
56	*
57	* Hydra_Software_Devel/SW7425-1170/2 8/26/11 4:21p syang
58	* SW7425-1170: refactor pixel aspect ratio related code
59	*
60	* Hydra_Software_Devel/SW7425-1170/1 8/23/11 6:18p vanessah
61	* SW7425-1170: ASP cleanup
62	*
63	* Hydra_Software_Devel/136 7/18/11 11:20a vanessah
64	* SW7425-835: SW7425-923: fix ViCE2 channel id bug + B0 STG
65	*
66	* Hydra_Software_Devel/135 7/11/11 2:17p tdo
67	* SW7420-1971: Video Pause seen when VEC alignment is going on. Add flag
68	* to keep BVN connected while doing alignment.
69	*
70	* Hydra_Software_Devel/134 6/10/11 6:26p hongtaoz
71	* SW7425-704: fixed compile error for chips without STG;
72	*
73	* Hydra_Software_Devel/133 6/10/11 5:49p hongtaoz
74	* SW7425-704: add NRT mode support to VDC; moved the STG meta data
75	* passing from window writer isr to reader isr; added bStallStc flag
76	* support;
77	*
78	* Hydra_Software_Devel/132 3/2/11 11:29a jessem
79	* SW7425-135: Fixed incorrect indexing with CMP1 and CMP2 windows.
80	*
81	* Hydra_Software_Devel/131 11/11/10 7:29p albertl
82	* SW7125-364: Fixed BVDC_P_CbIsDirty and added assert to check bitfields
83	* in dirty bits fit within union integer representation. Fixed naming
84	* of dirty bits.
85	*
86	* Hydra_Software_Devel/130 10/25/10 2:57p pntruong
87	* SW7420-619: Leave csc dither off until further clarification of usage
88	* that does not introduce side-effects.
89	*
90	* Hydra_Software_Devel/129 10/11/10 12:43p jessem
91	* SW7420-173: Added support for VFD as source feature.
92	*
93	* Hydra_Software_Devel/128 6/23/10 4:59p rpan
94	* SW7400-2808: Stop enabling BVN while aligning VECs.
95	*
96	* Hydra_Software_Devel/127 5/7/10 7:19p albertl
97	* SW7125-364: Changed dirty bits to use union structure to avoid type-pun
98	* warnings
99	*
100	* Hydra_Software_Devel/126 4/19/10 10:18p tdo
101	* SW3548-2814: Improvements to VDC ulBlackMagic. Move
102	* BDBG_OBJECT_ID_DECLARE private header files instead of .c.
103	*
104	* Hydra_Software_Devel/125 4/7/10 11:34a tdo
105	* SW3548-2814: Improvements to VDC ulBlackMagic. Rename TLA
106	*
107	* Hydra_Software_Devel/124 4/5/10 4:12p tdo
108	* SW3548-2814: Improvements to VDC ulBlackMagic
109	*
110	* Hydra_Software_Devel/123 3/17/10 12:04p syang
111	* SW7405-4046: set canvas ctrl after sur ctrl; handle gfx win vnet the
112	* same as video; ensure that reader and writer vnetState match in sync-
113	* locked case; aligned width up to even for stride in feeder and cap;
114	* assert mosaic mode doesn't co-exist with dest cut;
115	*
116	* Hydra_Software_Devel/122 3/16/10 4:34p rpan
117	* SW7340-144: Attempt to fix a Coverity warning.
118	*
119	* Hydra_Software_Devel/121 1/6/10 3:41p rpan
120	* SW7468-64: Consolidate VEC modulo count trigger implementation.
121	*
122	* Hydra_Software_Devel/120 12/21/09 2:45p rpan
123	* SW7468-30: 1) When OSCL is enabled for 1080p display, top and bottom
124	* RDC slots are used for building RULs.
125	* 2) Addressed the video format stored at hCompistor being overwritten
126	* issue.
127	*
128	* Hydra_Software_Devel/119 3/18/09 10:22a rpan
129	* PR53104: Always build format switch RUL as long as VEC is switching
130	* format. Otherwise, we may get stuck in format swithing if somehow the
131	* first TOP field interrupt is missed.
132	*
133	* Hydra_Software_Devel/118 1/8/09 2:26p rpan
134	* PR50391: Renabled the VEC RUL execution mechanism after fixing a number
135	* of RDC related issues.
136	*
137	* Hydra_Software_Devel/117 12/24/08 10:40a rpan
138	* PR50391: Back out the change that adds NOP to RUL. This occassionally
139	* caused ApplyChange timeout.
140	*
141	* Hydra_Software_Devel/116 12/24/08 10:28a rpan
142	* PR50391: Always add a NOP to RUL during format switch. This helps
143	* silent some RDC check messages.
144	*
145	* Hydra_Software_Devel/115 12/18/08 6:49p rpan
146	* PR50391: Changes to make sure format switch RUL can always be executed.
147	*
148	* Hydra_Software_Devel/114 11/12/08 3:13p tdo
149	* PR48642: Provide clipping rect for histo luma region
150	*
151	* Hydra_Software_Devel/113 8/8/08 3:29p yuxiaz
152	* PR45484: Enable Dithering in VDC.
153	*
154	* Hydra_Software_Devel/112 5/22/08 1:19p pntruong
155	* PR42475, PR41898: Rollback pr41898. Need re-revaluation of resource
156	* releasing.
157	*
158	* Hydra_Software_Devel/111 4/18/08 1:43p pntruong
159	* PR41898: Need better synchronization of window states. Synchronize the
160	* releases of resource and vnetmode together in writer task.
161	*
162	* Hydra_Software_Devel/110 3/25/08 3:17p syang
163	* PR 40431: add complete assert for critical section protection among src
164	* _isr, dsp _isr, and ApplyChanges
165	*
166	* Hydra_Software_Devel/109 2/29/08 4:19p yuxiaz
167	* PR39158: Implement dithering in various BVN components for 3548.
168	*
169	* Hydra_Software_Devel/108 9/24/07 3:42p hongtaoz
170	* PR34955: track and clean up the sync-slipped mpeg PIP source during
171	* display format switch;
172	*
173	* Hydra_Software_Devel/107 2/20/07 2:56p jessem
174	* PR25235: Removed the use of rate mask and replaced with actual value of
175	* source frame and display refresh rates.
176	*
177	* Hydra_Software_Devel/106 1/18/07 11:35a hongtaoz
178	* PR23260: disable display triggers at destroy for clean shutdown;
179	*
180	* Hydra_Software_Devel/105 10/25/06 3:45p hongtaoz
181	* PR25166: avoid flushing the same cached RUL twice in a vsync isr;
182	*
183	* Hydra_Software_Devel/104 7/23/06 4:23p hongtaoz
184	* PR22437: 1st sync-lock source _isr cleans up display slip RUL; when a
185	* mpeg source's last window is disconnected, clean up source slots
186	* immediately; when mpeg source is muting, don't perform 50->60
187	* conversion to avoid video freeze or flash artifact;
188	*
189	* Hydra_Software_Devel/103 7/17/06 1:01p hongtaoz
190	* PR22713: increased the synlock transfer semaphore count; display _isr
191	* cleans up source slots only when the semaphore count is 0;
192	*
193	* Hydra_Software_Devel/102 7/13/06 10:56a jessem
194	* PR 22389: Added BVDC_P_MapSrcFrameRateToVerticalRefreshRate_isr.
195	*
196	* Hydra_Software_Devel/101 5/26/06 3:42p pntruong
197	* PR20642: Refactored handling of hList.
198	*
199	* Hydra_Software_Devel/99 4/6/06 1:56p pntruong
200	* PR20642: Optimized VDC codes (refactoring).
201	*
202	* Hydra_Software_Devel/98 2/9/06 4:15p pntruong
203	* PR19270: HDCP glitches at wrap of Sarnoff 1080i DYNPICTS.TRP stream.
204	* Update hdmi rate manager in vertical blanking to avoid glitches.
205	*
206	* Hydra_Software_Devel/96 1/25/06 10:58p pntruong
207	* PR19172: Black-screen with latest VDC on 97398. The mosaic added 4
208	* more slots for capture compositing surface this pushes the hddvi slot
209	* out, and not all slot has track execution. This causes the update
210	* format rul of hddvi not properly execute and cause hddvi not to lock.
211	* Fixes by freeing non-used frame slot in vdec/656/hddvi, and free up
212	* more rdc vars to be used for track execution.
213	*
214	* Hydra_Software_Devel/95 10/11/05 11:18a hongtaoz
215	* PR15495: back out previous change; single RUL applied to dual slots
216	* needs further work to be robust;
217	*
218	* Hydra_Software_Devel/94 10/10/05 3:23p hongtaoz
219	* PR15495: combine T/B RUL in case of critical double RULs;
220	*
221	* Hydra_Software_Devel/93 9/16/05 2:30p hongtaoz
222	* PR16812: when synclock transfers to new cmp, reset semaphore at
223	* display_isr also in case mpeg isr stops calling back;
224	*
225	* Hydra_Software_Devel/92 8/29/05 3:30p hongtaoz
226	* PR16812, PR15495: build both T/B RULs for sync-slipped playback side
227	* muting RUL and not touch window playback side before the new vnet RUL
228	* is executed; restore window's current shutdown state without affecting
229	* user setting;
230	*
231	* Hydra_Software_Devel/91 8/18/05 1:18p pntruong
232	* PR15757, PR16391, PR16411, PR12519, PR14791, PR15535, PR15206, PR15778:
233	* Improved bandwidth for cropping/scaler/capture/playback. Unified
234	* window shutdown sequence for destroy, reconfigure mad/scaler, and/or
235	* reconfigure result of source changes. And miscellances fixes from
236	* above PRs.
237	*
238	* Hydra_Software_Devel/XVDPhase1/XVDPhase1_merge/1 8/16/05 5:24p hongtaoz
239	* PR12519: take in fix from main-line;
240	*
241	* Hydra_Software_Devel/90 6/14/05 1:35p hongtaoz
242	* PR14510, PR15163, PR15743: avoid repeated faked triggers;
243	*
244	* Hydra_Software_Devel/XVDPhase1/2 5/2/05 11:22p pntruong
245	* PR15084: Monitor both triggers when source lost triggers.
246	*
247	* Hydra_Software_Devel/XVDPhase1/1 5/2/05 4:54p pntruong
248	* PR12519, PR13121, PR15048, PR15084, PR15100: Dynamically re-allocate
249	* capture in bvn path to reduce memory consumption and bandwith.
250	*
251	* Hydra_Software_Devel/2 5/1/05 11:40p pntruong
252	* Added monitoring of both triggers, since hddvi does not always trigger
253	* frame for progressive.
254	*
255	* Hydra_Software_Devel/1 5/1/05 4:49p pntruong
256	* XVDPhase1 branch off. Temp storage so we can keep track of changes.
257	*
258	* Hydra_Software_Devel/89 4/21/05 5:51p hongtaoz
259	* PR14868: force trigger the correct vdec src slot;
260	*
261	* Hydra_Software_Devel/88 4/20/05 10:51a pntruong
262	* PR14834: Reconnecting linein with MAD enabled will put video output
263	* into bad state.
264	*
265	* Hydra_Software_Devel/87 4/18/05 2:45p yuxiaz
266	* PR14808: Force trigger the slot lose trigger based on input source
267	* format for hd_dvi. Fixed src/window state machine for HD_DVI.
268	*
269	* Hydra_Software_Devel/86 4/8/05 3:38p pntruong
270	* PR14018, PR14011, PR14450, PR14648: Vec to generate fake trigger when
271	* source is pulled or not configured correctly or any condition that
272	* cause source to lose trigger. This vec's fake trigger enable the
273	* applychanges to go thru, and does not result in timeout.
274	*
275	* Hydra_Software_Devel/85 3/11/05 9:21a pntruong
276	* PR14112, PR14046: Fixed hd/sd channel change for progressive mode.
277	*
278	* Hydra_Software_Devel/84 2/1/05 3:06p pntruong
279	* PR14003: Rapid open and close of the same mpeg window will cause feeder
280	* error.
281	*
282	* Hydra_Software_Devel/83 1/31/05 6:52p pntruong
283	* PR12790: Noticeable screen flickering on digital to digital channel
284	* change. Also, used _isr version of kni functions in critical
285	* sections.
286	*
287	* Hydra_Software_Devel/82 1/28/05 9:17a pntruong
288	* PR13321: Stress test failed (MAIN/PIP swap and format change).
289	*
290	* Hydra_Software_Devel/81 1/26/05 4:53p pntruong
291	* PR13450, PR12854, PR13549, PR13617, PR13618, PR13683, PR13321, PR13646,
292	* PR13447, PR13429: Disabled vec triggers when vec reset (e.g. format
293	* change) to prevent it from continuosly executing same register update
294	* list that cause system locked up and/or causing vec errors.
295	*
296	* Hydra_Software_Devel/80 12/3/04 4:41p pntruong
297	* PR13453: Pip window deletion timeout error with BCM7038B0 Phase 4
298	* reference software.
299	*
300	* Hydra_Software_Devel/79 12/2/04 7:17p pntruong
301	* PR12854: Repeated display format changes causes loss of sync and
302	* flashing video.
303	*
304	* Hydra_Software_Devel/78 11/29/04 4:57p pntruong
305	* PR13076, PR11749: No need to keep track of synclock dummy rul.
306	*
307	* Hydra_Software_Devel/77 11/23/04 8:54p pntruong
308	* PR13076, PR11749: Video jitter under heavy system load. Added RUL
309	* execution check to reduce number of programmed registers.
310	*
311	* Hydra_Software_Devel/76 11/16/04 8:01p pntruong
312	* PR13076: Video jitter under heavy system load. Added some
313	* optimizations, additional work needed.
314	*
315	* Hydra_Software_Devel/75 11/12/04 5:43p pntruong
316	* PR13242: Repeated stop/start of live digital decode produces vertical
317	* split-screen which moves to the right with each restart.
318	*
319	* Hydra_Software_Devel/74 11/2/04 5:29p pntruong
320	* PR13076: Added cached memory support for rul.
321	*
322	* Hydra_Software_Devel/73 11/1/04 2:11p yuxiaz
323	* PR12790: Add sync slip to sync lock transition to fix graphics
324	* flickering on analog to digital channel change.
325	*
326	* Hydra_Software_Devel/72 10/29/04 3:55p hongtaoz
327	* PR13125: added time stamp at the end of display RUL and Vdec RUL to
328	* measure RUL execution time;
329	*
330	* Hydra_Software_Devel/71 10/12/04 3:50p yuxiaz
331	* PR12790: Fixed flickering for digital to digital channel change in
332	* Brutus.
333	*
334	* Hydra_Software_Devel/70 10/6/04 3:40p yuxiaz
335	* PR12790: Fixed flickering for digital to digital channel change.
336	*
337	* Hydra_Software_Devel/69 10/6/04 2:27p pntruong
338	* PR12854: Repeated display format changes causes loss of sync and
339	* flashing video.
340	*
341	* Hydra_Software_Devel/68 10/5/04 4:27p pntruong
342	* PR12854: Increased the vsync delay for build front-end blocks when
343	* format change.
344	*
345	* Hydra_Software_Devel/67 10/5/04 2:08p pntruong
346	* PR12907: Timing problem in VDC.
347	*
348	* Hydra_Software_Devel/66 9/15/04 3:55p yuxiaz
349	* PR 12606: Fixed channel change in simul mode.
350	*
351	* Hydra_Software_Devel/65 9/10/04 4:13p pntruong
352	* PR12615: Re-intitial multibuffer when window re-create to remove old
353	* states.
354	*
355	* Hydra_Software_Devel/64 9/9/04 8:00p pntruong
356	* PR12615: Re-intitial multibuffer when window re-create to remove old
357	* states.
358	*
359	* Hydra_Software_Devel/63 9/9/04 1:40p pntruong
360	* PR11573: Remove 3rd display slot from VDC allocation.
361	*
362	* Hydra_Software_Devel/62 8/31/04 1:05p pntruong
363	* PR11266: Added the visibility or shutoff gfx feeder check for the
364	* sync-slip case.
365	*
366	* Hydra_Software_Devel/61 8/26/04 6:35p syang
367	* PR 11266: added src picture call back func for gfx; added src state to
368	* call back func for XVD sync;
369	*
370	* Hydra_Software_Devel/60 8/18/04 1:59p pntruong
371	* PR12231: Fixed for gfx window as well.
372	*
373	* Hydra_Software_Devel/59 8/12/04 1:49p pntruong
374	* PR12272: TAB is not enabled the first time when bring up analog.
375	*
376	* Hydra_Software_Devel/58 8/11/04 3:47p pntruong
377	* PR12246: Video may be lost on main display when stress HD/SD streams/
378	* formats change in 10-20 minutes.
379	*
380	* Hydra_Software_Devel/57 8/2/04 4:36p pntruong
381	* PR11981: Improved read/modify/write sequence. Factored out duplicate
382	* codes. Removed RDC instructions (any instruction that uses IMM with
383	* VAR) that sensitive to 256-byte boundary.
384	*
385	* Hydra_Software_Devel/56 7/30/04 12:45p tdo
386	* PR11971: add call to BVDC_P_Pep_BuildRul_isr to build PEP RUL
387	*
388	* Hydra_Software_Devel/55 7/9/04 5:47p pntruong
389	* PR11887: Simplify the computation of rectangles in VDC.
390	*
391	* Hydra_Software_Devel/54 7/8/04 7:19p albertl
392	* PR 7662: Fixed issues with different compositors overwriting 656 and
393	* MISC settings used by other compostiors. Disabled feeder to Bypass
394	* when 656 is inactive.
395	*
396	* Hydra_Software_Devel/53 7/6/04 8:33a pntruong
397	* PR9957: Prevent create/destroy from effecting hardware in VDC.
398	*
399	* Hydra_Software_Devel/52 6/25/04 3:26p yuxiaz
400	* PR 11659: Rename RDC variables reserved for VDC to
401	* BRDC_Variable_VDC_num. Move the defination of reserved variables back
402	* to RDC.
403	*
404	* Hydra_Software_Devel/50 6/25/04 9:09a yuxiaz
405	* PR 11659: Use reserved RDC variables defined in VDC instead of the ones
406	* in RDC. Variables defined in RDC can be used by all the moduals.
407	*
408	* Hydra_Software_Devel/49 6/22/04 2:10p yuxiaz
409	* PR 11612: Fixed mutil-buffering after mode switching. Fixed pitch for
410	* capture and playback.
411	*
412	* Hydra_Software_Devel/48 6/22/04 1:25p hongtaoz
413	* PR11549: added MAD support for 720p/1080i format;
414	*
415	* Hydra_Software_Devel/47 6/17/04 4:37p pntruong
416	* PR9957: Prevent create/destroy from effecting hardware in VDC.
417	*
418	* Hydra_Software_Devel/46 6/16/04 7:38p hongtaoz
419	* PR11422: fixed mode switch problem with analog video source; modified
420	* multi-buffering algorithm to avoid deadlock.
421	*
422	* Hydra_Software_Devel/45 6/3/04 9:35p albertl
423	* PR 7662: Bringup of 656 output for B0.
424	*
425	* Hydra_Software_Devel/44 5/24/04 6:59p jasonh
426	* PR 11189: Merge down from B0 to main-line
427	*
428	* Hydra_Software_Devel/Refsw_Devel_7038_B0/3 5/21/04 6:57p hongtaoz
429	* PR10944: added initial MAD32 support of 480i->480p;
430	*
431	* Hydra_Software_Devel/Refsw_Devel_7038_B0/2 5/17/04 7:35p hongtaoz
432	* PR10944: added initial MAD32 support;
433	*
434	* Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/29/04 7:30p hongtaoz
435	* PR10852: simplified the color space conversion process;
436	* PR9996: supported multi-standard color space conversion at compositor
437	* with color primaries matching;
438	* PR8761: fixed part of C++ compiling errors;
439	*
440	* Hydra_Software_Devel/42 4/27/04 4:42p yuxiaz
441	* PR 10699: Added time stamp tracking for multi-buffering debugging.
442	*
443	* Hydra_Software_Devel/41 4/13/04 5:41p pntruong
444	* PR8987: Added support for output format change from interlace to/from
445	* progressive format.
446	*
447	* Hydra_Software_Devel/40 4/7/04 2:14p yuxiaz
448	* PR 10404: Combine BRDC_Slot_SetNumEntries_isr and
449	* BRDC_Slot_AssignList_isr into BRDC_Slot_SetList_isr so both RUL
450	* address and count are set in one atomic function.
451	*
452	* Hydra_Software_Devel/39 4/1/04 2:25p hongtaoz
453	* PR9996: add color space conversion for different video surfaces in
454	* compositor.
455	*
456	* Hydra_Software_Devel/38 3/29/04 3:23p pntruong
457	* PR8987: Removed direct register write timer code as it would need to
458	* be in a separate basemodule before we can use it. Added counter to
459	* ignore vec reset in build RUL until vec stable. This fixed the
460	* display output format change to/from 1080i & 480i and 720p & 480p.
461	*
462	* Hydra_Software_Devel/37 3/23/04 8:42p pntruong
463	* PR8987: Added debug capability to output interrupt timing. Use
464	* BVDC_P_USE_TIMER_DEBUGGER to enable or disable timing feature. This
465	* currently use TIMER2 timer watchdog.
466	*
467	* Hydra_Software_Devel/36 3/22/04 8:13p pntruong
468	* PR8987: Added fixed for output format change from I->I, and P->P.
469	* Additional work required for I->P and P->I.
470	*
471	* Hydra_Software_Devel/35 3/16/04 12:37p maivu
472	* PR 8987: Update Vec state when mode is switched
473	*
474	* Hydra_Software_Devel/34 3/12/04 4:23p yuxiaz
475	* PR 10032: Move BVDC_P_Vnet_BuildRul_isr to source isr.
476	*
477	* Hydra_Software_Devel/33 3/11/04 12:44p pntruong
478	* PR9865: Make iTransitionPic per compositor based.
479	*
480	* Hydra_Software_Devel/32 3/11/04 10:01a hongtaoz
481	* PR9865: VDC sync lock determination at video window open/close;
482	* 1) a vdc-wise global flag "bSupportSlip2Lock" is added to turn on/off
483	* the sync-slip to lock on-the-fly transition; by default it's off; only
484	* when all the transition works smoothly, we'll turn on this feature or
485	* put it into pDefSettings for application to decide when calling
486	* BVDC_Open;
487	* 2) when the slip2lock on-the-fly transition is allowed, there will be 2
488	* fields of period for transition to happen; during this period, the -
489	* to-be-locked display would still build sync-slip RUL to avoid
490	* overwriting MFD in case of timing difference between the old sync-
491	* locked vec and newly locked vec;
492	* 3) also during the transition period, the vnet mode would not be
493	* modified to scaler-only mode even if the lock window doesn't require
494	* scaling down, so that the transition fields would be played back from
495	* the captured buffers;
496	*
497	* Hydra_Software_Devel/31 3/8/04 6:37p hongtaoz
498	* PR9917: display freezes and hang when sync-slipped mpeg video window
499	* transitioned to sync-lock on the fly; the reason is that the vnet
500	* switch isn't turn off and the sync-locked compositor is still waiting
501	* for the closed video picture when the sync-locked window is closed.
502	*
503	* Hydra_Software_Devel/30 3/3/04 11:57a hongtaoz
504	* PR9689: Open/Close/Open sequence for video windows doesn't work because
505	* a video window is created with zero window sizes which caused assert,
506	* the fix is to use a flag to indicate whether the window setting being
507	* applied to determine if RUL builder to accomandate that window into
508	* the RUL;
509	*
510	* Hydra_Software_Devel/29 3/3/04 9:46a maivu
511	* PR 8987: Fixed 480p/720p (progressive) mode switching problem.
512	*
513	* Hydra_Software_Devel/28 2/25/04 5:34p maivu
514	* PR 9784, PR 9831: Removed unnecessary initial nop RUL, since we're
515	* double buffering the Ruls now.
516	*
517	* Hydra_Software_Devel/27 2/20/04 9:58a pntruong
518	* PR8987: Added code to re-initialized RULs, and reset each window's
519	* block.
520	*
521	* Hydra_Software_Devel/26 2/4/04 1:32p pntruong
522	* PR8861: Analyze VDC Rul building for next field.
523	*
524	* Hydra_Software_Devel/25 2/3/04 11:02a pntruong
525	* PR9075: Double buffer RULs in VDC. Need to keep track of index for
526	* each slot.
527	*
528	* Hydra_Software_Devel/24 2/2/04 4:33p pntruong
529	* PR9559: 720p and 480p are broken in VDC and not working on
530	* mvd_vdc_test.
531	*
532	* Hydra_Software_Devel/23 1/23/04 3:48p pntruong
533	* PR9459: BVDC_Window_Get_? functions return incorrect state.
534	*
535	* Hydra_Software_Devel/22 1/21/04 10:30a yuxiaz
536	* PR 9076: Change BRDC_Slot_AssignList to _isr for double buffer RUL.
537	*
538	* Hydra_Software_Devel/21 1/20/04 8:32p pntruong
539	* PR9075: Double buffer RULs in VDC.
540	*
541	* Hydra_Software_Devel/20 1/14/04 4:39p yuxiaz
542	* PR 9076: Change isr functions to _isr.
543	*
544	* Hydra_Software_Devel/19 12/29/03 6:42p pntruong
545	* PR 9117: Refactor BINT to no longer use strings to specify interrupt
546	* name.
547	*
548	* Hydra_Software_Devel/18 12/19/03 4:35p pntruong
549	* PR9073: Fix interrupt abstraction for MVD to VDC.
550	*
551	* Hydra_Software_Devel/17 12/10/03 3:54p syang
552	* PR 8914: ensure DefaultKeyAlpha and other register inited, fixed
553	* prroblem with GFD_0_SRC_START in the case of bottom field
554	*
555	* Hydra_Software_Devel/16 12/5/03 11:55a maivu
556	* PR 8863: always build for current field, instead of next field. Fixes
557	* HD problem.
558	*
559	* Hydra_Software_Devel/15 11/25/03 5:04p pntruong
560	* Added GFX build RUL.
561	*
562	* Hydra_Software_Devel/14 11/24/03 5:02p yuxiaz
563	* Build RUL of next filed in ISR for interlace.
564	*
565	* Hydra_Software_Devel/13 11/7/03 10:02a pntruong
566	* Fxied partial RUL execution. That may result in RDC hang.
567	*
568	* Hydra_Software_Devel/12 10/30/03 6:21p pntruong
569	* Updated window state.
570	*
571	* Hydra_Software_Devel/11 10/29/03 11:45a pntruong
572	* Reformated code.
573	*
574	* Hydra_Software_Devel/10 10/28/03 2:46p maivu
575	* Update the slot entries in hw, after we build the Rul.
576	*
577	* Hydra_Software_Devel/9 10/24/03 5:12p pntruong
578	* Updated RUL building to hanlde sync-lock and sync-slip.
579	*
580	* Hydra_Software_Devel/8 10/14/03 10:53a pntruong
581	* Allocated more RULs to adapt to the way analog fields come in.
582	*
583	* Hydra_Software_Devel/7 10/7/03 5:36p maivu
584	* Added field id to BVDC_P_Vec_BuildRul.
585	*
586	* Hydra_Software_Devel/6 10/6/03 2:50p yuxiaz
587	* Added bvdc_common_priv.h, clean up private include files.
588	*
589	* Hydra_Software_Devel/6 10/6/03 2:48p yuxiaz
590	* Added bvdc_common_priv.h, clean up private include files.
591	*
592	* Hydra_Software_Devel/5 10/2/03 10:31a pntruong
593	* Added backend isr callback.
594	*
595	* Hydra_Software_Devel/4 9/26/03 3:56p pntruong
596	* Removed uneeded functions.
597	*
598	* Hydra_Software_Devel/3 8/22/03 12:00p pntruong
599	* Added create and destroy.
600	*
601	* Hydra_Software_Devel/2 7/28/03 11:29a pntruong
602	* added BDBG_MODULE(BVDC).
603	*
604	* Hydra_Software_Devel/1 7/17/03 5:55p pntruong
605	* Added source.
606	*
607	***************************************************************************/
608	#include "bstd.h" /* standard types */
609	#include "bkni.h" /* memcpy calls */
610	#include "bvdc.h" /* Video display */
611	#include "bdbg.h"
612	#include "bavc.h"
613	#include "bvdc_priv.h"
614	#include "bvdc_common_priv.h"
615	#include "bvdc_compositor_priv.h"
616	#include "bvdc_display_priv.h"
617	#include "bvdc_source_priv.h"
618	#include "bvdc_feeder_priv.h"
619
620	BDBG_MODULE(BVDC_PRIV);
621
622	/***************************************************************************
623	* Add an NO-OP into RUL.
624	*
625	*/
626	void BVDC_P_BuildNoOpsRul_isr
627	( BRDC_List_Handle hList )
628	{
629	uint32_t ulCurrentEntries;
630	uint32_t ulNewEntries;
631	uint32_t *pulCurrent;
632	uint32_t *pulStart;
633
634	/* Save the current number of entries, will update number for this list
635	* at the end. */
636	BRDC_List_GetNumEntries_isr(hList, &ulCurrentEntries);
637
638	/* get pointer to list entries */
639	pulStart = pulCurrent =
640	BRDC_List_GetStartCachedAddress_isr(hList) + ulCurrentEntries;
641
642	/* Valid start address */
643	BDBG_ASSERT(pulStart);
644	BVDC_P_BUILD_NO_OPS(pulCurrent);
645
646	/* Update entries count */
647	ulNewEntries = (uint32_t)(pulCurrent - pulStart);
648
649	BRDC_List_SetNumEntries_isr(hList, ulCurrentEntries + ulNewEntries);
650	return;
651	}
652
653
654	/***************************************************************************
655	* Get the currently list pointer and store in pList! Including the
656	* last executed status.
657	*
658	*/
659	void BVDC_P_ReadListInfo_isr
660	( BVDC_P_ListInfo *pList,
661	BRDC_List_Handle hList )
662	{
663	uint32_t ulNumEntries;
664
665	/* Read list info once! This prevent calling into RDC multiple times. */
666	BRDC_List_GetNumEntries_isr(hList, &ulNumEntries);
667	pList->bLastExecuted = BRDC_List_GetLastExecStatus_isr(hList);
668	pList->pulStartNonCached = BRDC_List_GetStartAddress_isr(hList);
669	pList->pulStart = BRDC_List_GetStartCachedAddress_isr(hList);
670	pList->pulCurrent = pList->pulStart + ulNumEntries;
671	return;
672	}
673
674
675	/***************************************************************************
676	* Update the number of entries from pList to hList!
677	*
678	*/
679	void BVDC_P_WriteListInfo_isr
680	( const BVDC_P_ListInfo *pList,
681	BRDC_List_Handle hList )
682	{
683	BERR_Code eRdcErrCode;
684	uint32_t ulNumEntries;
685
686	/* Update the entries again. */
687	ulNumEntries = (uint32_t)(pList->pulCurrent - pList->pulStart);
688	eRdcErrCode = BRDC_List_SetNumEntries_isr(hList, ulNumEntries);
689
690	/* Got to make sure we allocated enough RUL mem! Something that must be
691	* done in BVDC_Open(), and instrumented with tests runs! */
692	BDBG_ASSERT(BERR_SUCCESS == eRdcErrCode);
693	return;
694	}
695
696
697	/***************************************************************************
698	*
699	*/
700	void BVDC_P_Dither_Init
701	( BVDC_P_DitherSetting *pDitherSetting,
702	uint32_t ulLfsrCtrlT0,
703	uint32_t ulLfsrCtrlT1,
704	uint32_t ulLfsrCtrlT2,
705	uint32_t ulLfsrValue )
706	{
707	if(pDitherSetting)
708	{
709	pDitherSetting->ulLfsrSeq = 0; /* once */
710	pDitherSetting->ulLfsrValue = ulLfsrValue;
711	pDitherSetting->ulLfsrCtrlT0 = ulLfsrCtrlT0;
712	pDitherSetting->ulLfsrCtrlT1 = ulLfsrCtrlT1;
713	pDitherSetting->ulLfsrCtrlT2 = ulLfsrCtrlT2;
714
715	pDitherSetting->ulMode = 0; /* 0=rounding, 1=TRUNCATE, 2=Dither */
716	pDitherSetting->ulCh0Offset = 0;
717	pDitherSetting->ulCh1Offset = 0;
718	pDitherSetting->ulCh2Offset = 0;
719	pDitherSetting->ulCh0Scale = 1;
720	pDitherSetting->ulCh1Scale = 1;
721	pDitherSetting->ulCh2Scale = 1;
722	}
723
724	return;
725	}
726
727
728	/***************************************************************************
729	* BVDC_P_CompositorDisplay_isr
730	*
731	* This get call at every display vsync trigger a slot w/ done execution.
732	* We're then building the RUL for the next field/frame.
733	*
734	* pvCompositorHandle contains hCompositor
735	* (iParam2) = BAVC_Polarity_eTopField /BAVC_Polarity_eBotField;
736	*/
737	void BVDC_P_CompositorDisplay_isr
738	( void *pvCompositorHandle,
739	int iParam2 )
740	{
741	uint32_t i;
742	BRDC_Slot_Handle hSlot;
743	BRDC_List_Handle hList;
744	BVDC_P_ListInfo stList;
745	BVDC_Compositor_Handle hCompositor = (BVDC_Compositor_Handle)pvCompositorHandle;
746	BAVC_Polarity eNextFieldId;
747
748	BDBG_ENTER(BVDC_P_CompositorDisplay_isr);
749
750	/* Get The compositor handle from isr callback */
751	eNextFieldId = BVDC_P_NEXT_POLARITY((BAVC_Polarity)(iParam2));
752
753	/* Build Display RUL & Compositor (playback modules) */
754	BDBG_OBJECT_ASSERT(hCompositor, BVDC_CMP);
755	BDBG_OBJECT_ASSERT(hCompositor->hDisplay, BVDC_DSP);
756	BDBG_OBJECT_ASSERT(hCompositor->hVdc, BVDC_VDC);
757
758	/* Display only have T/B slot. */
759	BDBG_ASSERT(BAVC_Polarity_eFrame != (BAVC_Polarity)iParam2);
760
761	/* Basically this guaranteed that interrupt will not run dried. */
762	BDBG_ASSERT(BVDC_P_STATE_IS_INACTIVE(hCompositor)==false);
763
764	/* Make sure the BKNI enter/leave critical section works. */
765	BDBG_ASSERT(0 == hCompositor->hVdc->ulInsideCs);
766	hCompositor->hVdc->ulInsideCs++;
767
768	if((BVDC_P_ItState_eNotActive == hCompositor->hDisplay->eItState) \|\|
769	(BVDC_P_ItState_eSwitchMode == hCompositor->hDisplay->eItState))
770	{
771	/* Detected the force execution, or mode switch reset of vec. */
772	uint32_t ulVecResetDetected = BREG_Read32(hCompositor->hVdc->hRegister,
773	hCompositor->hDisplay->ulRdcVarAddr);
774
775	/* If ulVecResetDetected it means that the last RDC executed a VEC's
776	* reset. At this point we want to change the state of the vec. */
777	if(ulVecResetDetected)
778	{
779	BAVC_Polarity ePolarity;
780	/* Acknowledge reset. */
781	BREG_Write32(hCompositor->hVdc->hRegister, hCompositor->hDisplay->ulRdcVarAddr, 0);
782	BDBG_MSG(("Display[%d]'s state: %s (%s => %d)", hCompositor->eId,
783	(BVDC_P_ItState_eNotActive == hCompositor->hDisplay->eItState) ? "eNotActive" :
784	(BVDC_P_ItState_eSwitchMode == hCompositor->hDisplay->eItState) ? "eSwitchMode" : "eActive",
785	(BAVC_Polarity_eTopField==iParam2)?"T":
786	(BAVC_Polarity_eBotField==iParam2)?"B":"F", ulVecResetDetected));
787	if((BVDC_P_ItState_eSwitchMode == hCompositor->hDisplay->eItState) \|\|
788	(BVDC_P_ItState_eNotActive == hCompositor->hDisplay->eItState))
789	{
790	hCompositor->hDisplay->eItState = BVDC_P_ItState_eActive;
791	}
792
793	/* Clean up Top/Bot display slot/list */
794	for(ePolarity = BAVC_Polarity_eTopField;
795	ePolarity <= BAVC_Polarity_eBotField; ePolarity++)
796	{
797	BVDC_P_CMP_NEXT_RUL(hCompositor, ePolarity);
798	hSlot = BVDC_P_CMP_GET_SLOT(hCompositor, ePolarity);
799	hList = BVDC_P_CMP_GET_LIST(hCompositor, ePolarity);
800	BRDC_List_SetNumEntries_isr(hList, 0);
801	BVDC_P_BuildNoOpsRul_isr(hList);
802	#if BVDC_P_ORTHOGONAL_VEC
803	/* Disable execution tracking. This caused hwTrackCount and
804	* software TrackCount mismatch because only one RUL actually
805	* gets executed.
806	* This is done for orthogonal VEC for now. It may make sense
807	* to apply this for all the VECs.
808	*/
809	BRDC_Slot_UpdateLastRulStatus_isr(hSlot, hList, false);
810
811	#endif
812	BRDC_Slot_SetCachedList_isr(hSlot, hList);
813	#if BVDC_P_ORTHOGONAL_VEC
814	/* Re-enable execution tracking.
815	*/
816	BRDC_Slot_UpdateLastRulStatus_isr(hSlot, hList, true);
817
818	#endif
819	}
820
821	/* Clean up Top/Bot/Frame slot/list of sync-lock source. */
822	if(hCompositor->hSyncLockSrc)
823	{
824	BVDC_P_Source_CleanupSlots_isr(hCompositor->hSyncLockSrc);
825
826	/* clean up mpeg PIP source slots as well if it's not locked */
827	if(hCompositor->hForceTrigPipSrc)
828	{
829	BVDC_P_Source_CleanupSlots_isr(hCompositor->hForceTrigPipSrc);
830	}
831	}
832	/* Re-enable triggers. */
833	BVDC_P_Display_EnableTriggers_isr(hCompositor->hDisplay, true);
834	goto BVDC_P_CompositorDisplay_isr_Done;
835	}
836	}
837
838	/* Check if we're doing frame. If we're doing frame we're use a topfield
839	* slot to trigger the frame slot in source isr for sycn lock. */
840	if((BAVC_Polarity_eBotField != iParam2) &&
841	(!hCompositor->hDisplay->stCurInfo.pFmtInfo->bInterlaced)
842	#if (BVDC_P_SUPPORT_IT_VER >= 2)
843	&& (2 != hCompositor->hDisplay->stCurInfo.ulTriggerModuloCnt)
844	#endif
845	)
846	{
847	eNextFieldId = BAVC_Polarity_eFrame;
848	BVDC_P_CMP_NEXT_RUL(hCompositor, BAVC_Polarity_eTopField);
849	hSlot = BVDC_P_CMP_GET_SLOT(hCompositor, BAVC_Polarity_eTopField);
850	hList = BVDC_P_CMP_GET_LIST(hCompositor, BAVC_Polarity_eTopField);
851	}
852	else
853	{
854	/* eNextField can only be either eTopField or eBotField once
855	* we get here. The following line fixes a Coverity warning.
856	*/
857	eNextFieldId = (BAVC_Polarity_eBotField == eNextFieldId) ?
858	BAVC_Polarity_eBotField : BAVC_Polarity_eTopField;
859
860	/* Get the approriate slot/list for building RUL. */
861	BVDC_P_CMP_NEXT_RUL(hCompositor, eNextFieldId);
862	hSlot = BVDC_P_CMP_GET_SLOT(hCompositor, eNextFieldId);
863	hList = BVDC_P_CMP_GET_LIST(hCompositor, eNextFieldId);
864	}
865
866	/* Reset the RUL entry count and build RUL for backend! */
867	#if BVDC_P_ORTHOGONAL_VEC
868	/* Always tracking execution will simplify a lot of
869	* cases where we check the bLastExecuted flag. It's not
870	* to bad since the size of compositor side RUL for sync-locked
871	* source path is short anyway.
872	*
873	*/
874	BRDC_Slot_UpdateLastRulStatus_isr(hSlot, hList, true);
875	#else
876	BRDC_Slot_UpdateLastRulStatus_isr(hSlot, hList, !hCompositor->hSyncLockSrc);
877	#endif
878	BRDC_List_SetNumEntries_isr(hList, 0);
879	BVDC_P_ReadListInfo_isr(&stList, hList);
880
881	if((BVDC_P_ItState_eSwitchMode == hCompositor->hDisplay->eItState) \|\|
882	(true == hCompositor->hDisplay->bAlignAdjusting && !hCompositor->hDisplay->stCurInfo.stAlignCfg.bKeepBvnConnected))
883	{
884	/* When switching modes or doing VEC alignment, build the Vec only.
885	* Do not enable the front-end blocks yet. When doing VEC alignment VEC
886	* triggers can be fired earlier than normal cases. This may cause
887	* BVN unable to finish processing the picture and result in BVN hang.
888	*/
889	if(BVDC_P_ItState_eSwitchMode == hCompositor->hDisplay->eItState)
890	{
891	BDBG_MSG(("Vec mode switch[%s]: %s to %s",
892	(BAVC_Polarity_eTopField == eNextFieldId) ? "T" :
893	(BAVC_Polarity_eBotField == eNextFieldId) ? "B" : "F",
894	hCompositor->hDisplay->stCurInfo.pFmtInfo->pchFormatStr,
895	hCompositor->hDisplay->stNewInfo.pFmtInfo->pchFormatStr));
896	}
897
898	/* Reset VEC as long as it is in switch mode */
899	BVDC_P_Vec_BuildRul_isr(hCompositor->hDisplay, &stList, eNextFieldId);
900	}
901	else
902	{
903	/* Check if VFD is used a source */
904	for (i = 0; i < hCompositor->pFeatures->ulMaxVideoWindow; i++)
905	{
906	uint32_t j = 0;
907
908	switch (hCompositor->eId)
909	{
910	case BVDC_CompositorId_eCompositor0:
911	j = (i == 0) ? BVDC_P_WindowId_eComp0_V0 : BVDC_P_WindowId_eComp0_V1;
912	break;
913	case BVDC_CompositorId_eCompositor1:
914	j = (i == 0) ? BVDC_P_WindowId_eComp1_V0 : BVDC_P_WindowId_eComp1_V1;
915	break;
916	case BVDC_CompositorId_eCompositor2:
917	j = BVDC_P_WindowId_eComp2_V0;
918	break;
919	case BVDC_CompositorId_eCompositor3:
920	j = BVDC_P_WindowId_eComp3_V0;
921	break;
922	case BVDC_CompositorId_eCompositor4:
923	j = BVDC_P_WindowId_eComp4_V0;
924	break;
925	case BVDC_CompositorId_eCompositor5:
926	j = BVDC_P_WindowId_eComp5_V0;
927	break;
928	default:
929	break;
930	}
931
932	if (hCompositor->ahWindow[j])
933	{
934	if (hCompositor->ahWindow[j]->stCurInfo.hSource)
935	{
936	if (hCompositor->ahWindow[j]->stCurInfo.hSource->hVfdFeeder &&
937	BVDC_P_STATE_IS_ACTIVE(hCompositor->ahWindow[j]->stCurInfo.hSource))
938	{
939	if (hCompositor->ahWindow[j]->stCurInfo.hSource->hVfdFeeder->stCurrSurInfo.hSurface)
940	{
941	BAVC_Polarity ePolarity = (!hCompositor->stCurInfo.pFmtInfo->bInterlaced) ?
942	BAVC_Polarity_eFrame : (BAVC_Polarity)iParam2;
943	BVDC_P_Source_VfdDataReady_isr(hCompositor->ahWindow[j]->stCurInfo.hSource,
944	hCompositor->ahWindow[j], &stList, ePolarity);
945	}
946	}
947	}
948	}
949	}
950
951	/* Window detect window destroy done and set event. */
952	for(i = 0; i < BVDC_P_MAX_WINDOW_COUNT; i++)
953	{
954	if(hCompositor->ahWindow[i])
955	{
956	BVDC_P_Window_UpdateState_isr(hCompositor->ahWindow[i]);
957	}
958	}
959
960	/* A disconnected window causes an mfd source to be orphan and needs a new
961	* compositor to drive it. Since mfd's slots could be driven by t/b/f,
962	* we need to make it complete the last execution before transferring
963	* the force trigger (driving the mfd job) to this compositor. The
964	* mfd _isr will release the semaphore (ulTransferLock == 0) to signal it's
965	* done cleaning up. */
966	if(hCompositor->hSrcToBeLocked)
967	{
968	BDBG_MSG(("cmp[%d] trying to lock new orphan mfd[%d]",
969	hCompositor->eId, hCompositor->hSrcToBeLocked->eId));
970	if(!hCompositor->hSrcToBeLocked->ulTransferLock)
971	{
972	BVDC_P_Source_FindLockWindow_isr(hCompositor->hSrcToBeLocked, true);
973	}
974	else
975	{
976	/* This is a backup to prevent infinite wait for lock transfer in case
977	* the critical mpeg callback is missing during the synclock transfer process; */
978	BDBG_MSG(("Clean up mfd[%d] slots before transfer to new cmp %d",
979	hCompositor->hSrcToBeLocked->eId, hCompositor->hSrcToBeLocked->ulTransferLock, hCompositor->eId));
980	if(--hCompositor->hSrcToBeLocked->ulTransferLock == 0)
981	{
982	/* clean up source slots to get rid of leftover source RULs for old
983	source/windows config; */
984	BVDC_P_Source_CleanupSlots_isr(hCompositor->hSrcToBeLocked);
985	}
986	}
987	}
988
989	/* If Compositor/Display has at least one sync-lock source it will be the
990	* source isr that build the RUL. This return true if it has sync-lock
991	* source. In that case it will just build the RUL to force trigger the
992	* source slot. */
993	if(hCompositor->hSyncLockSrc)
994	{
995	/* this is to prevent gfx flash for slip2lock transitioned display */
996	if(hCompositor->ulSlip2Lock)
997	{
998	BDBG_MSG(("cmp[%d] build slip parts for mfd[%d]",
999	hCompositor->eId, hCompositor->hSyncLockSrc->eId));
1000	BVDC_P_Compositor_BuildSyncSlipRul_isr(hCompositor, &stList, eNextFieldId, true);
1001	}
1002	BVDC_P_Compositor_BuildSyncLockRul_isr(hCompositor, &stList, eNextFieldId);
1003	}
1004	else
1005	{
1006	BVDC_P_Compositor_BuildSyncSlipRul_isr(hCompositor, &stList, eNextFieldId, true);
1007	}
1008
1009	/* Poll for unplug sources. */
1010	for(i = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1011	{
1012	/* Is this the compositor going to handle polling? */
1013	if(hCompositor != hCompositor->hVdc->hCmpCheckSource)
1014	{
1015	break;
1016	}
1017
1018	/* This compositor will check for source that lost triggers or
1019	* otherwise no longer function. */
1020	if((BVDC_P_STATE_IS_ACTIVE(hCompositor->hVdc->ahSource[i])) &&
1021	(hCompositor->hVdc->ahSource[i]->hTrigger0Cb) &&
1022	(hCompositor->hVdc->ahSource[i]->hTrigger1Cb))
1023	{
1024	BVDC_Source_Handle hSource = hCompositor->hVdc->ahSource[i];
1025	BDBG_OBJECT_ASSERT(hSource, BVDC_SRC);
1026	/* does the source still have control? */
1027	if((BVDC_P_TriggerCtrl_eSource == hSource->eTrigCtrl) &&
1028	(hSource->ulVecTrigger))
1029	{
1030	hSource->ulVecTrigger--;
1031	if(!hSource->ulVecTrigger)
1032	{
1033	uint32_t i;
1034	/* Remove the triggers from the slots, because VEC is
1035	* going generate artificial triggers. */
1036	for(i = 0; i < hSource->ulSlotUsed; i++)
1037	{
1038	BRDC_Slot_ExecuteOnTrigger_isr(hSource->ahSlot[i],
1039	BRDC_Trigger_UNKNOWN, true);
1040	}
1041
1042	/* start the faked field trigger from display; */
1043	hSource->eNextFieldFake = hSource->eNextFieldIntP;
1044
1045	/* Make sure the slot are clean, especially if the last
1046	* RUL is the one that cause the source to lose triggers. */
1047	BVDC_P_Source_CleanupSlots_isr(hSource);
1048
1049	/* Turn trigger _isr callback to detect when trigger
1050	* cames back. */
1051	hSource->eTrigCtrl = BVDC_P_TriggerCtrl_eDisplay;
1052	hSource->ulVecTrigger = BVDC_P_TRIGGER_LOST_THRESHOLD;
1053	BINT_ClearCallback_isr(hSource->hTrigger0Cb);
1054	BINT_ClearCallback_isr(hSource->hTrigger1Cb);
1055	BINT_EnableCallback_isr(hSource->hTrigger0Cb);
1056	BINT_EnableCallback_isr(hSource->hTrigger1Cb);
1057	BDBG_WRN(("(D) Display[%d] acquires control of source[%d]'s slots",
1058	hCompositor->hDisplay->eId, hSource->eId));
1059	}
1060	}
1061	else if(BVDC_P_TriggerCtrl_eXfering == hSource->eTrigCtrl)
1062	{
1063	hSource->eTrigCtrl = BVDC_P_TriggerCtrl_eSource;
1064	}
1065	else if(BVDC_P_TriggerCtrl_eDisplay == hSource->eTrigCtrl)
1066	{
1067	/* Force trigger the current source's format fieldid. */
1068	BVDC_P_BUILD_IMM_EXEC_OPS(stList.pulCurrent,
1069	hSource->aulImmTriggerAddr[hSource->eNextFieldFake]);
1070	/* advance the faked field trigger from display; */
1071	hSource->eNextFieldFake = BVDC_P_NEXT_POLARITY(hSource->eNextFieldFake);
1072	}
1073	}
1074	}
1075	}
1076
1077	/* Updated lists count */
1078	BVDC_P_WriteListInfo_isr(&stList, hList);
1079
1080	if(BAVC_Polarity_eFrame != eNextFieldId)
1081	{
1082	BRDC_Slot_Handle hOtherSlot = BVDC_P_CMP_GET_SLOT(hCompositor,
1083	BVDC_P_NEXT_POLARITY(eNextFieldId));
1084	/* Note: to flush the cached RUL only once, call the Dual function
1085	instead of two individual slot functions; */
1086	BRDC_Slot_SetCachedListDual_isr(hSlot, hOtherSlot, hList);
1087	}
1088	else
1089	{
1090	BRDC_Slot_SetCachedList_isr(hSlot, hList);
1091	}
1092
1093	#if BVDC_P_SUPPORT_STG
1094	/* NRT STG host arm if this display isr builds the STG RUL. */
1095	/* only host arm for sync-slipped display, or the first time when slip transitioned to lock;
1096	the reason not to host arm the 2nd time during transition is to avoid NRT trigger firing early
1097	such that when source isr replaces sync-locked display slots with dummy RUL and before
1098	the source slot is installed with any meaningful RUL the NRT trigger might fire dummy nop
1099	RUL at both display and source slots which might stop the NRT trigger forever! */
1100	if(BVDC_P_DISPLAY_USED_STG(hCompositor->hDisplay->eMasterTg) &&
1101	hCompositor->hDisplay->stCurInfo.bStgNonRealTime &&
1102	(!hCompositor->hSyncLockSrc \|\| (hCompositor->ulSlip2Lock==1)))
1103	{
1104	if(hCompositor->ulSlip2Lock==1) hCompositor->ulSlip2Lock++;
1105	BREG_Write32(hCompositor->hDisplay->hVdc->hRegister,
1106	BCHP_VIDEO_ENC_STG_0_HOST_ARM + hCompositor->hDisplay->ulStgRegOffset, 1);
1107	}
1108	#endif
1109
1110	BVDC_P_CompositorDisplay_isr_Done:
1111	hCompositor->hVdc->ulInsideCs--;
1112	BDBG_LEAVE(BVDC_P_CompositorDisplay_isr);
1113	return;
1114	}
1115
1116	/***************************************************************************
1117	* This function convert from percentage clip rect (left, right, top, bottom)
1118	* and width and height to the actual rect
1119	* offset_x = width * left
1120	* offset_y = height * top
1121	* size_x = width - (width * left + width * right)
1122	* size_y = height - (height * top + height * bottom)
1123	*/
1124	void BVDC_P_CalculateRect_isr
1125	( const BVDC_ClipRect *pClipRect,
1126	uint32_t ulWidth,
1127	uint32_t ulHeight,
1128	bool bInterlaced,
1129	BVDC_P_Rect *pRect )
1130	{
1131	pRect->lLeft = ulWidth * pClipRect->ulLeft / BVDC_P_CLIPRECT_PERCENT;
1132	pRect->lTop = (ulHeight >> bInterlaced) * pClipRect->ulTop / BVDC_P_CLIPRECT_PERCENT;
1133	pRect->ulWidth = ulWidth -(pRect->lLeft +
1134	ulWidth * pClipRect->ulRight / BVDC_P_CLIPRECT_PERCENT);
1135	pRect->ulHeight = (ulHeight >> bInterlaced) -
1136	(pRect->lTop + (ulHeight >> bInterlaced) * pClipRect->ulBottom / BVDC_P_CLIPRECT_PERCENT);
1137	}
1138
1139	/***************************************************************************
1140	* This function checks if a callback's dirty bits are dirty.
1141	*/
1142	bool BVDC_P_CbIsDirty
1143	(void *pDirty,
1144	uint32_t ulSize )
1145	{
1146	static const uint8_t aulZero[BVDC_P_DIRTY_INT_ARRAY_SIZE * sizeof(uint32_t)]={0};
1147	BDBG_ASSERT(ulSize <= sizeof(aulZero));
1148	return (BKNI_Memcmp(pDirty, aulZero, ulSize)? true : false);
1149	}
1150
1151	/***************************************************************************
1152	*
1153	* Utility function called by BVDC_P_Window_AspectRatioCorrection_isr and
1154	* BVDC_P_Window_CalcuUserDisplaySize_isr, and BVDC_P_Display_CalPixelAspectRatio_isr
1155	* to calculate the U4.16 fixed point format aspect ratio of a PIXEL
1156	*
1157	* note: pixel asp ratio range is well bounded ( <16, i.e. 4 int bits ), so
1158	* calcu it first, and also it could have more frac bits than the asp ratio
1159	* of a sub-rect (that is not well bounded).
1160	*/
1161	void BVDC_P_CalcuPixelAspectRatio_isr(
1162	BFMT_AspectRatio eFullAspectRatio, /* full asp ratio enum */
1163	uint32_t ulSampleAspectRatioX, /* width of one sampled src pixel */
1164	uint32_t ulSampleAspectRatioY, /* height of one sampled src pixel */
1165	uint32_t ulFullWidth, /* full asp ratio width */
1166	uint32_t ulFullHeight, /* full asp ratio height */
1167	const BVDC_P_ClipRect * pAspRatCnvsClip, /* asp rat cnvs clip */
1168	uintAR_t * pulPxlAspRatio, /* PxlAspR_int.PxlAspR_frac */
1169	uint32_t * pulPxlAspRatio_x_y /* PxlAspR_x<<16 \| PxlAspR_y */
1170	)
1171	{
1172	uint32_t ulAspRatCnvsWidth, ulAspRatCnvsHeight;
1173	uintAR_t ulPixAspRatio = 0;
1174	uint16_t uiPixAspR_x=0, uiPixAspR_y=0;
1175	#if BVDC_P_SUPPORT_STG
1176	uint32_t b=0, a=0, m=0, i=0;
1177	#endif
1178	BDBG_ASSERT((NULL != pulPxlAspRatio) && (NULL != pulPxlAspRatio_x_y));
1179	BDBG_ASSERT(NULL != pAspRatCnvsClip);
1180
1181	ulAspRatCnvsWidth = ulFullWidth - (pAspRatCnvsClip->ulLeft + pAspRatCnvsClip->ulRight);
1182	ulAspRatCnvsHeight = ulFullHeight - (pAspRatCnvsClip->ulTop + pAspRatCnvsClip->ulBottom);
1183
1184	/* Set default value for unknown aspect ratio. */
1185	if(BVDC_P_IS_UNKNOWN_ASPR(eFullAspectRatio, ulSampleAspectRatioX, ulSampleAspectRatioY))
1186	{
1187	uint32_t ulHVRatio = (ulFullWidth * 100) / ulFullHeight;
1188	eFullAspectRatio = BVDC_P_EQ_DELTA(ulHVRatio, 130, 25)
1189	? BFMT_AspectRatio_e4_3 : BFMT_AspectRatio_eSquarePxl;
1190	}
1191
1192	/* Pay attention to overflow, assuming ulAspRatCnvsHeight could be as big as 1080 */
1193	switch (eFullAspectRatio)
1194	{
1195	case BFMT_AspectRatio_eSquarePxl:
1196	BDBG_MSG(("BFMT_AspectRatio_eSquarePxl"));
1197	uiPixAspR_x = 1;
1198	uiPixAspR_y = 1;
1199	break;
1200	case BFMT_AspectRatio_e4_3:
1201	BDBG_MSG(("BFMT_AspectRatio_e4_3"));
1202	uiPixAspR_x = ulAspRatCnvsHeight * 4;
1203	uiPixAspR_y = ulAspRatCnvsWidth * 3;
1204	break;
1205	case BFMT_AspectRatio_e16_9:
1206	BDBG_MSG(("BFMT_AspectRatio_e16_9"));
1207	uiPixAspR_x = ulAspRatCnvsHeight * 16;
1208	uiPixAspR_y = ulAspRatCnvsWidth * 9;
1209	break;
1210	case BFMT_AspectRatio_e221_1:
1211	BDBG_MSG(("BFMT_AspectRatio_e221_1"));
1212	uiPixAspR_x = (ulAspRatCnvsHeight * 221) >> 3;
1213	uiPixAspR_y = (ulAspRatCnvsWidth * 100) >> 3;
1214	ulPixAspRatio = ((((uintAR_t)ulAspRatCnvsHeight << BVDC_P_ASPR_FRAC_BITS_NUM) * 2) / (ulAspRatCnvsWidth) +
1215	(((uintAR_t)ulAspRatCnvsHeight << BVDC_P_ASPR_FRAC_BITS_NUM) * 21) / (100 * ulAspRatCnvsWidth));
1216	break;
1217	case BFMT_AspectRatio_e15_9:
1218	BDBG_MSG(("BFMT_AspectRatio_e15_9"));
1219	uiPixAspR_x = ulAspRatCnvsHeight * 15;
1220	uiPixAspR_y = ulAspRatCnvsWidth * 9;
1221	break;
1222	case BFMT_AspectRatio_eSAR:
1223	BDBG_MSG(("BFMT_AspectRatio_eSAR: %d, %d", ulSampleAspectRatioX, ulSampleAspectRatioY));
1224	uiPixAspR_x = ulSampleAspectRatioX;
1225	uiPixAspR_y = ulSampleAspectRatioY;
1226	break;
1227	default:
1228	uiPixAspR_x = 1;
1229	uiPixAspR_y = 1;
1230	BDBG_ERR(("Bad asp ratio enum %d", eFullAspectRatio));
1231	break;
1232	}
1233
1234	if(uiPixAspR_y == uiPixAspR_x)
1235	{
1236	uiPixAspR_y = uiPixAspR_x = 1;
1237	}
1238	#if BVDC_P_SUPPORT_STG
1239	/* Euclidean gcd algorithm */
1240	else
1241	{
1242	a = uiPixAspR_y > uiPixAspR_x ? uiPixAspR_y:uiPixAspR_x;
1243	b = uiPixAspR_y > uiPixAspR_x ? uiPixAspR_x:uiPixAspR_y;
1244
1245	while (b && (i<10)) { m = a % b; a = b; b = m; i++;}
1246
1247	if (i<10) {
1248	uiPixAspR_y/=a;
1249	uiPixAspR_x/=a;
1250	}
1251	}
1252	#endif
1253
1254	if (BFMT_AspectRatio_e221_1 != eFullAspectRatio)
1255	{
1256	ulPixAspRatio = ((uintAR_t)uiPixAspR_x << BVDC_P_ASPR_FRAC_BITS_NUM) / (uiPixAspR_y);
1257	}
1258
1259	*pulPxlAspRatio = ulPixAspRatio;
1260	*pulPxlAspRatio_x_y = ((uint32_t)uiPixAspR_x <<16) \| uiPixAspR_y;
1261
1262	BDBG_MSG(("pxlAspR: %8x %8x", pulPxlAspRatio, pulPxlAspRatio_x_y));
1263	}
1264
1265	/***************************************************************************
1266	*
1267	* Utility function called by BVDC_Source_GetCapabilities
1268	*/
1269	bool BVDC_P_IsPxlfmtSupported
1270	(BPXL_Format ePxlFmt)
1271	{
1272
1273	if(!BPXL_IS_YCbCr422_FORMAT(ePxlFmt)
1274	#if (BVDC_P_SUPPORT_BVN_10BIT_444)
1275	&& !BPXL_IS_YCbCr422_10BIT_FORMAT(ePxlFmt)
1276	&& !BPXL_IS_YCbCr444_10BIT_FORMAT(ePxlFmt)
1277	#endif
1278	)
1279	{
1280	return false;
1281	}
1282
1283	#if (BVDC_P_MFD_SUPPORT_BYTE_ORDER)
1284	/* Can support all formats with MFD_SUPPORT_BYTE_ORDER */
1285	return true;
1286
1287	#else
1288	/* Old chips: only limited formats are supported */
1289	#if (BSTD_CPU_ENDIAN == BSTD_ENDIAN_LITTLE)
1290	if ((ePxlFmt == BPXL_eY08_Cr8_Y18_Cb8) \|\|
1291	(ePxlFmt == BPXL_eCr8_Y08_Cb8_Y18) \|\|
1292	(ePxlFmt == BPXL_eY08_Cb8_Y18_Cr8) \|\|
1293	(ePxlFmt == BPXL_eCb8_Y08_Cr8_Y18))
1294	#else
1295	if ((ePxlFmt == BPXL_eCb8_Y18_Cr8_Y08) \|\|
1296	(ePxlFmt == BPXL_eY18_Cb8_Y08_Cr8) \|\|
1297	(ePxlFmt == BPXL_eCr8_Y18_Cb8_Y08) \|\|
1298	(ePxlFmt == BPXL_eY18_Cr8_Y08_Cb8))
1299	#endif
1300	{
1301	return false;
1302	}
1303	else
1304	{
1305	return true;
1306	}
1307	#endif
1308	}
1309
1310	/* End of file. */

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vdc/7552/bvdc_priv.c

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