| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2003-2009, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: bcmtm.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/1 $ |
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| 12 | * $brcm_Date: 9/30/09 5:19p $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /rockford/bsp/bcm97550/common/bcmtm.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/1 9/30/09 5:19p farshidf |
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| 21 | * SW7550-38: mini non-os code |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/1 3/24/05 4:40p dlwin |
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| 24 | * PR 14606: Merge to main development branch. |
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| 25 | * |
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| 26 | * Hydra_Software_Devel/6 5/27/04 5:13p brianlee |
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| 27 | * PR11238: Enable LED/KPD pins for 7038 B0. |
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| 28 | * |
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| 29 | * Hydra_Software_Devel/5 5/25/04 6:39p brianlee |
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| 30 | * PR11214: Merge from B0 branch. |
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| 31 | * |
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| 32 | * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:06p brianlee |
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| 33 | * PR10857: Version for 7038 B0. |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:03p brianlee |
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| 36 | * PR10857: Version for 7038 B0. |
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| 37 | * |
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| 38 | * Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:02p brianlee |
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| 39 | * PR10857: Version for 7038 B0. |
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| 40 | * |
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| 41 | * Hydra_Software_Devel/4 2/18/04 11:21a brianlee |
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| 42 | * PR9791: Enable IR2 instead of PWM1. |
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| 43 | * |
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| 44 | * Hydra_Software_Devel/3 1/15/04 11:12a brianlee |
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| 45 | * PR8921: Enable PKT3 input pins. |
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| 46 | * |
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| 47 | * Hydra_Software_Devel/2 10/31/03 10:29a brianlee |
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| 48 | * Enable all external interrupt inputs. |
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| 49 | * |
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| 50 | * Hydra_Software_Devel/1 10/8/03 4:38p brianlee |
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| 51 | * Initial version. |
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| 52 | * |
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| 53 | * |
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| 54 | ***************************************************************************/ |
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| 55 | |
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| 56 | #ifndef BCMTM_H |
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| 57 | #define BCMTM_H |
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| 58 | |
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| 59 | #ifdef __cplusplus |
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| 60 | extern "C" { |
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| 61 | #endif |
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| 62 | |
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| 63 | /**************************************************************************** |
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| 64 | * BSC |
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| 65 | ***************************************************************************/ |
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| 66 | #define BSC0_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_03_SHIFT) |
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| 67 | #define BSC0_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_02_SHIFT) |
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| 68 | #define BSC1_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_05_SHIFT) |
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| 69 | #define BSC1_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_04_SHIFT) |
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| 70 | #define BSC2_SDA (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_07_SHIFT) |
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| 71 | #define BSC2_SCL (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_06_SHIFT) |
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| 72 | #define BSC3_SDA (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_01_SHIFT) |
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| 73 | #define BSC3_SCL (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_00_SHIFT) |
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| 74 | |
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| 75 | #define BSC0_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_03_MASK |
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| 76 | #define BSC0_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_02_MASK |
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| 77 | #define BSC1_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_05_MASK |
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| 78 | #define BSC1_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_04_MASK |
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| 79 | #define BSC2_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_07_MASK |
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| 80 | #define BSC2_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_06_MASK |
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| 81 | #define BSC3_SDA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_01_MASK |
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| 82 | #define BSC3_SCL_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_sgpio_00_MASK |
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| 83 | |
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| 84 | /**************************************************************************** |
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| 85 | * SPI |
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| 86 | ***************************************************************************/ |
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| 87 | #define SPI_SS1 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_SHIFT) |
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| 88 | #define SPI_SS0 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_39_SHIFT) |
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| 89 | #define SPI_MISO (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_38_SHIFT) |
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| 90 | #define SPI_MOSI (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_SHIFT) |
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| 91 | #define SPI_CLK (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_SHIFT) |
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| 92 | |
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| 93 | #define SPI_SS1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_MASK |
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| 94 | #define SPI_SS0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_39_MASK |
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| 95 | #define SPI_MISO_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_38_MASK |
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| 96 | #define SPI_MOSI_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_MASK |
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| 97 | #define SPI_CLK_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_MASK |
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| 98 | |
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| 99 | /**************************************************************************** |
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| 100 | * UART |
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| 101 | ***************************************************************************/ |
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| 102 | #define UARTB_TX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_SHIFT) |
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| 103 | #define UARTB_RX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_SHIFT) |
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| 104 | #define UARTA_TX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_SHIFT) |
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| 105 | #define UARTA_RX (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_32_SHIFT) |
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| 106 | |
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| 107 | #define UARTB_TX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_MASK |
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| 108 | #define UARTB_RX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_MASK |
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| 109 | #define UARTA_TX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_MASK |
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| 110 | #define UARTA_RX_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_32_MASK |
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| 111 | |
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| 112 | /**************************************************************************** |
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| 113 | * PWM |
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| 114 | ***************************************************************************/ |
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| 115 | #define PWM_1 (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SHIFT) |
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| 116 | #define PWM_0 (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_05_SHIFT) |
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| 117 | |
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| 118 | #define PWM_1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_MASK |
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| 119 | #define PWM_0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_05_MASK |
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| 120 | |
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| 121 | /**************************************************************************** |
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| 122 | * IR |
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| 123 | ***************************************************************************/ |
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| 124 | #define IR2_IN (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SHIFT) |
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| 125 | #define IR3_IN (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_SHIFT) |
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| 126 | |
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| 127 | #define IR2_IN_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_MASK |
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| 128 | #define IR3_IN_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_MASK |
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| 129 | |
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| 130 | /**************************************************************************** |
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| 131 | * PKT3 |
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| 132 | ***************************************************************************/ |
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| 133 | #define PKT3_CLK (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_SHIFT) |
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| 134 | #define PKT3_DATA (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_SHIFT) |
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| 135 | #define PKT3_SYNC (1 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_SHIFT) |
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| 136 | |
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| 137 | #define PKT3_CLK_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_MASK |
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| 138 | #define PKT3_DATA_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_MASK |
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| 139 | #define PKT3_SYNC_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_MASK |
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| 140 | |
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| 141 | /**************************************************************************** |
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| 142 | * LED/Keypad |
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| 143 | ***************************************************************************/ |
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| 144 | #define LDK_LS_3 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_SHIFT) |
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| 145 | #define LDK_LS_2 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_SHIFT) |
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| 146 | #define LDK_LS_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_SHIFT) |
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| 147 | #define LDK_LS_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_SHIFT) |
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| 148 | |
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| 149 | #define LDK_LD_7 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_SHIFT) |
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| 150 | #define LDK_LD_6 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_SHIFT) |
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| 151 | #define LDK_LD_5 (3 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_SHIFT) |
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| 152 | |
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| 153 | #define LDK_KD_2 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_55_SHIFT) |
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| 154 | #define LDK_KD_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_54_SHIFT) |
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| 155 | #define LDK_KD_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_53_SHIFT) |
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| 156 | #define LDK_LS_4 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_SHIFT) |
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| 157 | #define LDK_LD_4 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_SHIFT) |
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| 158 | #define LDK_LD_3 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_SHIFT) |
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| 159 | #define LDK_LD_2 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_48_SHIFT) |
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| 160 | #define LDK_LD_1 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_47_SHIFT) |
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| 161 | #define LDK_LD_0 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_46_SHIFT) |
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| 162 | |
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| 163 | #define LDK_KD_3 (2 << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_56_SHIFT) |
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| 164 | |
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| 165 | #define LDK_MUX_7_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_MASK | \ |
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| 166 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_MASK | \ |
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| 167 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_MASK | \ |
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| 168 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_MASK ) |
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| 169 | #define LDK_MUX_8_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_MASK | \ |
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| 170 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_MASK | \ |
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| 171 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_MASK ) |
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| 172 | #define LDK_MUX_9_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_55_MASK | \ |
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| 173 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_54_MASK | \ |
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| 174 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_53_MASK | \ |
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| 175 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_MASK | \ |
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| 176 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_MASK | \ |
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| 177 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_MASK | \ |
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| 178 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_48_MASK | \ |
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| 179 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_47_MASK | \ |
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| 180 | BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_46_MASK ) |
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| 181 | #define LDK_MUX_10_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_56_MASK) |
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| 182 | |
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| 183 | |
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| 184 | /**************************************************************************** |
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| 185 | * MISC. |
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| 186 | ***************************************************************************/ |
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| 187 | #define EXT_LONG_RST (2L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_SHIFT) |
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| 188 | #define EXT_LONG_RST_MASK (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_40_MASK |
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| 189 | |
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| 190 | #define EXT_IRQB_0 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_SHIFT) |
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| 191 | #define EXT_IRQB_1 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_SHIFT) |
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| 192 | #define EXT_IRQB_2 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_SHIFT) |
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| 193 | #define EXT_IRQB_3 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_SHIFT) |
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| 194 | #define EXT_IRQB_4 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_SHIFT) |
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| 195 | #define EXT_IRQB_5 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_SHIFT) |
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| 196 | #define EXT_IRQB_6 (1L << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_SHIFT) |
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| 197 | |
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| 198 | #define EXT_IRQB_0_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_MASK |
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| 199 | #define EXT_IRQB_1_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_MASK |
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| 200 | #define EXT_IRQB_2_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_MASK |
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| 201 | #define EXT_IRQB_3_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_MASK |
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| 202 | #define EXT_IRQB_4_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_MASK |
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| 203 | #define EXT_IRQB_5_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_30_MASK |
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| 204 | #define EXT_IRQB_6_MASK BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_31_MASK |
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| 205 | |
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| 206 | /**************************************************************************** |
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| 207 | * Function prototypes |
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| 208 | ****************************************************************************/ |
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| 209 | void bcmConfigureTm (BREG_Handle hReg7038); |
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| 210 | |
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| 211 | #ifdef __cplusplus |
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| 212 | } |
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| 213 | #endif |
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| 214 | |
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| 215 | #endif |
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| 216 | |
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