| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Definitions for the address map in the JUNKIO Asic |
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| 7 | * |
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| 8 | * Created with Information from: |
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| 9 | * |
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| 10 | * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" |
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| 11 | * |
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| 12 | * and the Mach Sources |
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| 13 | * |
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| 14 | * Copyright (C) 199x the Anonymous |
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| 15 | * Copyright (C) 2002, 2003 Maciej W. Rozycki |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H |
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| 19 | #define __ASM_MIPS_DEC_IOASIC_ADDRS_H |
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| 20 | |
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| 21 | #define IOASIC_SLOT_SIZE 0x00040000 |
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| 22 | |
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| 23 | /* |
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| 24 | * Address ranges decoded by the I/O ASIC for onboard devices. |
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| 25 | */ |
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| 26 | #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */ |
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| 27 | #define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ |
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| 28 | #define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ |
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| 29 | #define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ |
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| 30 | #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ |
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| 31 | #define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ |
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| 32 | #define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ |
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| 33 | #define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ |
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| 34 | #define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ |
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| 35 | #define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ |
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| 36 | #define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */ |
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| 37 | #define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ |
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| 38 | #define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */ |
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| 39 | #define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ |
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| 40 | #define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ |
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| 41 | #define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ |
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| 42 | #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ |
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| 43 | #define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ |
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| 44 | #define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ |
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| 45 | |
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| 46 | |
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| 47 | /* |
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| 48 | * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). |
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| 49 | */ |
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| 50 | /* all systems */ |
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| 51 | #define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ |
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| 52 | #define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */ |
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| 53 | #define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */ |
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| 54 | #define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */ |
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| 55 | #define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */ |
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| 56 | |
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| 57 | /* except Maxine */ |
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| 58 | #define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */ |
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| 59 | #define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */ |
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| 60 | |
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| 61 | /* Maxine */ |
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| 62 | #define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */ |
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| 63 | #define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */ |
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| 64 | #define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */ |
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| 65 | #define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */ |
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| 66 | #define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */ |
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| 67 | #define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */ |
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| 68 | #define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */ |
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| 69 | |
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| 70 | /* all systems */ |
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| 71 | #define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */ |
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| 72 | #define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */ |
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| 73 | #define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */ |
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| 74 | #define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */ |
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| 75 | |
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| 76 | /* all systems */ |
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| 77 | #define IO_REG_SSR 0x100 /* System Support Register */ |
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| 78 | #define IO_REG_SIR 0x110 /* System Interrupt Register */ |
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| 79 | #define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */ |
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| 80 | #define IO_REG_SAR 0x130 /* System Address Register */ |
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| 81 | |
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| 82 | /* Maxine */ |
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| 83 | #define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */ |
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| 84 | #define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */ |
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| 85 | |
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| 86 | /* all systems */ |
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| 87 | #define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */ |
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| 88 | #define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */ |
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| 89 | #define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */ |
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| 90 | |
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| 91 | /* except Maxine */ |
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| 92 | #define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */ |
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| 93 | |
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| 94 | /* Maxine */ |
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| 95 | #define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */ |
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| 96 | #define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */ |
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| 97 | |
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| 98 | /* all systems */ |
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| 99 | #define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */ |
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| 100 | #define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */ |
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| 101 | #define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */ |
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| 102 | #define IO_REG_FCTR 0x1e0 /* Free-Running Counter */ |
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| 103 | #define IO_REG_RES_31 0x1f0 /* unused */ |
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| 104 | |
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| 105 | |
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| 106 | /* |
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| 107 | * The upper 16 bits of the System Support Register are a part of the |
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| 108 | * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC |
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| 109 | * machines. The exception is the Maxine, which makes use of the |
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| 110 | * FLOPPY and ISDN bits (otherwise unused) and has a different SCC |
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| 111 | * wiring. |
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| 112 | */ |
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| 113 | /* all systems */ |
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| 114 | #define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */ |
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| 115 | #define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */ |
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| 116 | #define IO_SSR_RES_27 (1<<27) /* unused */ |
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| 117 | #define IO_SSR_RES_26 (1<<26) /* unused */ |
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| 118 | #define IO_SSR_RES_25 (1<<25) /* unused */ |
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| 119 | #define IO_SSR_RES_24 (1<<24) /* unused */ |
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| 120 | #define IO_SSR_RES_23 (1<<23) /* unused */ |
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| 121 | #define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */ |
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| 122 | #define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */ |
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| 123 | #define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */ |
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| 124 | |
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| 125 | /* except Maxine */ |
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| 126 | #define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */ |
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| 127 | #define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */ |
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| 128 | #define IO_SSR_RES_22 (1<<22) /* unused */ |
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| 129 | #define IO_SSR_RES_21 (1<<21) /* unused */ |
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| 130 | #define IO_SSR_RES_20 (1<<20) /* unused */ |
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| 131 | #define IO_SSR_RES_19 (1<<19) /* unused */ |
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| 132 | |
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| 133 | /* Maxine */ |
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| 134 | #define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */ |
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| 135 | #define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */ |
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| 136 | #define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */ |
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| 137 | #define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */ |
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| 138 | #define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */ |
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| 139 | #define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */ |
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| 140 | |
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| 141 | /* |
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| 142 | * The lower 16 bits are system-specific. Bits 15,11:8 are common and |
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| 143 | * defined here. The rest is defined in system-specific headers. |
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| 144 | */ |
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| 145 | #define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */ |
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| 146 | #define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */ |
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| 147 | #define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */ |
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| 148 | #define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */ |
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| 149 | #define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */ |
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| 150 | |
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| 151 | #endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */ |
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