| [2] | 1 | /* |
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| 2 | * include/asm-mips/i8259.h |
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| 3 | * |
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| 4 | * i8259A interrupt definitions. |
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| 5 | * |
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| 6 | * Copyright (C) 2003 Maciej W. Rozycki |
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| 7 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or |
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| 10 | * modify it under the terms of the GNU General Public License |
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| 11 | * as published by the Free Software Foundation; either version |
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| 12 | * 2 of the License, or (at your option) any later version. |
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| 13 | */ |
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| 14 | #ifndef _ASM_I8259_H |
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| 15 | #define _ASM_I8259_H |
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| 16 | |
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| 17 | |
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| 18 | #include <asm/io.h> |
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| 19 | |
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| 20 | extern spinlock_t i8259A_lock; |
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| 21 | |
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| 22 | extern void init_i8259_irqs(void); |
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| 23 | |
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| 24 | /* |
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| 25 | * Do the traditional i8259 interrupt polling thing. This is for the few |
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| 26 | * cases where no better interrupt acknowledge method is available and we |
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| 27 | * absolutely must touch the i8259. |
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| 28 | */ |
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| 29 | static inline int i8259_irq(void) |
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| 30 | { |
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| 31 | int irq; |
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| 32 | |
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| 33 | spin_lock(&i8259A_lock); |
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| 34 | |
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| 35 | /* Perform an interrupt acknowledge cycle on controller 1. */ |
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| 36 | outb(0x0C, 0x20); /* prepare for poll */ |
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| 37 | irq = inb(0x20) & 7; |
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| 38 | if (irq == 2) { |
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| 39 | /* |
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| 40 | * Interrupt is cascaded so perform interrupt |
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| 41 | * acknowledge on controller 2. |
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| 42 | */ |
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| 43 | outb(0x0C, 0xA0); /* prepare for poll */ |
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| 44 | irq = (inb(0xA0) & 7) + 8; |
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| 45 | } |
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| 46 | |
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| 47 | if (unlikely(irq == 7)) { |
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| 48 | /* |
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| 49 | * This may be a spurious interrupt. |
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| 50 | * |
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| 51 | * Read the interrupt status register (ISR). If the most |
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| 52 | * significant bit is not set then there is no valid |
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| 53 | * interrupt. |
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| 54 | */ |
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| 55 | outb(0x0B, 0x20); /* ISR register */ |
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| 56 | if(~inb(0x20) & 0x80) |
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| 57 | irq = -1; |
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| 58 | } |
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| 59 | |
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| 60 | spin_unlock(&i8259A_lock); |
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| 61 | |
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| 62 | return irq; |
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| 63 | } |
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| 64 | |
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| 65 | #endif /* _ASM_I8259_H */ |
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