| 1 | /* |
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| 2 | * |
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| 3 | * BRIEF MODULE DESCRIPTION |
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| 4 | * ITE 8172 Interrupt Numbering |
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| 5 | * |
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| 6 | * Copyright 2000 MontaVista Software Inc. |
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| 7 | * Author: MontaVista Software, Inc. |
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| 8 | * ppopov@mvista.com or source@mvista.com |
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| 9 | * |
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| 10 | * This program is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by the |
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| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
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| 13 | * option) any later version. |
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| 14 | * |
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| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 25 | * |
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| 26 | * You should have received a copy of the GNU General Public License along |
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| 27 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 29 | */ |
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| 30 | |
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| 31 | #ifndef _MIPS_ITEINT_H |
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| 32 | #define _MIPS_ITEINT_H |
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| 33 | |
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| 34 | /* |
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| 35 | * Here's the "strategy": |
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| 36 | * We number the LPC serial irqs from 0 to 15, |
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| 37 | * the local bus irqs from 16 to 31, |
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| 38 | * the pci dev register interrupts from 32 to 47, |
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| 39 | * and the non-maskable ints from 48 to 53. |
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| 40 | */ |
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| 41 | |
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| 42 | #define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */ |
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| 43 | #define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0) |
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| 44 | #define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1) |
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| 45 | #define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2) |
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| 46 | #define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3) |
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| 47 | #define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4) |
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| 48 | #define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5) |
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| 49 | #define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6) |
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| 50 | #define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7) |
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| 51 | #define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8) |
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| 52 | #define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9) |
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| 53 | #define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10) |
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| 54 | #define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11) |
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| 55 | #define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12) |
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| 56 | #define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13) |
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| 57 | #define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14) |
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| 58 | #define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15) |
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| 59 | |
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| 60 | #define IT8172_LB_IRQ_BASE 16 /* first local bus int number */ |
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| 61 | #define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */ |
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| 62 | #define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1) |
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| 63 | #define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2) |
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| 64 | #define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3) |
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| 65 | #define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4) |
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| 66 | #define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5) |
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| 67 | #define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6) |
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| 68 | #define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7) |
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| 69 | #define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8) |
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| 70 | #define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9) |
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| 71 | #define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10) |
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| 72 | #define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11) |
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| 73 | /* 12 - 15 reserved */ |
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| 74 | |
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| 75 | /* |
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| 76 | * Note here that the pci dev registers includes bits for more than |
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| 77 | * just the pci devices. |
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| 78 | */ |
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| 79 | #define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */ |
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| 80 | #define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0) |
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| 81 | #define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1) |
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| 82 | #define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2) |
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| 83 | #define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3) |
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| 84 | #define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4) |
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| 85 | #define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5) |
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| 86 | #define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6) |
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| 87 | #define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7) |
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| 88 | #define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8) |
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| 89 | #define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9) |
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| 90 | #define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10) |
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| 91 | #define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11) |
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| 92 | #define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12) |
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| 93 | #define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13) |
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| 94 | #define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14) |
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| 95 | #define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15) |
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| 96 | |
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| 97 | #define IT8172_NMI_IRQ_BASE 48 |
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| 98 | #define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0) |
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| 99 | #define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1) |
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| 100 | #define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2) |
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| 101 | #define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3) |
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| 102 | #define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4) |
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| 103 | #define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5) |
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| 104 | |
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| 105 | #define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ) |
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| 106 | /* Finally, let's move over here the mips cpu timer interrupt. |
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| 107 | */ |
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| 108 | #define MIPS_CPU_TIMER_IRQ (NR_IRQS-1) |
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| 109 | |
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| 110 | /* |
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| 111 | * IT8172 Interrupt Controller Registers |
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| 112 | */ |
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| 113 | struct it8172_intc_regs { |
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| 114 | volatile unsigned short lb_req; /* offset 0 */ |
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| 115 | volatile unsigned short lb_mask; |
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| 116 | volatile unsigned short lb_trigger; |
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| 117 | volatile unsigned short lb_level; |
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| 118 | unsigned char pad0[8]; |
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| 119 | |
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| 120 | volatile unsigned short lpc_req; /* offset 0x10 */ |
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| 121 | volatile unsigned short lpc_mask; |
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| 122 | volatile unsigned short lpc_trigger; |
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| 123 | volatile unsigned short lpc_level; |
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| 124 | unsigned char pad1[8]; |
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| 125 | |
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| 126 | volatile unsigned short pci_req; /* offset 0x20 */ |
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| 127 | volatile unsigned short pci_mask; |
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| 128 | volatile unsigned short pci_trigger; |
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| 129 | volatile unsigned short pci_level; |
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| 130 | unsigned char pad2[8]; |
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| 131 | |
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| 132 | volatile unsigned short nmi_req; /* offset 0x30 */ |
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| 133 | volatile unsigned short nmi_mask; |
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| 134 | volatile unsigned short nmi_trigger; |
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| 135 | volatile unsigned short nmi_level; |
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| 136 | unsigned char pad3[6]; |
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| 137 | |
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| 138 | volatile unsigned short nmi_redir; /* offset 0x3E */ |
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| 139 | unsigned char pad4[0xBE]; |
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| 140 | |
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| 141 | volatile unsigned short intstatus; /* offset 0xFE */ |
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| 142 | }; |
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| 143 | |
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| 144 | #endif /* _MIPS_ITEINT_H */ |
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