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serial.h @ 2

Last change on this file since 2 was 2, checked in by jglee, 11 years ago
first commit
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File size: 16.7 KB

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1	/*
2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.
5	*
6	* Copyright (C) 1999 by Ralf Baechle
7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8	*/
9	#ifndef _ASM_SERIAL_H
10	#define _ASM_SERIAL_H
11
12
13	/*
14	* This assumes you have a 1.8432 MHz clock for your UART.
15	*
16	* It'd be nice if someone built a serial card with a 24.576 MHz
17	* clock, since the 16550A is capable of handling a top speed of 1.5
18	* megabits/second; but this requires the faster clock.
19	*/
20	#define BASE_BAUD (1843200 / 16)
21
22	/* Standard COM flags (except for COM4, because of the 8514 problem) */
23	#ifdef CONFIG_SERIAL_DETECT_IRQ
24	#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST \| ASYNC_AUTO_IRQ)
25	#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF \| ASYNC_AUTO_IRQ)
26	#else
27	#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST)
28	#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29	#endif
30
31	#ifdef CONFIG_SERIAL_MANY_PORTS
32	#define FOURPORT_FLAGS ASYNC_FOURPORT
33	#define ACCENT_FLAGS 0
34	#define BOCA_FLAGS 0
35	#define HUB6_FLAGS 0
36	#define RS_TABLE_SIZE 64
37	#else
38	#define RS_TABLE_SIZE
39	#endif
40
41	/*
42	* The following define the access methods for the HUB6 card. All
43	* access is through two ports for all 24 possible chips. The card is
44	* selected through the high 2 bits, the port on that card with the
45	* "middle" 3 bits, and the register on that port with the bottom
46	* 3 bits.
47	*
48	* While the access port and interrupt is configurable, the default
49	* port locations are 0x302 for the port control register, and 0x303
50	* for the data read/write register. Normally, the interrupt is at irq3
51	* but can be anything from 3 to 7 inclusive. Note that using 3 will
52	* require disabling com2.
53	*/
54
55	#define C_P(card,port) (((card)<<6\|(port)<<3) + 1)
56
57	#ifdef CONFIG_MACH_JAZZ
58	#include <asm/jazz.h>
59
60	#ifndef CONFIG_OLIVETTI_M700
61	/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
62	exactly which ones ... XXX */
63	#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
64	#else
65	/* but the M700 isn't such a strange beast */
66	#define JAZZ_BASE_BAUD BASE_BAUD
67	#endif
68
69	#define _JAZZ_SERIAL_INIT(int, base) \
70	{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
71	.iomem_base = (__u8 *) base, .iomem_reg_shift = 0, \
72	.io_type = SERIAL_IO_MEM }
73	#define JAZZ_SERIAL_PORT_DEFNS \
74	_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
75	_JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
76	#else
77	#define JAZZ_SERIAL_PORT_DEFNS
78	#endif
79
80	#ifdef CONFIG_MIPS_COBALT
81	#include <asm/cobalt/cobalt.h>
82	#define COBALT_BASE_BAUD (18432000 / 16)
83	#define COBALT_SERIAL_PORT_DEFNS \
84	/* UART CLK PORT IRQ FLAGS */ \
85	{ 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
86	#else
87	#define COBALT_SERIAL_PORT_DEFNS
88	#endif
89
90	/*
91	* Both Galileo boards have the same UART mappings.
92	*/
93	#if defined (CONFIG_MIPS_EV96100) \|\| defined (CONFIG_MIPS_EV64120)
94	#include <asm/galileo-boards/ev96100.h>
95	#include <asm/galileo-boards/ev96100int.h>
96	#define EV96100_SERIAL_PORT_DEFNS \
97	{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
98	.flags = STD_COM_FLAGS, \
99	.iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
100	.io_type = SERIAL_IO_MEM }, \
101	{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
102	.flags = STD_COM_FLAGS, \
103	.iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
104	.io_type = SERIAL_IO_MEM },
105	#else
106	#define EV96100_SERIAL_PORT_DEFNS
107	#endif
108
109	#ifdef CONFIG_MIPS_ITE8172
110	#include <asm/it8172/it8172.h>
111	#include <asm/it8172/it8172_int.h>
112	#include <asm/it8712.h>
113	#define ITE_SERIAL_PORT_DEFNS \
114	{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
115	.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
116	{ .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
117	.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
118	/* Smart Card Reader 0 */ \
119	{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
120	.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
121	/* Smart Card Reader 1 */ \
122	{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
123	.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
124	#else
125	#define ITE_SERIAL_PORT_DEFNS
126	#endif
127
128	#ifdef CONFIG_MIPS_IVR
129	#include <asm/it8172/it8172.h>
130	#include <asm/it8172/it8172_int.h>
131	#define IVR_SERIAL_PORT_DEFNS \
132	{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
133	.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
134	/* Smart Card Reader 1 */ \
135	{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
136	.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
137	#else
138	#define IVR_SERIAL_PORT_DEFNS
139	#endif
140
141	#ifdef CONFIG_TOSHIBA_JMR3927
142	#include <asm/jmr3927/jmr3927.h>
143	#define TXX927_SERIAL_PORT_DEFNS \
144	{ .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
145	.flags = UART0_FLAGS, .type = 1 }, \
146	{ .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
147	.flags = UART1_FLAGS, .type = 1 },
148	#else
149	#define TXX927_SERIAL_PORT_DEFNS
150	#endif
151
152	#ifdef CONFIG_SERIAL_AU1X00
153	#include <asm/mach-au1x00/au1000.h>
154	#ifdef CONFIG_SOC_AU1000
155	#define AU1000_SERIAL_PORT_DEFNS \
156	{ .baud_base = 0, .port = UART0_ADDR, \
157	.iomem_base = (unsigned char *)UART0_ADDR, \
158	.irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
159	.iomem_reg_shift = 2 }, \
160	{ .baud_base = 0, .port = UART1_ADDR, \
161	.iomem_base = (unsigned char *)UART1_ADDR, \
162	.irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
163	.iomem_reg_shift = 2 }, \
164	{ .baud_base = 0, .port = UART2_ADDR, \
165	.iomem_base = (unsigned char *)UART2_ADDR, \
166	.irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
167	.iomem_reg_shift = 2 }, \
168	{ .baud_base = 0, .port = UART3_ADDR, \
169	.iomem_base = (unsigned char *)UART3_ADDR, \
170	.irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
171	.iomem_reg_shift = 2 },
172	#endif
173
174	#ifdef CONFIG_SOC_AU1500
175	#define AU1000_SERIAL_PORT_DEFNS \
176	{ .baud_base = 0, .port = UART0_ADDR, \
177	.iomem_base = (unsigned char *)UART0_ADDR, \
178	.irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
179	.iomem_reg_shift = 2 }, \
180	{ .baud_base = 0, .port = UART3_ADDR, \
181	.iomem_base = (unsigned char *)UART3_ADDR, \
182	.irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
183	.iomem_reg_shift = 2 },
184	#endif
185
186	#ifdef CONFIG_SOC_AU1100
187	#define AU1000_SERIAL_PORT_DEFNS \
188	{ .baud_base = 0, .port = UART0_ADDR, \
189	.iomem_base = (unsigned char *)UART0_ADDR, \
190	.irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
191	.iomem_reg_shift = 2 }, \
192	{ .baud_base = 0, .port = UART1_ADDR, \
193	.iomem_base = (unsigned char *)UART1_ADDR, \
194	.irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
195	.iomem_reg_shift = 2 }, \
196	{ .baud_base = 0, .port = UART3_ADDR, \
197	.iomem_base = (unsigned char *)UART3_ADDR, \
198	.irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
199	.iomem_reg_shift = 2 },
200	#endif
201
202	#ifdef CONFIG_SOC_AU1550
203	#define AU1000_SERIAL_PORT_DEFNS \
204	{ .baud_base = 0, .port = UART0_ADDR, \
205	.iomem_base = (unsigned char *)UART0_ADDR, \
206	.irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
207	.iomem_reg_shift = 2 }, \
208	{ .baud_base = 0, .port = UART1_ADDR, \
209	.iomem_base = (unsigned char *)UART1_ADDR, \
210	.irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
211	.iomem_reg_shift = 2 }, \
212	{ .baud_base = 0, .port = UART3_ADDR, \
213	.iomem_base = (unsigned char *)UART3_ADDR, \
214	.irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
215	.iomem_reg_shift = 2 },
216	#endif
217
218	#ifdef CONFIG_SOC_AU1200
219	#define AU1000_SERIAL_PORT_DEFNS \
220	{ .baud_base = 0, .port = UART0_ADDR, \
221	.iomem_base = (unsigned char *)UART0_ADDR, \
222	.irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
223	.iomem_reg_shift = 2 }, \
224	{ .baud_base = 0, .port = UART1_ADDR, \
225	.iomem_base = (unsigned char *)UART1_ADDR, \
226	.irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
227	.iomem_reg_shift = 2 },
228	#endif
229
230	#else
231	#define AU1000_SERIAL_PORT_DEFNS
232	#endif
233
234	#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
235	#define STD_SERIAL_PORT_DEFNS \
236	/* UART CLK PORT IRQ FLAGS */ \
237	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
238	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
239	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
240	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
241
242	#ifdef CONFIG_SERIAL_MANY_PORTS
243	#define EXTRA_SERIAL_PORT_DEFNS \
244	{ 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
245	{ 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
246	{ 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
247	{ 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
248	{ 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
249	{ 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
250	{ 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
251	{ 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
252	{ 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
253	{ 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
254	{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
255	{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
256	{ 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
257	{ 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
258	{ 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
259	{ 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
260	{ 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
261	{ 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
262	{ 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
263	{ 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
264	{ 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
265	{ 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
266	{ 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
267	{ 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
268	{ 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
269	{ 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
270	{ 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
271	{ 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
272	#else /* CONFIG_SERIAL_MANY_PORTS */
273	#define EXTRA_SERIAL_PORT_DEFNS
274	#endif /* CONFIG_SERIAL_MANY_PORTS */
275
276	#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
277	#define STD_SERIAL_PORT_DEFNS
278	#define EXTRA_SERIAL_PORT_DEFNS
279	#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
280
281	/* You can have up to four HUB6's in the system, but I've only
282	* included two cards here for a total of twelve ports.
283	*/
284	#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
285	#define HUB6_SERIAL_PORT_DFNS \
286	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
287	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
288	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
289	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
290	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
291	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
292	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
293	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
294	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
295	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
296	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
297	{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
298	#else
299	#define HUB6_SERIAL_PORT_DFNS
300	#endif
301
302	#ifdef CONFIG_MOMENCO_JAGUAR_ATX
303	/* Ordinary NS16552 duart with a 20MHz crystal. */
304	#define JAGUAR_ATX_UART_CLK 20000000
305	#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
306
307	#define JAGUAR_ATX_SERIAL1_IRQ 6
308	#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
309
310	#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
311	{ baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
312	flags: (ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST), \
313	iomem_base: (__u8 *) base, iomem_reg_shift: 2, \
314	io_type: SERIAL_IO_MEM }
315	#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
316	_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
317	#else
318	#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
319	#endif
320
321	#ifdef CONFIG_MOMENCO_OCELOT_3
322	#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
323	#define OCELOT_3_SERIAL_IRQ 6
324	#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
325
326	#define _OCELOT_3_SERIAL_INIT(int, base) \
327	{ baud_base: OCELOT_3_BASE_BAUD, irq: int, \
328	flags: STD_COM_FLAGS, \
329	iomem_base: (__u8 *) base, iomem_reg_shift: 2, \
330	io_type: SERIAL_IO_MEM }
331
332	#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
333	_OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
334	#else
335	#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
336	#endif
337
338	#ifdef CONFIG_MOMENCO_OCELOT
339	/* Ordinary NS16552 duart with a 20MHz crystal. */
340	#define OCELOT_BASE_BAUD ( 20000000 / 16 )
341
342	#define OCELOT_SERIAL1_IRQ 4
343	#define OCELOT_SERIAL1_BASE 0xe0001020
344
345	#define _OCELOT_SERIAL_INIT(int, base) \
346	{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
347	.iomem_base = (__u8 *) base, .iomem_reg_shift = 2, \
348	.io_type = SERIAL_IO_MEM }
349	#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
350	_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
351	#else
352	#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
353	#endif
354
355	#ifdef CONFIG_MOMENCO_OCELOT_G
356	/* Ordinary NS16552 duart with a 20MHz crystal. */
357	#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
358
359	#define OCELOT_G_SERIAL1_IRQ 4
360	#if 0
361	#define OCELOT_G_SERIAL1_BASE 0xe0001020
362	#else
363	#define OCELOT_G_SERIAL1_BASE 0xfd000020
364	#endif
365
366	#define _OCELOT_G_SERIAL_INIT(int, base) \
367	{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
368	.iomem_base = (__u8 *) base, .iomem_reg_shift = 2, \
369	.io_type = SERIAL_IO_MEM }
370	#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
371	_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
372	#else
373	#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
374	#endif
375
376	#ifdef CONFIG_MOMENCO_OCELOT_C
377	/* Ordinary NS16552 duart with a 20MHz crystal. */
378	#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
379
380	#define OCELOT_C_SERIAL1_IRQ 80
381	#define OCELOT_C_SERIAL1_BASE 0xfd000020
382
383	#define OCELOT_C_SERIAL2_IRQ 81
384	#define OCELOT_C_SERIAL2_BASE 0xfd000000
385
386	#define _OCELOT_C_SERIAL_INIT(int, base) \
387	{ .baud_base = OCELOT_C_BASE_BAUD, \
388	.irq = (int), \
389	.flags = STD_COM_FLAGS, \
390	.iomem_base = (__u8 *) base, \
391	.iomem_reg_shift = 2, \
392	.io_type = SERIAL_IO_MEM \
393	}
394	#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
395	_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
396	_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
397	#else
398	#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
399	#endif
400
401	#ifdef CONFIG_DDB5477
402	#include <asm/ddb5xxx/ddb5477.h>
403	#define DDB5477_SERIAL_PORT_DEFNS \
404	{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
405	.flags = STD_COM_FLAGS, .iomem_base = (__u8*)0xbfa04200, \
406	.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
407	{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
408	.flags = STD_COM_FLAGS, .iomem_base = (__u8*)0xbfa04240, \
409	.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
410	#else
411	#define DDB5477_SERIAL_PORT_DEFNS
412	#endif
413
414	#ifdef CONFIG_SGI_IP32
415	/*
416	* The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
417	* They are initialized in ip32_setup
418	*/
419	#define IP32_SERIAL_PORT_DEFNS \
420	{},{},
421	#else
422	#define IP32_SERIAL_PORT_DEFNS
423	#endif /* CONFIG_SGI_IP32 */
424
425	#define SERIAL_PORT_DFNS \
426	COBALT_SERIAL_PORT_DEFNS \
427	DDB5477_SERIAL_PORT_DEFNS \
428	EV96100_SERIAL_PORT_DEFNS \
429	EXTRA_SERIAL_PORT_DEFNS \
430	HUB6_SERIAL_PORT_DFNS \
431	IP32_SERIAL_PORT_DEFNS \
432	ITE_SERIAL_PORT_DEFNS \
433	IVR_SERIAL_PORT_DEFNS \
434	JAZZ_SERIAL_PORT_DEFNS \
435	STD_SERIAL_PORT_DEFNS \
436	MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
437	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
438	MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
439	MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
440	TXX927_SERIAL_PORT_DEFNS \
441	AU1000_SERIAL_PORT_DEFNS
442
443	#endif /* _ASM_SERIAL_H */

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source: svn/trunk/newcon3bcm2_21bu/toolchain/mips-linux-uclibc/include/asm/serial.h @ 2

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