| 1 | /* ********************************************************************* |
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| 2 | * SB1250 Board Support Package |
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| 3 | * |
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| 4 | * Generic Bus Constants File: sb1250_genbus.h |
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| 5 | * |
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| 6 | * This module contains constants and macros useful for |
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| 7 | * manipulating the SB1250's Generic Bus interface |
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| 8 | * |
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| 9 | * SB1250 specification level: User's manual 1/02/02 |
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| 10 | * |
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| 11 | * Author: Mitch Lichtenberg |
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| 12 | * |
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| 13 | ********************************************************************* |
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| 14 | * |
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| 15 | * Copyright 2000,2001,2002,2003 |
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| 16 | * Broadcom Corporation. All rights reserved. |
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| 17 | * |
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| 18 | * This program is free software; you can redistribute it and/or |
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| 19 | * modify it under the terms of the GNU General Public License as |
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| 20 | * published by the Free Software Foundation; either version 2 of |
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| 21 | * the License, or (at your option) any later version. |
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| 22 | * |
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| 23 | * This program is distributed in the hope that it will be useful, |
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| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 26 | * GNU General Public License for more details. |
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| 27 | * |
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| 28 | * You should have received a copy of the GNU General Public License |
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| 29 | * along with this program; if not, write to the Free Software |
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| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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| 31 | * MA 02111-1307 USA |
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| 32 | ********************************************************************* */ |
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| 33 | |
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| 34 | |
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| 35 | #ifndef _SB1250_GENBUS_H |
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| 36 | #define _SB1250_GENBUS_H |
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| 37 | |
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| 38 | #include "sb1250_defs.h" |
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| 39 | |
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| 40 | /* |
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| 41 | * Generic Bus Region Configuration Registers (Table 11-4) |
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| 42 | */ |
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| 43 | |
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| 44 | #define S_IO_RDY_ACTIVE 0 |
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| 45 | #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) |
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| 46 | |
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| 47 | #define S_IO_ENA_RDY 1 |
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| 48 | #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) |
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| 49 | |
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| 50 | #define S_IO_WIDTH_SEL 2 |
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| 51 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) |
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| 52 | #define K_IO_WIDTH_SEL_1 0 |
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| 53 | #define K_IO_WIDTH_SEL_2 1 |
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| 54 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 55 | #define K_IO_WIDTH_SEL_1L 2 |
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| 56 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 57 | #define K_IO_WIDTH_SEL_4 3 |
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| 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) |
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| 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) |
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| 60 | |
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| 61 | #define S_IO_PARITY_ENA 4 |
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| 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) |
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| 63 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 64 | #define S_IO_BURST_EN 5 |
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| 65 | #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) |
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| 66 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 67 | #define S_IO_PARITY_ODD 6 |
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| 68 | #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) |
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| 69 | #define S_IO_NONMUX 7 |
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| 70 | #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) |
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| 71 | |
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| 72 | #define S_IO_TIMEOUT 8 |
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| 73 | #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) |
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| 74 | #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) |
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| 75 | #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) |
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| 76 | |
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| 77 | /* |
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| 78 | * Generic Bus Region Size register (Table 11-5) |
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| 79 | */ |
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| 80 | |
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| 81 | #define S_IO_MULT_SIZE 0 |
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| 82 | #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) |
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| 83 | #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) |
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| 84 | #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) |
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| 85 | |
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| 86 | #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ |
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| 87 | |
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| 88 | /* |
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| 89 | * Generic Bus Region Address (Table 11-6) |
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| 90 | */ |
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| 91 | |
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| 92 | #define S_IO_START_ADDR 0 |
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| 93 | #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) |
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| 94 | #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) |
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| 95 | #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) |
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| 96 | |
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| 97 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ |
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| 98 | |
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| 99 | /* |
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| 100 | * Generic Bus Region 0 Timing Registers (Table 11-7) |
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| 101 | */ |
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| 102 | |
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| 103 | #define S_IO_ALE_WIDTH 0 |
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| 104 | #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) |
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| 105 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) |
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| 106 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) |
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| 107 | |
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| 108 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 109 | #define M_IO_EARLY_CS _SB_MAKEMASK1(3) |
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| 110 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 111 | |
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| 112 | #define S_IO_ALE_TO_CS 4 |
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| 113 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) |
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| 114 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) |
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| 115 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) |
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| 116 | |
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| 117 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 118 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) |
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| 119 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) |
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| 120 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) |
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| 121 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) |
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| 122 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 123 | |
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| 124 | #define S_IO_CS_WIDTH 8 |
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| 125 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) |
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| 126 | #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) |
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| 127 | #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) |
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| 128 | |
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| 129 | #define S_IO_RDY_SMPLE 13 |
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| 130 | #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) |
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| 131 | #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) |
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| 132 | #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) |
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| 133 | |
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| 134 | |
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| 135 | /* |
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| 136 | * Generic Bus Timing 1 Registers (Table 11-8) |
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| 137 | */ |
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| 138 | |
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| 139 | #define S_IO_ALE_TO_WRITE 0 |
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| 140 | #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) |
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| 141 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) |
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| 142 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) |
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| 143 | |
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| 144 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 145 | #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) |
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| 146 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 147 | |
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| 148 | #define S_IO_WRITE_WIDTH 4 |
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| 149 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) |
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| 150 | #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) |
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| 151 | #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) |
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| 152 | |
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| 153 | #define S_IO_IDLE_CYCLE 8 |
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| 154 | #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) |
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| 155 | #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) |
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| 156 | #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) |
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| 157 | |
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| 158 | #define S_IO_OE_TO_CS 12 |
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| 159 | #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) |
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| 160 | #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) |
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| 161 | #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) |
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| 162 | |
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| 163 | #define S_IO_CS_TO_OE 14 |
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| 164 | #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) |
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| 165 | #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) |
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| 166 | #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) |
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| 167 | |
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| 168 | /* |
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| 169 | * Generic Bus Interrupt Status Register (Table 11-9) |
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| 170 | */ |
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| 171 | |
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| 172 | #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) |
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| 173 | #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) |
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| 174 | #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) |
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| 175 | #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) |
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| 176 | #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) |
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| 177 | #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) |
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| 178 | #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) |
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| 179 | #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) |
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| 180 | #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) |
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| 181 | |
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| 182 | #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) |
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| 183 | #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) |
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| 184 | #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) |
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| 185 | #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) |
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| 186 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 187 | #define M_IO_COH_ERR _SB_MAKEMASK1(14) |
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| 188 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 189 | |
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| 190 | /* |
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| 191 | * PCMCIA configuration register (Table 12-6) |
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| 192 | */ |
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| 193 | |
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| 194 | #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) |
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| 195 | #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) |
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| 196 | #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) |
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| 197 | #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) |
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| 198 | #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) |
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| 199 | #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) |
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| 200 | #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) |
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| 201 | #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) |
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| 202 | #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) |
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| 203 | #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) |
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| 204 | |
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| 205 | /* |
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| 206 | * PCMCIA status register (Table 12-7) |
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| 207 | */ |
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| 208 | |
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| 209 | #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) |
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| 210 | #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) |
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| 211 | #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) |
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| 212 | #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) |
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| 213 | #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) |
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| 214 | #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) |
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| 215 | #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) |
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| 216 | #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) |
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| 217 | #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) |
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| 218 | #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) |
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| 219 | #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) |
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| 220 | |
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| 221 | /* |
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| 222 | * GPIO Interrupt Type Register (table 13-3) |
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| 223 | */ |
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| 224 | |
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| 225 | #define K_GPIO_INTR_DISABLE 0 |
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| 226 | #define K_GPIO_INTR_EDGE 1 |
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| 227 | #define K_GPIO_INTR_LEVEL 2 |
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| 228 | #define K_GPIO_INTR_SPLIT 3 |
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| 229 | |
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| 230 | #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) |
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| 231 | #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) |
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| 232 | #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) |
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| 233 | #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) |
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| 234 | |
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| 235 | #define S_GPIO_INTR_TYPE0 0 |
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| 236 | #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) |
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| 237 | #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) |
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| 238 | #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) |
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| 239 | |
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| 240 | #define S_GPIO_INTR_TYPE2 2 |
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| 241 | #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) |
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| 242 | #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) |
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| 243 | #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) |
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| 244 | |
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| 245 | #define S_GPIO_INTR_TYPE4 4 |
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| 246 | #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) |
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| 247 | #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) |
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| 248 | #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) |
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| 249 | |
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| 250 | #define S_GPIO_INTR_TYPE6 6 |
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| 251 | #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) |
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| 252 | #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) |
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| 253 | #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) |
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| 254 | |
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| 255 | #define S_GPIO_INTR_TYPE8 8 |
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| 256 | #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) |
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| 257 | #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) |
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| 258 | #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) |
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| 259 | |
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| 260 | #define S_GPIO_INTR_TYPE10 10 |
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| 261 | #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) |
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| 262 | #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) |
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| 263 | #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) |
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| 264 | |
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| 265 | #define S_GPIO_INTR_TYPE12 12 |
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| 266 | #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) |
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| 267 | #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) |
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| 268 | #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) |
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| 269 | |
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| 270 | #define S_GPIO_INTR_TYPE14 14 |
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| 271 | #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) |
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| 272 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) |
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| 273 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) |
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| 274 | |
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| 275 | |
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| 276 | #endif |
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