| 1 | /* |
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| 2 | * Copyright (C) 1999, 2000 Ralf Baechle |
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| 3 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
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| 4 | */ |
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| 5 | #ifndef _IOC3_H |
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| 6 | #define _IOC3_H |
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| 7 | |
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| 8 | /* SUPERIO uart register map */ |
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| 9 | typedef volatile struct ioc3_uartregs { |
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| 10 | union { |
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| 11 | volatile __u8 rbr; /* read only, DLAB == 0 */ |
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| 12 | volatile __u8 thr; /* write only, DLAB == 0 */ |
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| 13 | volatile __u8 dll; /* DLAB == 1 */ |
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| 14 | } u1; |
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| 15 | union { |
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| 16 | volatile __u8 ier; /* DLAB == 0 */ |
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| 17 | volatile __u8 dlm; /* DLAB == 1 */ |
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| 18 | } u2; |
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| 19 | union { |
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| 20 | volatile __u8 iir; /* read only */ |
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| 21 | volatile __u8 fcr; /* write only */ |
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| 22 | } u3; |
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| 23 | volatile __u8 iu_lcr; |
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| 24 | volatile __u8 iu_mcr; |
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| 25 | volatile __u8 iu_lsr; |
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| 26 | volatile __u8 iu_msr; |
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| 27 | volatile __u8 iu_scr; |
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| 28 | } ioc3_uregs_t; |
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| 29 | |
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| 30 | #define iu_rbr u1.rbr |
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| 31 | #define iu_thr u1.thr |
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| 32 | #define iu_dll u1.dll |
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| 33 | #define iu_ier u2.ier |
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| 34 | #define iu_dlm u2.dlm |
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| 35 | #define iu_iir u3.iir |
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| 36 | #define iu_fcr u3.fcr |
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| 37 | |
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| 38 | struct ioc3_sioregs { |
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| 39 | volatile __u8 fill[0x141]; /* starts at 0x141 */ |
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| 40 | |
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| 41 | volatile __u8 uartc; |
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| 42 | volatile __u8 kbdcg; |
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| 43 | |
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| 44 | volatile __u8 fill0[0x150 - 0x142 - 1]; |
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| 45 | |
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| 46 | volatile __u8 pp_data; |
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| 47 | volatile __u8 pp_dsr; |
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| 48 | volatile __u8 pp_dcr; |
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| 49 | |
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| 50 | volatile __u8 fill1[0x158 - 0x152 - 1]; |
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| 51 | |
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| 52 | volatile __u8 pp_fifa; |
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| 53 | volatile __u8 pp_cfgb; |
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| 54 | volatile __u8 pp_ecr; |
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| 55 | |
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| 56 | volatile __u8 fill2[0x168 - 0x15a - 1]; |
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| 57 | |
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| 58 | volatile __u8 rtcad; |
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| 59 | volatile __u8 rtcdat; |
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| 60 | |
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| 61 | volatile __u8 fill3[0x170 - 0x169 - 1]; |
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| 62 | |
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| 63 | struct ioc3_uartregs uartb; /* 0x20170 */ |
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| 64 | struct ioc3_uartregs uarta; /* 0x20178 */ |
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| 65 | }; |
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| 66 | |
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| 67 | /* Register layout of IOC3 in configuration space. */ |
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| 68 | struct ioc3 { |
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| 69 | volatile __u32 pad0[7]; /* 0x00000 */ |
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| 70 | volatile __u32 sio_ir; /* 0x0001c */ |
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| 71 | volatile __u32 sio_ies; /* 0x00020 */ |
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| 72 | volatile __u32 sio_iec; /* 0x00024 */ |
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| 73 | volatile __u32 sio_cr; /* 0x00028 */ |
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| 74 | volatile __u32 int_out; /* 0x0002c */ |
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| 75 | volatile __u32 mcr; /* 0x00030 */ |
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| 76 | |
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| 77 | /* General Purpose I/O registers */ |
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| 78 | volatile __u32 gpcr_s; /* 0x00034 */ |
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| 79 | volatile __u32 gpcr_c; /* 0x00038 */ |
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| 80 | volatile __u32 gpdr; /* 0x0003c */ |
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| 81 | volatile __u32 gppr_0; /* 0x00040 */ |
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| 82 | volatile __u32 gppr_1; /* 0x00044 */ |
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| 83 | volatile __u32 gppr_2; /* 0x00048 */ |
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| 84 | volatile __u32 gppr_3; /* 0x0004c */ |
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| 85 | volatile __u32 gppr_4; /* 0x00050 */ |
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| 86 | volatile __u32 gppr_5; /* 0x00054 */ |
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| 87 | volatile __u32 gppr_6; /* 0x00058 */ |
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| 88 | volatile __u32 gppr_7; /* 0x0005c */ |
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| 89 | volatile __u32 gppr_8; /* 0x00060 */ |
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| 90 | volatile __u32 gppr_9; /* 0x00064 */ |
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| 91 | volatile __u32 gppr_10; /* 0x00068 */ |
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| 92 | volatile __u32 gppr_11; /* 0x0006c */ |
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| 93 | volatile __u32 gppr_12; /* 0x00070 */ |
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| 94 | volatile __u32 gppr_13; /* 0x00074 */ |
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| 95 | volatile __u32 gppr_14; /* 0x00078 */ |
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| 96 | volatile __u32 gppr_15; /* 0x0007c */ |
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| 97 | |
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| 98 | /* Parallel Port Registers */ |
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| 99 | volatile __u32 ppbr_h_a; /* 0x00080 */ |
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| 100 | volatile __u32 ppbr_l_a; /* 0x00084 */ |
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| 101 | volatile __u32 ppcr_a; /* 0x00088 */ |
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| 102 | volatile __u32 ppcr; /* 0x0008c */ |
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| 103 | volatile __u32 ppbr_h_b; /* 0x00090 */ |
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| 104 | volatile __u32 ppbr_l_b; /* 0x00094 */ |
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| 105 | volatile __u32 ppcr_b; /* 0x00098 */ |
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| 106 | |
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| 107 | /* Keyboard and Mouse Registers */ |
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| 108 | volatile __u32 km_csr; /* 0x0009c */ |
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| 109 | volatile __u32 k_rd; /* 0x000a0 */ |
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| 110 | volatile __u32 m_rd; /* 0x000a4 */ |
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| 111 | volatile __u32 k_wd; /* 0x000a8 */ |
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| 112 | volatile __u32 m_wd; /* 0x000ac */ |
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| 113 | |
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| 114 | /* Serial Port Registers */ |
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| 115 | volatile __u32 sbbr_h; /* 0x000b0 */ |
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| 116 | volatile __u32 sbbr_l; /* 0x000b4 */ |
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| 117 | volatile __u32 sscr_a; /* 0x000b8 */ |
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| 118 | volatile __u32 stpir_a; /* 0x000bc */ |
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| 119 | volatile __u32 stcir_a; /* 0x000c0 */ |
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| 120 | volatile __u32 srpir_a; /* 0x000c4 */ |
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| 121 | volatile __u32 srcir_a; /* 0x000c8 */ |
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| 122 | volatile __u32 srtr_a; /* 0x000cc */ |
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| 123 | volatile __u32 shadow_a; /* 0x000d0 */ |
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| 124 | volatile __u32 sscr_b; /* 0x000d4 */ |
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| 125 | volatile __u32 stpir_b; /* 0x000d8 */ |
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| 126 | volatile __u32 stcir_b; /* 0x000dc */ |
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| 127 | volatile __u32 srpir_b; /* 0x000e0 */ |
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| 128 | volatile __u32 srcir_b; /* 0x000e4 */ |
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| 129 | volatile __u32 srtr_b; /* 0x000e8 */ |
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| 130 | volatile __u32 shadow_b; /* 0x000ec */ |
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| 131 | |
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| 132 | /* Ethernet Registers */ |
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| 133 | volatile __u32 emcr; /* 0x000f0 */ |
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| 134 | volatile __u32 eisr; /* 0x000f4 */ |
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| 135 | volatile __u32 eier; /* 0x000f8 */ |
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| 136 | volatile __u32 ercsr; /* 0x000fc */ |
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| 137 | volatile __u32 erbr_h; /* 0x00100 */ |
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| 138 | volatile __u32 erbr_l; /* 0x00104 */ |
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| 139 | volatile __u32 erbar; /* 0x00108 */ |
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| 140 | volatile __u32 ercir; /* 0x0010c */ |
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| 141 | volatile __u32 erpir; /* 0x00110 */ |
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| 142 | volatile __u32 ertr; /* 0x00114 */ |
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| 143 | volatile __u32 etcsr; /* 0x00118 */ |
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| 144 | volatile __u32 ersr; /* 0x0011c */ |
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| 145 | volatile __u32 etcdc; /* 0x00120 */ |
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| 146 | volatile __u32 ebir; /* 0x00124 */ |
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| 147 | volatile __u32 etbr_h; /* 0x00128 */ |
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| 148 | volatile __u32 etbr_l; /* 0x0012c */ |
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| 149 | volatile __u32 etcir; /* 0x00130 */ |
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| 150 | volatile __u32 etpir; /* 0x00134 */ |
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| 151 | volatile __u32 emar_h; /* 0x00138 */ |
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| 152 | volatile __u32 emar_l; /* 0x0013c */ |
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| 153 | volatile __u32 ehar_h; /* 0x00140 */ |
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| 154 | volatile __u32 ehar_l; /* 0x00144 */ |
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| 155 | volatile __u32 micr; /* 0x00148 */ |
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| 156 | volatile __u32 midr_r; /* 0x0014c */ |
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| 157 | volatile __u32 midr_w; /* 0x00150 */ |
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| 158 | volatile __u32 pad1[(0x20000 - 0x00154) / 4]; |
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| 159 | |
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| 160 | /* SuperIO Registers XXX */ |
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| 161 | struct ioc3_sioregs sregs; /* 0x20000 */ |
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| 162 | volatile __u32 pad2[(0x40000 - 0x20180) / 4]; |
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| 163 | |
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| 164 | /* SSRAM Diagnostic Access */ |
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| 165 | volatile __u32 ssram[(0x80000 - 0x40000) / 4]; |
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| 166 | |
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| 167 | /* Bytebus device offsets |
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| 168 | 0x80000 - Access to the generic devices selected with DEV0 |
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| 169 | 0x9FFFF bytebus DEV_SEL_0 |
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| 170 | 0xA0000 - Access to the generic devices selected with DEV1 |
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| 171 | 0xBFFFF bytebus DEV_SEL_1 |
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| 172 | 0xC0000 - Access to the generic devices selected with DEV2 |
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| 173 | 0xDFFFF bytebus DEV_SEL_2 |
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| 174 | 0xE0000 - Access to the generic devices selected with DEV3 |
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| 175 | 0xFFFFF bytebus DEV_SEL_3 */ |
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| 176 | }; |
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| 177 | |
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| 178 | /* |
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| 179 | * Ethernet RX Buffer |
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| 180 | */ |
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| 181 | struct ioc3_erxbuf { |
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| 182 | __u32 w0; /* first word (valid,bcnt,cksum) */ |
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| 183 | __u32 err; /* second word various errors */ |
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| 184 | /* next comes n bytes of padding */ |
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| 185 | /* then the received ethernet frame itself */ |
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| 186 | }; |
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| 187 | |
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| 188 | #define ERXBUF_IPCKSUM_MASK 0x0000ffff |
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| 189 | #define ERXBUF_BYTECNT_MASK 0x07ff0000 |
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| 190 | #define ERXBUF_BYTECNT_SHIFT 16 |
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| 191 | #define ERXBUF_V 0x80000000 |
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| 192 | |
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| 193 | #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ |
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| 194 | #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ |
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| 195 | #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ |
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| 196 | #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ |
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| 197 | #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ |
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| 198 | #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ |
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| 199 | #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ |
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| 200 | #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ |
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| 201 | #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ |
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| 202 | #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ |
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| 203 | #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ |
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| 204 | #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ |
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| 205 | |
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| 206 | /* |
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| 207 | * Ethernet TX Descriptor |
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| 208 | */ |
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| 209 | #define ETXD_DATALEN 104 |
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| 210 | struct ioc3_etxd { |
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| 211 | __u32 cmd; /* command field */ |
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| 212 | __u32 bufcnt; /* buffer counts field */ |
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| 213 | __u64 p1; /* buffer pointer 1 */ |
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| 214 | __u64 p2; /* buffer pointer 2 */ |
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| 215 | __u8 data[ETXD_DATALEN]; /* opt. tx data */ |
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| 216 | }; |
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| 217 | |
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| 218 | #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ |
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| 219 | #define ETXD_INTWHENDONE 0x00001000 /* intr when done */ |
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| 220 | #define ETXD_D0V 0x00010000 /* data 0 valid */ |
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| 221 | #define ETXD_B1V 0x00020000 /* buf 1 valid */ |
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| 222 | #define ETXD_B2V 0x00040000 /* buf 2 valid */ |
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| 223 | #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ |
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| 224 | #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ |
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| 225 | #define ETXD_CHKOFF_SHIFT 20 |
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| 226 | |
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| 227 | #define ETXD_D0CNT_MASK 0x0000007f |
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| 228 | #define ETXD_B1CNT_MASK 0x0007ff00 |
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| 229 | #define ETXD_B1CNT_SHIFT 8 |
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| 230 | #define ETXD_B2CNT_MASK 0x7ff00000 |
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| 231 | #define ETXD_B2CNT_SHIFT 20 |
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| 232 | |
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| 233 | /* |
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| 234 | * Bytebus device space |
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| 235 | */ |
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| 236 | #define IOC3_BYTEBUS_DEV0 0x80000L |
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| 237 | #define IOC3_BYTEBUS_DEV1 0xa0000L |
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| 238 | #define IOC3_BYTEBUS_DEV2 0xc0000L |
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| 239 | #define IOC3_BYTEBUS_DEV3 0xe0000L |
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| 240 | |
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| 241 | /* ------------------------------------------------------------------------- */ |
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| 242 | |
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| 243 | /* Superio Registers (PIO Access) */ |
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| 244 | #define IOC3_SIO_BASE 0x20000 |
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| 245 | #define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ |
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| 246 | #define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ |
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| 247 | #define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ |
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| 248 | #define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ |
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| 249 | #define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ |
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| 250 | #define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ |
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| 251 | |
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| 252 | /* SSRAM Diagnostic Access */ |
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| 253 | #define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ |
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| 254 | #define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ |
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| 255 | #define IOC3_SSRAM_DM 0x0000ffff /* data mask */ |
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| 256 | #define IOC3_SSRAM_PM 0x00010000 /* parity mask */ |
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| 257 | |
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| 258 | /* bitmasks for PCI_SCR */ |
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| 259 | #define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ |
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| 260 | #define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ |
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| 261 | #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ |
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| 262 | #define PCI_SCR_RX_SERR (0x1 << 16) |
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| 263 | #define PCI_SCR_DROP_MODE (0x1 << 17) |
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| 264 | #define PCI_SCR_SIG_PAR_ERR (0x1 << 24) |
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| 265 | #define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) |
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| 266 | #define PCI_SCR_RX_TAR_ABRT (0x1 << 28) |
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| 267 | #define PCI_SCR_SIG_MST_ABRT (0x1 << 29) |
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| 268 | #define PCI_SCR_SIG_SERR (0x1 << 30) |
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| 269 | #define PCI_SCR_PAR_ERR (0x1 << 31) |
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| 270 | |
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| 271 | /* bitmasks for IOC3_KM_CSR */ |
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| 272 | #define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ |
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| 273 | #define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ |
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| 274 | #define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ |
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| 275 | #define KM_CSR_M_LCB 0x00000008 /* same for mouse */ |
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| 276 | #define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ |
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| 277 | #define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ |
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| 278 | #define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ |
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| 279 | #define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ |
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| 280 | #define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ |
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| 281 | #define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ |
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| 282 | #define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ |
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| 283 | #define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ |
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| 284 | #define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ |
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| 285 | #define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ |
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| 286 | #define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ |
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| 287 | #define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ |
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| 288 | #define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ |
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| 289 | #define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ |
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| 290 | #define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause |
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| 291 | SIO_IR to assert */ |
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| 292 | #define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause |
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| 293 | SIO_IR to assert */ |
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| 294 | #define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ |
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| 295 | #define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ |
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| 296 | #define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ |
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| 297 | #define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ |
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| 298 | |
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| 299 | /* bitmasks for IOC3_K_RD and IOC3_M_RD */ |
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| 300 | #define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ |
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| 301 | #define KM_RD_DATA_2_SHIFT 0 |
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| 302 | #define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ |
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| 303 | #define KM_RD_DATA_1_SHIFT 8 |
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| 304 | #define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ |
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| 305 | #define KM_RD_DATA_0_SHIFT 16 |
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| 306 | #define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ |
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| 307 | #define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ |
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| 308 | #define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ |
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| 309 | |
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| 310 | #define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ |
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| 311 | #define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ |
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| 312 | #define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ |
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| 313 | #define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ |
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| 314 | #define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ |
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| 315 | #define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) |
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| 316 | |
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| 317 | /* bitmasks for IOC3_K_WD & IOC3_M_WD */ |
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| 318 | #define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ |
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| 319 | #define KM_WD_WRT_DATA_SHIFT 0 |
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| 320 | |
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| 321 | /* bitmasks for serial RX status byte */ |
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| 322 | #define RXSB_OVERRUN 0x01 /* char(s) lost */ |
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| 323 | #define RXSB_PAR_ERR 0x02 /* parity error */ |
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| 324 | #define RXSB_FRAME_ERR 0x04 /* framing error */ |
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| 325 | #define RXSB_BREAK 0x08 /* break character */ |
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| 326 | #define RXSB_CTS 0x10 /* state of CTS */ |
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| 327 | #define RXSB_DCD 0x20 /* state of DCD */ |
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| 328 | #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ |
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| 329 | #define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ |
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| 330 | |
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| 331 | /* bitmasks for serial TX control byte */ |
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| 332 | #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ |
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| 333 | #define TXCB_INVALID 0x00 /* byte is invalid */ |
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| 334 | #define TXCB_VALID 0x40 /* byte is valid */ |
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| 335 | #define TXCB_MCR 0x80 /* data<7:0> to modem control register */ |
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| 336 | #define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ |
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| 337 | |
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| 338 | /* bitmasks for IOC3_SBBR_L */ |
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| 339 | #define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ |
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| 340 | #define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ |
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| 341 | |
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| 342 | /* bitmasks for IOC3_SSCR_<A:B> */ |
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| 343 | #define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ |
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| 344 | #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ |
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| 345 | #define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ |
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| 346 | #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ |
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| 347 | #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ |
|---|
| 348 | #define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ |
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| 349 | #define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ |
|---|
| 350 | #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ |
|---|
| 351 | #define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ |
|---|
| 352 | #define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ |
|---|
| 353 | #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ |
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| 354 | #define SSCR_RESET 0x80000000 /* reset DMA channels */ |
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| 355 | |
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| 356 | /* all producer/comsumer pointers are the same bitfield */ |
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| 357 | #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ |
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| 358 | #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ |
|---|
| 359 | #define PROD_CONS_PTR_OFF 3 |
|---|
| 360 | |
|---|
| 361 | /* bitmasks for IOC3_SRCIR_<A:B> */ |
|---|
| 362 | #define SRCIR_ARM 0x80000000 /* arm RX timer */ |
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| 363 | |
|---|
| 364 | /* bitmasks for IOC3_SRPIR_<A:B> */ |
|---|
| 365 | #define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ |
|---|
| 366 | #define SRPIR_BYTE_CNT_SHIFT 24 |
|---|
| 367 | |
|---|
| 368 | /* bitmasks for IOC3_STCIR_<A:B> */ |
|---|
| 369 | #define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ |
|---|
| 370 | #define STCIR_BYTE_CNT_SHIFT 24 |
|---|
| 371 | |
|---|
| 372 | /* bitmasks for IOC3_SHADOW_<A:B> */ |
|---|
| 373 | #define SHADOW_DR 0x00000001 /* data ready */ |
|---|
| 374 | #define SHADOW_OE 0x00000002 /* overrun error */ |
|---|
| 375 | #define SHADOW_PE 0x00000004 /* parity error */ |
|---|
| 376 | #define SHADOW_FE 0x00000008 /* framing error */ |
|---|
| 377 | #define SHADOW_BI 0x00000010 /* break interrupt */ |
|---|
| 378 | #define SHADOW_THRE 0x00000020 /* transmit holding register empty */ |
|---|
| 379 | #define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ |
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| 380 | #define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ |
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| 381 | #define SHADOW_DCTS 0x00010000 /* delta clear to send */ |
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| 382 | #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ |
|---|
| 383 | #define SHADOW_CTS 0x00100000 /* clear to send */ |
|---|
| 384 | #define SHADOW_DCD 0x00800000 /* data carrier detect */ |
|---|
| 385 | #define SHADOW_DTR 0x01000000 /* data terminal ready */ |
|---|
| 386 | #define SHADOW_RTS 0x02000000 /* request to send */ |
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| 387 | #define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ |
|---|
| 388 | #define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ |
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| 389 | #define SHADOW_LOOP 0x10000000 /* loopback enabled */ |
|---|
| 390 | |
|---|
| 391 | /* bitmasks for IOC3_SRTR_<A:B> */ |
|---|
| 392 | #define SRTR_CNT 0x00000fff /* reload value for RX timer */ |
|---|
| 393 | #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ |
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| 394 | #define SRTR_CNT_VAL_SHIFT 16 |
|---|
| 395 | #define SRTR_HZ 16000 /* SRTR clock frequency */ |
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| 396 | |
|---|
| 397 | /* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ |
|---|
| 398 | #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ |
|---|
| 399 | #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ |
|---|
| 400 | #define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ |
|---|
| 401 | #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ |
|---|
| 402 | #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ |
|---|
| 403 | #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ |
|---|
| 404 | #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ |
|---|
| 405 | #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ |
|---|
| 406 | #define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ |
|---|
| 407 | #define SIO_IR_SB_TX_MT 0x00000200 /* */ |
|---|
| 408 | #define SIO_IR_SB_RX_FULL 0x00000400 /* */ |
|---|
| 409 | #define SIO_IR_SB_RX_HIGH 0x00000800 /* */ |
|---|
| 410 | #define SIO_IR_SB_RX_TIMER 0x00001000 /* */ |
|---|
| 411 | #define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ |
|---|
| 412 | #define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ |
|---|
| 413 | #define SIO_IR_SB_INT 0x00008000 /* */ |
|---|
| 414 | #define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ |
|---|
| 415 | #define SIO_IR_SB_MEMERR 0x00020000 /* */ |
|---|
| 416 | #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ |
|---|
| 417 | #define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ |
|---|
| 418 | #define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ |
|---|
| 419 | #define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ |
|---|
| 420 | #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ |
|---|
| 421 | #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ |
|---|
| 422 | #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ |
|---|
| 423 | #define SIO_IR_GEN_INT_SHIFT 28 |
|---|
| 424 | |
|---|
| 425 | /* per device interrupt masks */ |
|---|
| 426 | #define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ |
|---|
| 427 | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ |
|---|
| 428 | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ |
|---|
| 429 | SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ |
|---|
| 430 | SIO_IR_SA_MEMERR) |
|---|
| 431 | #define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ |
|---|
| 432 | SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ |
|---|
| 433 | SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ |
|---|
| 434 | SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ |
|---|
| 435 | SIO_IR_SB_MEMERR) |
|---|
| 436 | #define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ |
|---|
| 437 | SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) |
|---|
| 438 | #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) |
|---|
| 439 | |
|---|
| 440 | /* macro to load pending interrupts */ |
|---|
| 441 | #define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ |
|---|
| 442 | PCI_INW(&((mem)->sio_ies_ro))) |
|---|
| 443 | |
|---|
| 444 | /* bitmasks for SIO_CR */ |
|---|
| 445 | #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ |
|---|
| 446 | #define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ |
|---|
| 447 | #define SIO_CR_SER_A_BASE_SHIFT 1 |
|---|
| 448 | #define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ |
|---|
| 449 | #define SIO_CR_SER_B_BASE_SHIFT 8 |
|---|
| 450 | #define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ |
|---|
| 451 | #define SIO_CR_CMD_PULSE_SHIFT 15 |
|---|
| 452 | #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ |
|---|
| 453 | #define SIO_CR_ARB_DIAG_TXA 0x00000000 |
|---|
| 454 | #define SIO_CR_ARB_DIAG_RXA 0x00080000 |
|---|
| 455 | #define SIO_CR_ARB_DIAG_TXB 0x00100000 |
|---|
| 456 | #define SIO_CR_ARB_DIAG_RXB 0x00180000 |
|---|
| 457 | #define SIO_CR_ARB_DIAG_PP 0x00200000 |
|---|
| 458 | #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ |
|---|
| 459 | |
|---|
| 460 | /* bitmasks for INT_OUT */ |
|---|
| 461 | #define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ |
|---|
| 462 | #define INT_OUT_MODE 0x00070000 /* mode mask */ |
|---|
| 463 | #define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ |
|---|
| 464 | #define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ |
|---|
| 465 | #define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ |
|---|
| 466 | #define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ |
|---|
| 467 | #define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ |
|---|
| 468 | #define INT_OUT_DIAG 0x40000000 /* diag mode */ |
|---|
| 469 | #define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ |
|---|
| 470 | |
|---|
| 471 | /* time constants for INT_OUT */ |
|---|
| 472 | #define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ |
|---|
| 473 | #define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ |
|---|
| 474 | #define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ |
|---|
| 475 | (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ |
|---|
| 476 | 100 / INT_OUT_NS_PER_TICK - 1) |
|---|
| 477 | #define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ |
|---|
| 478 | (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) |
|---|
| 479 | #define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ |
|---|
| 480 | #define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ |
|---|
| 481 | |
|---|
| 482 | /* bitmasks for GPCR */ |
|---|
| 483 | #define GPCR_DIR 0x000000ff /* tristate pin input or output */ |
|---|
| 484 | #define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ |
|---|
| 485 | #define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ |
|---|
| 486 | #define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ |
|---|
| 487 | |
|---|
| 488 | /* values for GPCR */ |
|---|
| 489 | #define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ |
|---|
| 490 | #define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ |
|---|
| 491 | #define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ |
|---|
| 492 | #define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ |
|---|
| 493 | #define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ |
|---|
| 494 | |
|---|
| 495 | /* defs for some of the generic I/O pins */ |
|---|
| 496 | #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ |
|---|
| 497 | #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ |
|---|
| 498 | #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ |
|---|
| 499 | |
|---|
| 500 | #define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ |
|---|
| 501 | #define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ |
|---|
| 502 | #define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ |
|---|
| 503 | |
|---|
| 504 | #define EMCR_DUPLEX 0x00000001 |
|---|
| 505 | #define EMCR_PROMISC 0x00000002 |
|---|
| 506 | #define EMCR_PADEN 0x00000004 |
|---|
| 507 | #define EMCR_RXOFF_MASK 0x000001f8 |
|---|
| 508 | #define EMCR_RXOFF_SHIFT 3 |
|---|
| 509 | #define EMCR_RAMPAR 0x00000200 |
|---|
| 510 | #define EMCR_BADPAR 0x00000800 |
|---|
| 511 | #define EMCR_BUFSIZ 0x00001000 |
|---|
| 512 | #define EMCR_TXDMAEN 0x00002000 |
|---|
| 513 | #define EMCR_TXEN 0x00004000 |
|---|
| 514 | #define EMCR_RXDMAEN 0x00008000 |
|---|
| 515 | #define EMCR_RXEN 0x00010000 |
|---|
| 516 | #define EMCR_LOOPBACK 0x00020000 |
|---|
| 517 | #define EMCR_ARB_DIAG 0x001c0000 |
|---|
| 518 | #define EMCR_ARB_DIAG_IDLE 0x00200000 |
|---|
| 519 | #define EMCR_RST 0x80000000 |
|---|
| 520 | |
|---|
| 521 | #define EISR_RXTIMERINT 0x00000001 |
|---|
| 522 | #define EISR_RXTHRESHINT 0x00000002 |
|---|
| 523 | #define EISR_RXOFLO 0x00000004 |
|---|
| 524 | #define EISR_RXBUFOFLO 0x00000008 |
|---|
| 525 | #define EISR_RXMEMERR 0x00000010 |
|---|
| 526 | #define EISR_RXPARERR 0x00000020 |
|---|
| 527 | #define EISR_TXEMPTY 0x00010000 |
|---|
| 528 | #define EISR_TXRTRY 0x00020000 |
|---|
| 529 | #define EISR_TXEXDEF 0x00040000 |
|---|
| 530 | #define EISR_TXLCOL 0x00080000 |
|---|
| 531 | #define EISR_TXGIANT 0x00100000 |
|---|
| 532 | #define EISR_TXBUFUFLO 0x00200000 |
|---|
| 533 | #define EISR_TXEXPLICIT 0x00400000 |
|---|
| 534 | #define EISR_TXCOLLWRAP 0x00800000 |
|---|
| 535 | #define EISR_TXDEFERWRAP 0x01000000 |
|---|
| 536 | #define EISR_TXMEMERR 0x02000000 |
|---|
| 537 | #define EISR_TXPARERR 0x04000000 |
|---|
| 538 | |
|---|
| 539 | #define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ |
|---|
| 540 | #define ERCSR_RX_TMR 0x40000000 /* simulation only */ |
|---|
| 541 | #define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ |
|---|
| 542 | |
|---|
| 543 | #define ERBR_ALIGNMENT 4096 |
|---|
| 544 | #define ERBR_L_RXRINGBASE_MASK 0xfffff000 |
|---|
| 545 | |
|---|
| 546 | #define ERBAR_BARRIER_BIT 0x0100 |
|---|
| 547 | #define ERBAR_RXBARR_MASK 0xffff0000 |
|---|
| 548 | #define ERBAR_RXBARR_SHIFT 16 |
|---|
| 549 | |
|---|
| 550 | #define ERCIR_RXCONSUME_MASK 0x00000fff |
|---|
| 551 | |
|---|
| 552 | #define ERPIR_RXPRODUCE_MASK 0x00000fff |
|---|
| 553 | #define ERPIR_ARM 0x80000000 |
|---|
| 554 | |
|---|
| 555 | #define ERTR_CNT_MASK 0x000007ff |
|---|
| 556 | |
|---|
| 557 | #define ETCSR_IPGT_MASK 0x0000007f |
|---|
| 558 | #define ETCSR_IPGR1_MASK 0x00007f00 |
|---|
| 559 | #define ETCSR_IPGR1_SHIFT 8 |
|---|
| 560 | #define ETCSR_IPGR2_MASK 0x007f0000 |
|---|
| 561 | #define ETCSR_IPGR2_SHIFT 16 |
|---|
| 562 | #define ETCSR_NOTXCLK 0x80000000 |
|---|
| 563 | |
|---|
| 564 | #define ETCDC_COLLCNT_MASK 0x0000ffff |
|---|
| 565 | #define ETCDC_DEFERCNT_MASK 0xffff0000 |
|---|
| 566 | #define ETCDC_DEFERCNT_SHIFT 16 |
|---|
| 567 | |
|---|
| 568 | #define ETBR_ALIGNMENT (64*1024) |
|---|
| 569 | #define ETBR_L_RINGSZ_MASK 0x00000001 |
|---|
| 570 | #define ETBR_L_RINGSZ128 0 |
|---|
| 571 | #define ETBR_L_RINGSZ512 1 |
|---|
| 572 | #define ETBR_L_TXRINGBASE_MASK 0xffffc000 |
|---|
| 573 | |
|---|
| 574 | #define ETCIR_TXCONSUME_MASK 0x0000ffff |
|---|
| 575 | #define ETCIR_IDLE 0x80000000 |
|---|
| 576 | |
|---|
| 577 | #define ETPIR_TXPRODUCE_MASK 0x0000ffff |
|---|
| 578 | |
|---|
| 579 | #define EBIR_TXBUFPROD_MASK 0x0000001f |
|---|
| 580 | #define EBIR_TXBUFCONS_MASK 0x00001f00 |
|---|
| 581 | #define EBIR_TXBUFCONS_SHIFT 8 |
|---|
| 582 | #define EBIR_RXBUFPROD_MASK 0x007fc000 |
|---|
| 583 | #define EBIR_RXBUFPROD_SHIFT 14 |
|---|
| 584 | #define EBIR_RXBUFCONS_MASK 0xff800000 |
|---|
| 585 | #define EBIR_RXBUFCONS_SHIFT 23 |
|---|
| 586 | |
|---|
| 587 | #define MICR_REGADDR_MASK 0x0000001f |
|---|
| 588 | #define MICR_PHYADDR_MASK 0x000003e0 |
|---|
| 589 | #define MICR_PHYADDR_SHIFT 5 |
|---|
| 590 | #define MICR_READTRIG 0x00000400 |
|---|
| 591 | #define MICR_BUSY 0x00000800 |
|---|
| 592 | |
|---|
| 593 | #define MIDR_DATA_MASK 0x0000ffff |
|---|
| 594 | |
|---|
| 595 | #define ERXBUF_IPCKSUM_MASK 0x0000ffff |
|---|
| 596 | #define ERXBUF_BYTECNT_MASK 0x07ff0000 |
|---|
| 597 | #define ERXBUF_BYTECNT_SHIFT 16 |
|---|
| 598 | #define ERXBUF_V 0x80000000 |
|---|
| 599 | |
|---|
| 600 | #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ |
|---|
| 601 | #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ |
|---|
| 602 | #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ |
|---|
| 603 | #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ |
|---|
| 604 | #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ |
|---|
| 605 | #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ |
|---|
| 606 | #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ |
|---|
| 607 | #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ |
|---|
| 608 | #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ |
|---|
| 609 | #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ |
|---|
| 610 | #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ |
|---|
| 611 | #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ |
|---|
| 612 | |
|---|
| 613 | #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ |
|---|
| 614 | #define ETXD_INTWHENDONE 0x00001000 /* intr when done */ |
|---|
| 615 | #define ETXD_D0V 0x00010000 /* data 0 valid */ |
|---|
| 616 | #define ETXD_B1V 0x00020000 /* buf 1 valid */ |
|---|
| 617 | #define ETXD_B2V 0x00040000 /* buf 2 valid */ |
|---|
| 618 | #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ |
|---|
| 619 | #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ |
|---|
| 620 | #define ETXD_CHKOFF_SHIFT 20 |
|---|
| 621 | |
|---|
| 622 | #define ETXD_D0CNT_MASK 0x0000007f |
|---|
| 623 | #define ETXD_B1CNT_MASK 0x0007ff00 |
|---|
| 624 | #define ETXD_B1CNT_SHIFT 8 |
|---|
| 625 | #define ETXD_B2CNT_MASK 0x7ff00000 |
|---|
| 626 | #define ETXD_B2CNT_SHIFT 20 |
|---|
| 627 | |
|---|
| 628 | typedef enum ioc3_subdevs_e { |
|---|
| 629 | ioc3_subdev_ether, |
|---|
| 630 | ioc3_subdev_generic, |
|---|
| 631 | ioc3_subdev_nic, |
|---|
| 632 | ioc3_subdev_kbms, |
|---|
| 633 | ioc3_subdev_ttya, |
|---|
| 634 | ioc3_subdev_ttyb, |
|---|
| 635 | ioc3_subdev_ecpp, |
|---|
| 636 | ioc3_subdev_rt, |
|---|
| 637 | ioc3_nsubdevs |
|---|
| 638 | } ioc3_subdev_t; |
|---|
| 639 | |
|---|
| 640 | /* subdevice disable bits, |
|---|
| 641 | * from the standard INFO_LBL_SUBDEVS |
|---|
| 642 | */ |
|---|
| 643 | #define IOC3_SDB_ETHER (1<<ioc3_subdev_ether) |
|---|
| 644 | #define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic) |
|---|
| 645 | #define IOC3_SDB_NIC (1<<ioc3_subdev_nic) |
|---|
| 646 | #define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms) |
|---|
| 647 | #define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya) |
|---|
| 648 | #define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb) |
|---|
| 649 | #define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp) |
|---|
| 650 | #define IOC3_SDB_RT (1<<ioc3_subdev_rt) |
|---|
| 651 | |
|---|
| 652 | #define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1) |
|---|
| 653 | |
|---|
| 654 | #define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB) |
|---|
| 655 | |
|---|
| 656 | #define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS |
|---|
| 657 | |
|---|
| 658 | #define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER |
|---|
| 659 | #define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT) |
|---|
| 660 | |
|---|
| 661 | #endif /* _IOC3_H */ |
|---|
