source: svn/trunk/newcon3bcm2_21bu/toolchain/mips-linux-uclibc/include/asm/vr41xx/vr41xx.h

Last change on this file was 2, checked in by jglee, 11 years ago

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1/*
2 * include/asm-mips/vr41xx/vr41xx.h
3 *
4 * Include file for NEC VR4100 series.
5 *
6 * Copyright (C) 1999 Michael Klar
7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef __NEC_VR41XX_H
18#define __NEC_VR41XX_H
19
20#include <linux/interrupt.h>
21
22/*
23 * CPU Revision
24 */
25/* VR4122 0x00000c70-0x00000c72 */
26#define PRID_VR4122_REV1_0      0x00000c70
27#define PRID_VR4122_REV2_0      0x00000c70
28#define PRID_VR4122_REV2_1      0x00000c70
29#define PRID_VR4122_REV3_0      0x00000c71
30#define PRID_VR4122_REV3_1      0x00000c72
31
32/* VR4181A 0x00000c73-0x00000c7f */
33#define PRID_VR4181A_REV1_0     0x00000c73
34#define PRID_VR4181A_REV1_1     0x00000c74
35
36/* VR4131 0x00000c80-0x00000c83 */
37#define PRID_VR4131_REV1_2      0x00000c80
38#define PRID_VR4131_REV2_0      0x00000c81
39#define PRID_VR4131_REV2_1      0x00000c82
40#define PRID_VR4131_REV2_2      0x00000c83
41
42/* VR4133 0x00000c84- */
43#define PRID_VR4133             0x00000c84
44
45/*
46 * Bus Control Uint
47 */
48extern unsigned long vr41xx_calculate_clock_frequency(void);
49extern unsigned long vr41xx_get_vtclock_frequency(void);
50extern unsigned long vr41xx_get_tclock_frequency(void);
51
52/*
53 * Clock Mask Unit
54 */
55typedef enum {
56        PIU_CLOCK,
57        SIU_CLOCK,
58        AIU_CLOCK,
59        KIU_CLOCK,
60        FIR_CLOCK,
61        DSIU_CLOCK,
62        CSI_CLOCK,
63        PCIU_CLOCK,
64        HSP_CLOCK,
65        PCI_CLOCK,
66        CEU_CLOCK,
67        ETHER0_CLOCK,
68        ETHER1_CLOCK
69} vr41xx_clock_t;
70
71extern void vr41xx_supply_clock(vr41xx_clock_t clock);
72extern void vr41xx_mask_clock(vr41xx_clock_t clock);
73
74/*
75 * Interrupt Control Unit
76 */
77/* CPU core Interrupt Numbers */
78#define MIPS_CPU_IRQ_BASE       0
79#define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
80#define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
81#define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
82#define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
83#define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
84#define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
85#define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
86#define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
87#define TIMER_IRQ               MIPS_CPU_IRQ(7)
88
89/* SYINT1 Interrupt Numbers */
90#define SYSINT1_IRQ_BASE        8
91#define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
92#define BATTRY_IRQ              SYSINT1_IRQ(0)
93#define POWER_IRQ               SYSINT1_IRQ(1)
94#define RTCLONG1_IRQ            SYSINT1_IRQ(2)
95#define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
96/* RFU */
97#define PIU_IRQ                 SYSINT1_IRQ(5)
98#define AIU_IRQ                 SYSINT1_IRQ(6)
99#define KIU_IRQ                 SYSINT1_IRQ(7)
100#define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
101#define SIU_IRQ                 SYSINT1_IRQ(9)
102#define BUSERR_IRQ              SYSINT1_IRQ(10)
103#define SOFTINT_IRQ             SYSINT1_IRQ(11)
104#define CLKRUN_IRQ              SYSINT1_IRQ(12)
105#define DOZEPIU_IRQ             SYSINT1_IRQ(13)
106#define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
107
108/* SYSINT2 Interrupt Numbers */
109#define SYSINT2_IRQ_BASE        24
110#define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
111#define RTCLONG2_IRQ            SYSINT2_IRQ(0)
112#define LED_IRQ                 SYSINT2_IRQ(1)
113#define HSP_IRQ                 SYSINT2_IRQ(2)
114#define TCLOCK_IRQ              SYSINT2_IRQ(3)
115#define FIR_IRQ                 SYSINT2_IRQ(4)
116#define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
117#define DSIU_IRQ                SYSINT2_IRQ(5)
118#define PCI_IRQ                 SYSINT2_IRQ(6)
119#define SCU_IRQ                 SYSINT2_IRQ(7)
120#define CSI_IRQ                 SYSINT2_IRQ(8)
121#define BCU_IRQ                 SYSINT2_IRQ(9)
122#define ETHERNET_IRQ            SYSINT2_IRQ(10)
123#define SYSINT2_IRQ_LAST        ETHERNET_IRQ
124
125/* GIU Interrupt Numbers */
126#define GIU_IRQ_BASE            40
127#define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
128#define GIU_IRQ_LAST            GIU_IRQ(31)
129#define GIU_IRQ_TO_PIN(x)       ((x) - GIU_IRQ_BASE)    /* Pin 0-31 */
130
131extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
132extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
133
134#define PIUINT_COMMAND          0x0040
135#define PIUINT_DATA             0x0020
136#define PIUINT_PAGE1            0x0010
137#define PIUINT_PAGE0            0x0008
138#define PIUINT_DATALOST         0x0004
139#define PIUINT_STATUSCHANGE     0x0001
140
141extern void vr41xx_enable_piuint(uint16_t mask);
142extern void vr41xx_disable_piuint(uint16_t mask);
143
144#define AIUINT_INPUT_DMAEND     0x0800
145#define AIUINT_INPUT_DMAHALT    0x0400
146#define AIUINT_INPUT_DATALOST   0x0200
147#define AIUINT_INPUT_DATA       0x0100
148#define AIUINT_OUTPUT_DMAEND    0x0008
149#define AIUINT_OUTPUT_DMAHALT   0x0004
150#define AIUINT_OUTPUT_NODATA    0x0002
151
152extern void vr41xx_enable_aiuint(uint16_t mask);
153extern void vr41xx_disable_aiuint(uint16_t mask);
154
155#define KIUINT_DATALOST         0x0004
156#define KIUINT_DATAREADY        0x0002
157#define KIUINT_SCAN             0x0001
158
159extern void vr41xx_enable_kiuint(uint16_t mask);
160extern void vr41xx_disable_kiuint(uint16_t mask);
161
162#define DSIUINT_CTS             0x0800
163#define DSIUINT_RXERR           0x0400
164#define DSIUINT_RX              0x0200
165#define DSIUINT_TX              0x0100
166#define DSIUINT_ALL             0x0f00
167
168extern void vr41xx_enable_dsiuint(uint16_t mask);
169extern void vr41xx_disable_dsiuint(uint16_t mask);
170
171#define FIRINT_UNIT             0x0010
172#define FIRINT_RX_DMAEND        0x0008
173#define FIRINT_RX_DMAHALT       0x0004
174#define FIRINT_TX_DMAEND        0x0002
175#define FIRINT_TX_DMAHALT       0x0001
176
177extern void vr41xx_enable_firint(uint16_t mask);
178extern void vr41xx_disable_firint(uint16_t mask);
179
180extern void vr41xx_enable_pciint(void);
181extern void vr41xx_disable_pciint(void);
182
183extern void vr41xx_enable_scuint(void);
184extern void vr41xx_disable_scuint(void);
185
186#define CSIINT_TX_DMAEND        0x0040
187#define CSIINT_TX_DMAHALT       0x0020
188#define CSIINT_TX_DATA          0x0010
189#define CSIINT_TX_FIFOEMPTY     0x0008
190#define CSIINT_RX_DMAEND        0x0004
191#define CSIINT_RX_DMAHALT       0x0002
192#define CSIINT_RX_FIFOEMPTY     0x0001
193
194extern void vr41xx_enable_csiint(uint16_t mask);
195extern void vr41xx_disable_csiint(uint16_t mask);
196
197extern void vr41xx_enable_bcuint(void);
198extern void vr41xx_disable_bcuint(void);
199
200/*
201 * General-Purpose I/O Unit
202 */
203enum {
204        TRIGGER_LEVEL,
205        TRIGGER_EDGE,
206        TRIGGER_EDGE_FALLING,
207        TRIGGER_EDGE_RISING
208};
209
210enum {
211        SIGNAL_THROUGH,
212        SIGNAL_HOLD
213};
214
215extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
216
217enum {
218        LEVEL_LOW,
219        LEVEL_HIGH
220};
221
222extern void vr41xx_set_irq_level(int pin, int level);
223
224enum {
225        PIO_INPUT,
226        PIO_OUTPUT
227};
228
229enum {
230        DATA_LOW,
231        DATA_HIGH
232};
233
234#endif /* __NEC_VR41XX_H */
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