| 1 | #ifndef _PS2ESDI_H_ |
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| 2 | #define _PS2ESDI_H_ |
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| 3 | |
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| 4 | #define NRML_ESDI_ID 0xddff |
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| 5 | #define INTG_ESDI_ID 0xdf9f |
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| 6 | |
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| 7 | #define PRIMARY_IO_BASE 0x3510 |
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| 8 | #define ALT_IO_BASE 0x3518 |
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| 9 | |
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| 10 | #define ESDI_CMD_INT (io_base+0) |
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| 11 | #define ESDI_STT_INT (io_base+0) |
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| 12 | #define ESDI_CONTROL (io_base+2) |
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| 13 | #define ESDI_STATUS (io_base+2) |
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| 14 | #define ESDI_ATTN (io_base+3) |
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| 15 | #define ESDI_INTRPT (io_base+3) |
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| 16 | |
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| 17 | #define STATUS_ENABLED 0x01 |
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| 18 | #define STATUS_ALTERNATE 0x02 |
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| 19 | #define STATUS_BUSY 0x10 |
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| 20 | #define STATUS_STAT_AVAIL 0x08 |
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| 21 | #define STATUS_INTR 0x01 |
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| 22 | #define STATUS_RESET_FAIL 0xea |
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| 23 | #define STATUS_CMD_INF 0x04 |
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| 24 | |
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| 25 | #define CTRL_SOFT_RESET 0xe4 |
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| 26 | #define CTRL_HARD_RESET 0x80 |
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| 27 | #define CTRL_EOI 0xe2 |
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| 28 | #define CTRL_ENABLE_DMA 0x02 |
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| 29 | #define CTRL_ENABLE_INTR 0x01 |
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| 30 | #define CTRL_DISABLE_INTR 0x00 |
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| 31 | |
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| 32 | #define ATT_EOI 0x02 |
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| 33 | |
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| 34 | /* bits of word 0 of configuration status block. more info see p.38 of tech ref */ |
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| 35 | #define CONFIG_IS 0x10 /* Invalid Secondary */ |
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| 36 | #define CONFIG_ZD 0x08 /* Zero Defect */ |
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| 37 | #define CONFIG_SF 0x04 /* Skewed Format */ |
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| 38 | #define CONFIG_FR 0x02 /* Removable */ |
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| 39 | #define CONFIG_RT 0x01 /* Retries */ |
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| 40 | |
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| 41 | #define PORT_SYS_A 0x92 |
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| 42 | #define PORT_DMA_FN 0x18 |
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| 43 | #define PORT_DMA_EX 0x1a |
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| 44 | |
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| 45 | #define ON (unsigned char)0x40 |
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| 46 | #define OFF (unsigned char)~ON |
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| 47 | #define LITE_ON outb(inb(PORT_SYS_A) | ON,PORT_SYS_A) |
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| 48 | #define LITE_OFF outb((inb(PORT_SYS_A) & OFF),PORT_SYS_A) |
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| 49 | |
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| 50 | #define FAIL 0 |
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| 51 | #define SUCCES 1 |
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| 52 | |
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| 53 | #define INT_CMD_COMPLETE 0x01 |
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| 54 | #define INT_CMD_ECC 0x03 |
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| 55 | #define INT_CMD_RETRY 0x05 |
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| 56 | #define INT_CMD_FORMAT 0x06 |
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| 57 | #define INT_CMD_ECC_RETRY 0x07 |
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| 58 | #define INT_CMD_WARNING 0x08 |
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| 59 | #define INT_CMD_ABORT 0x09 |
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| 60 | #define INT_RESET 0x0A |
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| 61 | #define INT_TRANSFER_REQ 0x0B |
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| 62 | #define INT_CMD_FAILED 0x0C |
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| 63 | #define INT_DMA_ERR 0x0D |
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| 64 | #define INT_CMD_BLK_ERR 0x0E |
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| 65 | #define INT_ATTN_ERROR 0x0F |
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| 66 | |
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| 67 | #define DMA_MASK_CHAN 0x90 |
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| 68 | #define DMA_UNMASK_CHAN 0xA0 |
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| 69 | #define DMA_WRITE_ADDR 0x20 |
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| 70 | #define DMA_WRITE_TC 0x40 |
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| 71 | #define DMA_WRITE_MODE 0x70 |
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| 72 | |
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| 73 | #define CMD_GET_DEV_CONFIG 0x09 |
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| 74 | #define CMD_READ 0x4601 |
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| 75 | #define CMD_WRITE 0x4602 |
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| 76 | #define DMA_READ_16 0x4C |
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| 77 | #define DMA_WRITE_16 0x44 |
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| 78 | |
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| 79 | |
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| 80 | #define MB 1024*1024 |
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| 81 | #define SECT_SIZE 512 |
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| 82 | |
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| 83 | #define ERROR 1 |
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| 84 | #define OK 0 |
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| 85 | |
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| 86 | #define HDIO_GETGEO 0x0301 |
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| 87 | |
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| 88 | #define FALSE 0 |
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| 89 | #define TRUE !FALSE |
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| 90 | |
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| 91 | struct ps2esdi_geometry { |
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| 92 | unsigned char heads; |
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| 93 | unsigned char sectors; |
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| 94 | unsigned short cylinders; |
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| 95 | unsigned long start; |
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| 96 | }; |
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| 97 | |
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| 98 | #endif /* _PS2ESDI_H_ */ |
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