| 1 | /* |
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| 2 | * include/linux/serial_reg.h |
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| 3 | * |
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| 4 | * Copyright (C) 1992, 1994 by Theodore Ts'o. |
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| 5 | * |
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| 6 | * Redistribution of this file is permitted under the terms of the GNU |
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| 7 | * Public License (GPL) |
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| 8 | * |
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| 9 | * These are the UART port assignments, expressed as offsets from the base |
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| 10 | * register. These assignments should hold for any serial port based on |
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| 11 | * a 8250, 16450, or 16550(A). |
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| 12 | */ |
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| 13 | |
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| 14 | #ifndef _LINUX_SERIAL_REG_H |
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| 15 | #define _LINUX_SERIAL_REG_H |
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| 16 | |
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| 17 | /* |
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| 18 | * DLAB=0 |
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| 19 | */ |
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| 20 | #define UART_RX 0 /* In: Receive buffer */ |
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| 21 | #define UART_TX 0 /* Out: Transmit buffer */ |
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| 22 | |
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| 23 | #define UART_IER 1 /* Out: Interrupt Enable Register */ |
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| 24 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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| 25 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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| 26 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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| 27 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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| 28 | /* |
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| 29 | * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 |
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| 30 | */ |
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| 31 | #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ |
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| 32 | |
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| 33 | #define UART_IIR 2 /* In: Interrupt ID Register */ |
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| 34 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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| 35 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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| 36 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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| 37 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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| 38 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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| 39 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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| 40 | |
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| 41 | #define UART_FCR 2 /* Out: FIFO Control Register */ |
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| 42 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ |
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| 43 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
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| 44 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
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| 45 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
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| 46 | /* |
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| 47 | * Note: The FIFO trigger levels are chip specific: |
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| 48 | * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 |
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| 49 | * PC16550D: 1 4 8 14 xx xx xx xx |
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| 50 | * TI16C550A: 1 4 8 14 xx xx xx xx |
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| 51 | * TI16C550C: 1 4 8 14 xx xx xx xx |
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| 52 | * ST16C550: 1 4 8 14 xx xx xx xx |
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| 53 | * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 |
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| 54 | * NS16C552: 1 4 8 14 xx xx xx xx |
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| 55 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 |
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| 56 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 |
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| 57 | * TI16C752: 8 16 56 60 8 16 32 56 |
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| 58 | */ |
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| 59 | #define UART_FCR_R_TRIG_00 0x00 |
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| 60 | #define UART_FCR_R_TRIG_01 0x40 |
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| 61 | #define UART_FCR_R_TRIG_10 0x80 |
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| 62 | #define UART_FCR_R_TRIG_11 0xc0 |
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| 63 | #define UART_FCR_T_TRIG_00 0x00 |
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| 64 | #define UART_FCR_T_TRIG_01 0x10 |
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| 65 | #define UART_FCR_T_TRIG_10 0x20 |
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| 66 | #define UART_FCR_T_TRIG_11 0x30 |
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| 67 | |
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| 68 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
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| 69 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
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| 70 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
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| 71 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
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| 72 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
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| 73 | /* 16650 definitions */ |
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| 74 | #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ |
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| 75 | #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ |
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| 76 | #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ |
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| 77 | #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ |
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| 78 | #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ |
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| 79 | #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ |
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| 80 | #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ |
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| 81 | #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ |
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| 82 | #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ |
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| 83 | |
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| 84 | #define UART_LCR 3 /* Out: Line Control Register */ |
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| 85 | /* |
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| 86 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting |
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| 87 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. |
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| 88 | */ |
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| 89 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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| 90 | #define UART_LCR_SBC 0x40 /* Set break control */ |
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| 91 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ |
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| 92 | #define UART_LCR_EPAR 0x10 /* Even parity select */ |
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| 93 | #define UART_LCR_PARITY 0x08 /* Parity Enable */ |
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| 94 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ |
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| 95 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ |
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| 96 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ |
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| 97 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
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| 98 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
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| 99 | |
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| 100 | #define UART_MCR 4 /* Out: Modem Control Register */ |
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| 101 | #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ |
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| 102 | #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ |
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| 103 | #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ |
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| 104 | #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ |
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| 105 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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| 106 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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| 107 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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| 108 | #define UART_MCR_RTS 0x02 /* RTS complement */ |
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| 109 | #define UART_MCR_DTR 0x01 /* DTR complement */ |
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| 110 | |
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| 111 | #define UART_LSR 5 /* In: Line Status Register */ |
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| 112 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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| 113 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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| 114 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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| 115 | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
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| 116 | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
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| 117 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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| 118 | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
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| 119 | |
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| 120 | #define UART_MSR 6 /* In: Modem Status Register */ |
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| 121 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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| 122 | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
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| 123 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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| 124 | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
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| 125 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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| 126 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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| 127 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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| 128 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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| 129 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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| 130 | |
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| 131 | #define UART_SCR 7 /* I/O: Scratch Register */ |
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| 132 | |
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| 133 | /* |
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| 134 | * DLAB=1 |
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| 135 | */ |
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| 136 | #define UART_DLL 0 /* Out: Divisor Latch Low */ |
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| 137 | #define UART_DLM 1 /* Out: Divisor Latch High */ |
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| 138 | |
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| 139 | /* |
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| 140 | * LCR=0xBF (or DLAB=1 for 16C660) |
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| 141 | */ |
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| 142 | #define UART_EFR 2 /* I/O: Extended Features Register */ |
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| 143 | #define UART_EFR_CTS 0x80 /* CTS flow control */ |
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| 144 | #define UART_EFR_RTS 0x40 /* RTS flow control */ |
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| 145 | #define UART_EFR_SCD 0x20 /* Special character detect */ |
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| 146 | #define UART_EFR_ECB 0x10 /* Enhanced control bit */ |
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| 147 | /* |
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| 148 | * the low four bits control software flow control |
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| 149 | */ |
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| 150 | |
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| 151 | /* |
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| 152 | * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 |
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| 153 | */ |
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| 154 | #define UART_XON1 4 /* I/O: Xon character 1 */ |
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| 155 | #define UART_XON2 5 /* I/O: Xon character 2 */ |
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| 156 | #define UART_XOFF1 6 /* I/O: Xoff character 1 */ |
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| 157 | #define UART_XOFF2 7 /* I/O: Xoff character 2 */ |
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| 158 | |
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| 159 | /* |
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| 160 | * EFR[4]=1 MCR[6]=1, TI16C752 |
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| 161 | */ |
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| 162 | #define UART_TI752_TCR 6 /* I/O: transmission control register */ |
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| 163 | #define UART_TI752_TLR 7 /* I/O: trigger level register */ |
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| 164 | |
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| 165 | /* |
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| 166 | * LCR=0xBF, XR16C85x |
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| 167 | */ |
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| 168 | #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx |
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| 169 | * In: Fifo count |
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| 170 | * Out: Fifo custom trigger levels */ |
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| 171 | /* |
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| 172 | * These are the definitions for the Programmable Trigger Register |
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| 173 | */ |
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| 174 | #define UART_TRG_1 0x01 |
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| 175 | #define UART_TRG_4 0x04 |
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| 176 | #define UART_TRG_8 0x08 |
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| 177 | #define UART_TRG_16 0x10 |
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| 178 | #define UART_TRG_32 0x20 |
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| 179 | #define UART_TRG_64 0x40 |
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| 180 | #define UART_TRG_96 0x60 |
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| 181 | #define UART_TRG_120 0x78 |
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| 182 | #define UART_TRG_128 0x80 |
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| 183 | |
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| 184 | #define UART_FCTR 1 /* Feature Control Register */ |
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| 185 | #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ |
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| 186 | #define UART_FCTR_RTS_4DELAY 0x01 |
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| 187 | #define UART_FCTR_RTS_6DELAY 0x02 |
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| 188 | #define UART_FCTR_RTS_8DELAY 0x03 |
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| 189 | #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ |
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| 190 | #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ |
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| 191 | #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ |
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| 192 | #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ |
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| 193 | #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ |
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| 194 | #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ |
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| 195 | #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ |
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| 196 | #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ |
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| 197 | #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ |
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| 198 | |
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| 199 | /* |
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| 200 | * LCR=0xBF, FCTR[6]=1 |
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| 201 | */ |
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| 202 | #define UART_EMSR 7 /* Extended Mode Select Register */ |
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| 203 | #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ |
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| 204 | #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ |
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| 205 | |
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| 206 | /* |
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| 207 | * The Intel XScale on-chip UARTs define these bits |
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| 208 | */ |
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| 209 | #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ |
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| 210 | #define UART_IER_UUE 0x40 /* UART Unit Enable */ |
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| 211 | #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ |
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| 212 | #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ |
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| 213 | |
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| 214 | #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ |
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| 215 | |
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| 216 | #define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */ |
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| 217 | #define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */ |
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| 218 | #define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */ |
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| 219 | #define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */ |
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| 220 | |
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| 221 | |
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| 222 | |
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| 223 | |
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| 224 | /* |
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| 225 | * These register definitions are for the 16C950 |
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| 226 | */ |
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| 227 | #define UART_ASR 0x01 /* Additional Status Register */ |
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| 228 | #define UART_RFL 0x03 /* Receiver FIFO level */ |
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| 229 | #define UART_TFL 0x04 /* Transmitter FIFO level */ |
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| 230 | #define UART_ICR 0x05 /* Index Control Register */ |
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| 231 | |
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| 232 | /* The 16950 ICR registers */ |
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| 233 | #define UART_ACR 0x00 /* Additional Control Register */ |
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| 234 | #define UART_CPR 0x01 /* Clock Prescalar Register */ |
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| 235 | #define UART_TCR 0x02 /* Times Clock Register */ |
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| 236 | #define UART_CKS 0x03 /* Clock Select Register */ |
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| 237 | #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ |
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| 238 | #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ |
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| 239 | #define UART_FCL 0x06 /* Flow Control Level Lower */ |
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| 240 | #define UART_FCH 0x07 /* Flow Control Level Higher */ |
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| 241 | #define UART_ID1 0x08 /* ID #1 */ |
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| 242 | #define UART_ID2 0x09 /* ID #2 */ |
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| 243 | #define UART_ID3 0x0A /* ID #3 */ |
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| 244 | #define UART_REV 0x0B /* Revision */ |
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| 245 | #define UART_CSR 0x0C /* Channel Software Reset */ |
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| 246 | #define UART_NMR 0x0D /* Nine-bit Mode Register */ |
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| 247 | #define UART_CTR 0xFF |
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| 248 | |
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| 249 | /* |
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| 250 | * The 16C950 Additional Control Reigster |
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| 251 | */ |
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| 252 | #define UART_ACR_RXDIS 0x01 /* Receiver disable */ |
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| 253 | #define UART_ACR_TXDIS 0x02 /* Receiver disable */ |
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| 254 | #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ |
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| 255 | #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ |
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| 256 | #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ |
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| 257 | #define UART_ACR_ASREN 0x80 /* Additional status enable */ |
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| 258 | |
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| 259 | |
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| 260 | |
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| 261 | /* |
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| 262 | * These definitions are for the RSA-DV II/S card, from |
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| 263 | * |
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| 264 | * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> |
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| 265 | */ |
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| 266 | |
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| 267 | #define UART_RSA_BASE (-8) |
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| 268 | |
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| 269 | #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ |
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| 270 | |
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| 271 | #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ |
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| 272 | #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ |
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| 273 | #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ |
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| 274 | #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ |
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| 275 | |
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| 276 | #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ |
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| 277 | |
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| 278 | #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ |
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| 279 | #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ |
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| 280 | #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ |
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| 281 | #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ |
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| 282 | #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ |
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| 283 | |
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| 284 | #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ |
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| 285 | |
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| 286 | #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ |
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| 287 | #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ |
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| 288 | #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ |
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| 289 | #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ |
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| 290 | #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ |
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| 291 | #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ |
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| 292 | #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ |
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| 293 | #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ |
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| 294 | |
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| 295 | #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ |
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| 296 | |
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| 297 | #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ |
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| 298 | |
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| 299 | #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ |
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| 300 | |
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| 301 | #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ |
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| 302 | |
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| 303 | /* |
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| 304 | * The RSA DSV/II board has two fixed clock frequencies. One is the |
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| 305 | * standard rate, and the other is 8 times faster. |
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| 306 | */ |
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| 307 | #define SERIAL_RSA_BAUD_BASE (921600) |
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| 308 | #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) |
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| 309 | |
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| 310 | /* |
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| 311 | * Extra serial register definitions for the internal UARTs |
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| 312 | * in TI OMAP processors. |
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| 313 | */ |
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| 314 | #define UART_OMAP_MDR1 0x08 /* Mode definition register */ |
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| 315 | #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ |
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| 316 | #define UART_OMAP_SCR 0x10 /* Supplementary control register */ |
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| 317 | #define UART_OMAP_SSR 0x11 /* Supplementary status register */ |
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| 318 | #define UART_OMAP_EBLR 0x12 /* BOF length register */ |
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| 319 | #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ |
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| 320 | #define UART_OMAP_MVER 0x14 /* Module version register */ |
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| 321 | #define UART_OMAP_SYSC 0x15 /* System configuration register */ |
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| 322 | #define UART_OMAP_SYSS 0x16 /* System status register */ |
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| 323 | |
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| 324 | #endif /* _LINUX_SERIAL_REG_H */ |
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| 325 | |
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