| 1 | /* |
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| 2 | * Hardware info about DECstation DS2100/3100 systems (otherwise known as |
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| 3 | * pmin/pmax or KN01). |
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| 4 | * |
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| 5 | * This file is subject to the terms and conditions of the GNU General Public |
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| 6 | * License. See the file "COPYING" in the main directory of this archive |
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| 7 | * for more details. |
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| 8 | * |
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| 9 | * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions |
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| 10 | * are by courtesy of Chris Fraser. |
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| 11 | * Copyright (C) 2002, 2003 Maciej W. Rozycki |
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| 12 | */ |
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| 13 | #ifndef __ASM_MIPS_DEC_KN01_H |
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| 14 | #define __ASM_MIPS_DEC_KN01_H |
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| 15 | |
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| 16 | #include <asm/addrspace.h> |
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| 17 | |
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| 18 | #define KN01_SLOT_BASE KSEG1ADDR(0x10000000) |
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| 19 | #define KN01_SLOT_SIZE 0x01000000 |
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| 20 | |
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| 21 | /* |
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| 22 | * Address ranges for devices. |
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| 23 | */ |
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| 24 | #define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */ |
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| 25 | #define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */ |
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| 26 | #define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */ |
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| 27 | #define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */ |
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| 28 | #define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */ |
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| 29 | #define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */ |
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| 30 | #define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */ |
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| 31 | #define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */ |
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| 32 | #define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */ |
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| 33 | #define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */ |
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| 34 | #define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */ |
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| 35 | #define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */ |
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| 36 | #define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */ |
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| 37 | #define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */ |
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| 38 | #define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */ |
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| 39 | #define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */ |
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| 40 | #define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */ |
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| 41 | |
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| 42 | |
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| 43 | /* |
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| 44 | * Some port addresses... |
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| 45 | */ |
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| 46 | #define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */ |
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| 47 | #define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */ |
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| 48 | #define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */ |
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| 49 | |
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| 50 | |
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| 51 | /* |
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| 52 | * Frame buffer memory address. |
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| 53 | */ |
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| 54 | #define KN01_VFB_MEM KSEG1ADDR(0x0fc00000) |
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| 55 | |
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| 56 | /* |
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| 57 | * CPU interrupt bits. |
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| 58 | */ |
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| 59 | #define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */ |
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| 60 | #define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */ |
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| 61 | #define KN01_CPU_INR_RTC 5 /* DS1287 RTC */ |
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| 62 | #define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */ |
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| 63 | #define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ |
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| 64 | #define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */ |
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| 65 | |
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| 66 | |
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| 67 | /* |
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| 68 | * System Control & Status Register bits. |
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| 69 | */ |
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| 70 | #define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ |
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| 71 | #define KN01_CSR_STATUS (1<<14) /* self-test result status output */ |
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| 72 | #define KN01_CSR_PARDIS (1<<13) /* parity error disable */ |
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| 73 | #define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ |
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| 74 | #define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ |
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| 75 | #define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ |
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| 76 | #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ |
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| 77 | #define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ |
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| 78 | #define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ |
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| 79 | #define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */ |
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| 80 | #define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ |
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| 81 | #define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ |
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| 82 | |
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| 83 | #endif /* __ASM_MIPS_DEC_KN01_H */ |
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