| 1 | /* |
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| 2 | * Hardware info about DECstation 5000/200 systems (otherwise known as |
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| 3 | * 3max or KN02). |
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| 4 | * |
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| 5 | * This file is subject to the terms and conditions of the GNU General Public |
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| 6 | * License. See the file "COPYING" in the main directory of this archive |
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| 7 | * for more details. |
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| 8 | * |
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| 9 | * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions |
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| 10 | * are by courtesy of Chris Fraser. |
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| 11 | * Copyright (C) 2002, 2003 Maciej W. Rozycki |
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| 12 | */ |
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| 13 | #ifndef __ASM_MIPS_DEC_KN02_H |
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| 14 | #define __ASM_MIPS_DEC_KN02_H |
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| 15 | |
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| 16 | #ifndef __ASSEMBLY__ |
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| 17 | #include <linux/types.h> |
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| 18 | #endif |
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| 19 | |
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| 20 | #include <asm/addrspace.h> |
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| 21 | #include <asm/dec/ecc.h> |
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| 22 | |
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| 23 | |
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| 24 | #define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000) |
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| 25 | #define KN02_SLOT_SIZE 0x00080000 |
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| 26 | |
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| 27 | /* |
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| 28 | * Address ranges decoded by the "system slot" logic for onboard devices. |
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| 29 | */ |
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| 30 | #define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */ |
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| 31 | #define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */ |
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| 32 | #define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */ |
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| 33 | #define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */ |
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| 34 | #define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */ |
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| 35 | #define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */ |
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| 36 | #define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */ |
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| 37 | #define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */ |
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| 38 | |
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| 39 | |
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| 40 | /* |
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| 41 | * Some port addresses... |
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| 42 | */ |
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| 43 | #define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */ |
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| 44 | #define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */ |
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| 45 | #define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */ |
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| 46 | |
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| 47 | |
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| 48 | /* |
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| 49 | * System Control & Status Register bits. |
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| 50 | */ |
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| 51 | #define KN02_CSR_RES_28 (0xf<<28) /* unused */ |
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| 52 | #define KN02_CSR_PSU (1<<27) /* power supply unit warning */ |
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| 53 | #define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ |
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| 54 | #define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ |
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| 55 | #define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ |
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| 56 | #define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ |
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| 57 | #define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ |
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| 58 | #define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ |
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| 59 | #define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ |
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| 60 | #define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */ |
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| 61 | #define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */ |
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| 62 | #define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ |
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| 63 | #define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ |
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| 64 | #define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ |
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| 65 | #define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ |
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| 66 | #define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ |
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| 67 | |
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| 68 | |
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| 69 | /* |
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| 70 | * CPU interrupt bits. |
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| 71 | */ |
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| 72 | #define KN02_CPU_INR_RES_6 6 /* unused */ |
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| 73 | #define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ |
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| 74 | #define KN02_CPU_INR_RES_4 4 /* unused */ |
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| 75 | #define KN02_CPU_INR_RTC 3 /* DS1287 RTC */ |
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| 76 | #define KN02_CPU_INR_CASCADE 2 /* CSR cascade */ |
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| 77 | |
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| 78 | /* |
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| 79 | * CSR interrupt bits. |
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| 80 | */ |
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| 81 | #define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */ |
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| 82 | #define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */ |
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| 83 | #define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */ |
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| 84 | #define KN02_CSR_INR_RES_4 4 /* unused */ |
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| 85 | #define KN02_CSR_INR_RES_3 3 /* unused */ |
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| 86 | #define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */ |
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| 87 | #define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */ |
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| 88 | #define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */ |
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| 89 | |
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| 90 | |
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| 91 | #define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */ |
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| 92 | #define KN02_IRQ_LINES 8 /* number of CSR interrupts */ |
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| 93 | |
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| 94 | #define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE) |
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| 95 | #define KN02_IRQ_MASK(n) (1 << (n)) |
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| 96 | #define KN02_IRQ_ALL 0xff |
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| 97 | |
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| 98 | |
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| 99 | #ifndef __ASSEMBLY__ |
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| 100 | extern __u32 cached_kn02_csr; |
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| 101 | extern spinlock_t kn02_lock; |
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| 102 | extern void init_kn02_irqs(int base); |
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| 103 | #endif |
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| 104 | |
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| 105 | #endif /* __ASM_MIPS_DEC_KN02_H */ |
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