| 1 | /* |
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| 2 | * linux/include/asm/dma.h: Defines for using and allocating dma channels. |
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| 3 | * Written by Hennus Bergman, 1992. |
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| 4 | * High DMA channel support & info by Hannu Savolainen |
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| 5 | * and John Boyd, Nov. 1992. |
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| 6 | * |
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| 7 | * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards |
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| 8 | * and can only be used for expansion cards. Onboard DMA controllers, such |
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| 9 | * as the R4030 on Jazz boards behave totally different! |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _ASM_DMA_H |
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| 13 | #define _ASM_DMA_H |
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| 14 | |
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| 15 | #include <asm/io.h> /* need byte IO */ |
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| 16 | #include <linux/delay.h> |
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| 17 | #include <asm/system.h> |
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| 18 | |
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| 19 | |
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| 20 | #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER |
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| 21 | #define dma_outb outb_p |
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| 22 | #else |
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| 23 | #define dma_outb outb |
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| 24 | #endif |
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| 25 | |
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| 26 | #define dma_inb inb |
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| 27 | |
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| 28 | /* |
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| 29 | * NOTES about DMA transfers: |
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| 30 | * |
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| 31 | * controller 1: channels 0-3, byte operations, ports 00-1F |
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| 32 | * controller 2: channels 4-7, word operations, ports C0-DF |
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| 33 | * |
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| 34 | * - ALL registers are 8 bits only, regardless of transfer size |
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| 35 | * - channel 4 is not used - cascades 1 into 2. |
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| 36 | * - channels 0-3 are byte - addresses/counts are for physical bytes |
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| 37 | * - channels 5-7 are word - addresses/counts are for physical words |
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| 38 | * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries |
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| 39 | * - transfer count loaded to registers is 1 less than actual count |
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| 40 | * - controller 2 offsets are all even (2x offsets for controller 1) |
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| 41 | * - page registers for 5-7 don't use data bit 0, represent 128K pages |
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| 42 | * - page registers for 0-3 use bit 0, represent 64K pages |
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| 43 | * |
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| 44 | * DMA transfers are limited to the lower 16MB of _physical_ memory. |
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| 45 | * Note that addresses loaded into registers must be _physical_ addresses, |
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| 46 | * not logical addresses (which may differ if paging is active). |
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| 47 | * |
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| 48 | * Address mapping for channels 0-3: |
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| 49 | * |
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| 50 | * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) |
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| 51 | * | ... | | ... | | ... | |
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| 52 | * | ... | | ... | | ... | |
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| 53 | * | ... | | ... | | ... | |
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| 54 | * P7 ... P0 A7 ... A0 A7 ... A0 |
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| 55 | * | Page | Addr MSB | Addr LSB | (DMA registers) |
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| 56 | * |
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| 57 | * Address mapping for channels 5-7: |
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| 58 | * |
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| 59 | * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) |
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| 60 | * | ... | \ \ ... \ \ \ ... \ \ |
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| 61 | * | ... | \ \ ... \ \ \ ... \ (not used) |
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| 62 | * | ... | \ \ ... \ \ \ ... \ |
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| 63 | * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 |
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| 64 | * | Page | Addr MSB | Addr LSB | (DMA registers) |
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| 65 | * |
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| 66 | * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses |
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| 67 | * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at |
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| 68 | * the hardware level, so odd-byte transfers aren't possible). |
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| 69 | * |
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| 70 | * Transfer count (_not # bytes_) is limited to 64K, represented as actual |
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| 71 | * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, |
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| 72 | * and up to 128K bytes may be transferred on channels 5-7 in one operation. |
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| 73 | * |
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| 74 | */ |
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| 75 | |
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| 76 | #define MAX_DMA_CHANNELS 8 |
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| 77 | |
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| 78 | /* |
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| 79 | * The maximum address in KSEG0 that we can perform a DMA transfer to on this |
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| 80 | * platform. This describes only the PC style part of the DMA logic like on |
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| 81 | * Deskstations or Acer PICA but not the much more versatile DMA logic used |
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| 82 | * for the local devices on Acer PICA or Magnums. |
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| 83 | */ |
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| 84 | #ifdef CONFIG_SGI_IP22 |
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| 85 | /* Horrible hack to have a correct DMA window on IP22 */ |
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| 86 | #include <asm/sgi/mc.h> |
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| 87 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000) |
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| 88 | #else |
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| 89 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) |
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| 90 | #endif |
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| 91 | |
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| 92 | /* 8237 DMA controllers */ |
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| 93 | #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
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| 94 | #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ |
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| 95 | |
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| 96 | /* DMA controller registers */ |
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| 97 | #define DMA1_CMD_REG 0x08 /* command register (w) */ |
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| 98 | #define DMA1_STAT_REG 0x08 /* status register (r) */ |
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| 99 | #define DMA1_REQ_REG 0x09 /* request register (w) */ |
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| 100 | #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ |
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| 101 | #define DMA1_MODE_REG 0x0B /* mode register (w) */ |
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| 102 | #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
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| 103 | #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ |
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| 104 | #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
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| 105 | #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ |
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| 106 | #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ |
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| 107 | |
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| 108 | #define DMA2_CMD_REG 0xD0 /* command register (w) */ |
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| 109 | #define DMA2_STAT_REG 0xD0 /* status register (r) */ |
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| 110 | #define DMA2_REQ_REG 0xD2 /* request register (w) */ |
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| 111 | #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
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| 112 | #define DMA2_MODE_REG 0xD6 /* mode register (w) */ |
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| 113 | #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
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| 114 | #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ |
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| 115 | #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
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| 116 | #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ |
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| 117 | #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ |
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| 118 | |
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| 119 | #define DMA_ADDR_0 0x00 /* DMA address registers */ |
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| 120 | #define DMA_ADDR_1 0x02 |
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| 121 | #define DMA_ADDR_2 0x04 |
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| 122 | #define DMA_ADDR_3 0x06 |
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| 123 | #define DMA_ADDR_4 0xC0 |
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| 124 | #define DMA_ADDR_5 0xC4 |
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| 125 | #define DMA_ADDR_6 0xC8 |
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| 126 | #define DMA_ADDR_7 0xCC |
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| 127 | |
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| 128 | #define DMA_CNT_0 0x01 /* DMA count registers */ |
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| 129 | #define DMA_CNT_1 0x03 |
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| 130 | #define DMA_CNT_2 0x05 |
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| 131 | #define DMA_CNT_3 0x07 |
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| 132 | #define DMA_CNT_4 0xC2 |
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| 133 | #define DMA_CNT_5 0xC6 |
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| 134 | #define DMA_CNT_6 0xCA |
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| 135 | #define DMA_CNT_7 0xCE |
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| 136 | |
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| 137 | #define DMA_PAGE_0 0x87 /* DMA page registers */ |
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| 138 | #define DMA_PAGE_1 0x83 |
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| 139 | #define DMA_PAGE_2 0x81 |
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| 140 | #define DMA_PAGE_3 0x82 |
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| 141 | #define DMA_PAGE_5 0x8B |
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| 142 | #define DMA_PAGE_6 0x89 |
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| 143 | #define DMA_PAGE_7 0x8A |
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| 144 | |
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| 145 | #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
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| 146 | #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
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| 147 | #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
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| 148 | |
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| 149 | #define DMA_AUTOINIT 0x10 |
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| 150 | |
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| 151 | extern spinlock_t dma_spin_lock; |
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| 152 | |
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| 153 | static __inline__ unsigned long claim_dma_lock(void) |
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| 154 | { |
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| 155 | unsigned long flags; |
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| 156 | spin_lock_irqsave(&dma_spin_lock, flags); |
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| 157 | return flags; |
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| 158 | } |
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| 159 | |
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| 160 | static __inline__ void release_dma_lock(unsigned long flags) |
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| 161 | { |
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| 162 | spin_unlock_irqrestore(&dma_spin_lock, flags); |
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| 163 | } |
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| 164 | |
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| 165 | /* enable/disable a specific DMA channel */ |
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| 166 | static __inline__ void enable_dma(unsigned int dmanr) |
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| 167 | { |
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| 168 | if (dmanr<=3) |
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| 169 | dma_outb(dmanr, DMA1_MASK_REG); |
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| 170 | else |
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| 171 | dma_outb(dmanr & 3, DMA2_MASK_REG); |
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| 172 | } |
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| 173 | |
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| 174 | static __inline__ void disable_dma(unsigned int dmanr) |
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| 175 | { |
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| 176 | if (dmanr<=3) |
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| 177 | dma_outb(dmanr | 4, DMA1_MASK_REG); |
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| 178 | else |
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| 179 | dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); |
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| 180 | } |
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| 181 | |
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| 182 | /* Clear the 'DMA Pointer Flip Flop'. |
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| 183 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. |
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| 184 | * Use this once to initialize the FF to a known state. |
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| 185 | * After that, keep track of it. :-) |
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| 186 | * --- In order to do that, the DMA routines below should --- |
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| 187 | * --- only be used while holding the DMA lock ! --- |
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| 188 | */ |
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| 189 | static __inline__ void clear_dma_ff(unsigned int dmanr) |
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| 190 | { |
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| 191 | if (dmanr<=3) |
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| 192 | dma_outb(0, DMA1_CLEAR_FF_REG); |
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| 193 | else |
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| 194 | dma_outb(0, DMA2_CLEAR_FF_REG); |
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| 195 | } |
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| 196 | |
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| 197 | /* set mode (above) for a specific DMA channel */ |
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| 198 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) |
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| 199 | { |
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| 200 | if (dmanr<=3) |
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| 201 | dma_outb(mode | dmanr, DMA1_MODE_REG); |
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| 202 | else |
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| 203 | dma_outb(mode | (dmanr&3), DMA2_MODE_REG); |
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| 204 | } |
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| 205 | |
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| 206 | /* Set only the page register bits of the transfer address. |
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| 207 | * This is used for successive transfers when we know the contents of |
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| 208 | * the lower 16 bits of the DMA current address register, but a 64k boundary |
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| 209 | * may have been crossed. |
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| 210 | */ |
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| 211 | static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) |
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| 212 | { |
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| 213 | switch(dmanr) { |
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| 214 | case 0: |
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| 215 | dma_outb(pagenr, DMA_PAGE_0); |
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| 216 | break; |
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| 217 | case 1: |
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| 218 | dma_outb(pagenr, DMA_PAGE_1); |
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| 219 | break; |
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| 220 | case 2: |
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| 221 | dma_outb(pagenr, DMA_PAGE_2); |
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| 222 | break; |
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| 223 | case 3: |
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| 224 | dma_outb(pagenr, DMA_PAGE_3); |
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| 225 | break; |
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| 226 | case 5: |
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| 227 | dma_outb(pagenr & 0xfe, DMA_PAGE_5); |
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| 228 | break; |
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| 229 | case 6: |
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| 230 | dma_outb(pagenr & 0xfe, DMA_PAGE_6); |
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| 231 | break; |
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| 232 | case 7: |
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| 233 | dma_outb(pagenr & 0xfe, DMA_PAGE_7); |
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| 234 | break; |
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| 235 | } |
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| 236 | } |
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| 237 | |
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| 238 | |
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| 239 | /* Set transfer address & page bits for specific DMA channel. |
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| 240 | * Assumes dma flipflop is clear. |
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| 241 | */ |
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| 242 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) |
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| 243 | { |
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| 244 | set_dma_page(dmanr, a>>16); |
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| 245 | if (dmanr <= 3) { |
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| 246 | dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); |
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| 247 | dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); |
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| 248 | } else { |
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| 249 | dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); |
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| 250 | dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); |
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| 251 | } |
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| 252 | } |
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| 253 | |
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| 254 | |
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| 255 | /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for |
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| 256 | * a specific DMA channel. |
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| 257 | * You must ensure the parameters are valid. |
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| 258 | * NOTE: from a manual: "the number of transfers is one more |
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| 259 | * than the initial word count"! This is taken into account. |
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| 260 | * Assumes dma flip-flop is clear. |
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| 261 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. |
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| 262 | */ |
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| 263 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) |
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| 264 | { |
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| 265 | count--; |
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| 266 | if (dmanr <= 3) { |
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| 267 | dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); |
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| 268 | dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); |
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| 269 | } else { |
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| 270 | dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); |
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| 271 | dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); |
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| 272 | } |
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| 273 | } |
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| 274 | |
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| 275 | |
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| 276 | /* Get DMA residue count. After a DMA transfer, this |
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| 277 | * should return zero. Reading this while a DMA transfer is |
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| 278 | * still in progress will return unpredictable results. |
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| 279 | * If called before the channel has been used, it may return 1. |
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| 280 | * Otherwise, it returns the number of _bytes_ left to transfer. |
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| 281 | * |
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| 282 | * Assumes DMA flip-flop is clear. |
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| 283 | */ |
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| 284 | static __inline__ int get_dma_residue(unsigned int dmanr) |
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| 285 | { |
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| 286 | unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE |
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| 287 | : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; |
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| 288 | |
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| 289 | /* using short to get 16-bit wrap around */ |
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| 290 | unsigned short count; |
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| 291 | |
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| 292 | count = 1 + dma_inb(io_port); |
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| 293 | count += dma_inb(io_port) << 8; |
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| 294 | |
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| 295 | return (dmanr<=3)? count : (count<<1); |
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| 296 | } |
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| 297 | |
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| 298 | |
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| 299 | /* These are in kernel/dma.c: */ |
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| 300 | extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ |
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| 301 | extern void free_dma(unsigned int dmanr); /* release it again */ |
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| 302 | |
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| 303 | /* From PCI */ |
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| 304 | |
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| 305 | #ifdef CONFIG_PCI |
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| 306 | extern int isa_dma_bridge_buggy; |
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| 307 | #else |
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| 308 | #define isa_dma_bridge_buggy (0) |
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| 309 | #endif |
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| 310 | |
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| 311 | #endif /* _ASM_DMA_H */ |
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