| 1 | /* |
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| 2 | * |
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| 3 | */ |
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| 4 | #ifndef _MIPS_EV96100_H |
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| 5 | #define _MIPS_EV96100_H |
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| 6 | |
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| 7 | #include <asm/addrspace.h> |
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| 8 | |
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| 9 | /* |
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| 10 | * GT64120 config space base address |
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| 11 | */ |
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| 12 | #define GT64120_BASE (KSEG1ADDR(0x14000000)) |
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| 13 | #define MIPS_GT_BASE GT64120_BASE |
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| 14 | |
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| 15 | /* |
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| 16 | * PCI Bus allocation |
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| 17 | */ |
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| 18 | #define GT_PCI_MEM_BASE 0x12000000UL |
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| 19 | #define GT_PCI_MEM_SIZE 0x02000000UL |
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| 20 | #define GT_PCI_IO_BASE 0x10000000UL |
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| 21 | #define GT_PCI_IO_SIZE 0x02000000UL |
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| 22 | #define GT_ISA_IO_BASE PCI_IO_BASE |
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| 23 | |
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| 24 | /* |
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| 25 | * Duart I/O ports. |
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| 26 | */ |
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| 27 | #define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) |
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| 28 | #define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) |
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| 29 | |
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| 30 | |
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| 31 | /* |
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| 32 | * EV96100 interrupt controller register base. |
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| 33 | */ |
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| 34 | #define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) |
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| 35 | |
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| 36 | /* |
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| 37 | * EV96100 UART register base. |
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| 38 | */ |
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| 39 | #define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR |
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| 40 | #define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR |
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| 41 | #define EV96100_BASE_BAUD ( 3686400 / 16 ) |
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| 42 | |
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| 43 | |
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| 44 | /* |
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| 45 | * Because of an error/peculiarity in the Galileo chip, we need to swap the |
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| 46 | * bytes when running bigendian. |
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| 47 | */ |
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| 48 | #define __GT_READ(ofs) \ |
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| 49 | (*(volatile __u32 *)(GT64120_BASE+(ofs))) |
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| 50 | #define __GT_WRITE(ofs, data) \ |
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| 51 | do { *(volatile __u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) |
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| 52 | #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) |
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| 53 | #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) |
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| 54 | |
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| 55 | #endif /* !(_MIPS_EV96100_H) */ |
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