source: svn/trunk/newcon3bcm2_21bu/toolchain/mipsel-linux-uclibc/include/asm/sgi/mc.h

Last change on this file was 2, checked in by jglee, 11 years ago

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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * mc.h: Definitions for SGI Memory Controller
7 *
8 * Copyright (C) 1996 David S. Miller
9 * Copyright (C) 1999 Ralf Baechle
10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 */
12
13#ifndef _SGI_MC_H
14#define _SGI_MC_H
15
16struct sgimc_regs {
17        __u32 _unused0;
18        volatile __u32 cpuctrl0;        /* CPU control register 0, readwrite */
19#define SGIMC_CCTRL0_REFS       0x0000000f /* REFS mask */
20#define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
21#define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
22#define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
23#define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
24#define SGIMC_CCTRL0_WDOG       0x00000100 /* Watchdog timer enable */
25#define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
26#define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
27#define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
28#define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
29#define SGIMC_CCTRL0_IENAB      0x00002000 /* Allow interrupts from MC */
30#define SGIMC_CCTRL0_ESNOOP     0x00004000 /* Snooping I/O enable */
31#define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
32#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33#define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
34#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
37#define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
38        __u32 _unused1;
39        volatile __u32 cpuctrl1;        /* CPU control register 1, readwrite */
40#define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
41#define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
42#define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
43#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
44#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
45#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
46#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
47
48        __u32 _unused2;
49        volatile __u32 watchdogt;       /* Watchdog reg rdonly, write clears */
50
51        __u32 _unused3;
52        volatile __u32 systemid;        /* MC system ID register, readonly */
53#define SGIMC_SYSID_MASKREV     0x0000000f /* Revision of MC controller */
54#define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
55
56        __u32 _unused4[3];
57        volatile __u32 divider; /* Divider reg for RPSS */
58
59        __u32 _unused5;
60        volatile __u32 eeprom;  /* EEPROM byte reg for r4k */
61#define SGIMC_EEPROM_PRE        0x00000001 /* eeprom chip PRE pin assertion */
62#define SGIMC_EEPROM_CSEL       0x00000002 /* Active high, eeprom chip select */
63#define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
64#define SGIMC_EEPROM_SDATAO     0x00000008 /* Serial EEPROM data-out */
65#define SGIMC_EEPROM_SDATAI     0x00000010 /* Serial EEPROM data-in */
66
67        __u32 _unused6[3];
68        volatile __u32 rcntpre; /* Preload refresh counter */
69
70        __u32 _unused7;
71        volatile __u32 rcounter;        /* Readonly refresh counter */
72
73        __u32 _unused8[13];
74        volatile __u32 giopar;  /* Parameter word for GIO64 */
75#define SGIMC_GIOPAR_HPC64      0x00000001 /* HPC talks to GIO using 64-bits */
76#define SGIMC_GIOPAR_GFX64      0x00000002 /* GFX talks to GIO using 64-bits */
77#define SGIMC_GIOPAR_EXP064     0x00000004 /* EXP(slot0) talks using 64-bits */
78#define SGIMC_GIOPAR_EXP164     0x00000008 /* EXP(slot1) talks using 64-bits */
79#define SGIMC_GIOPAR_EISA64     0x00000010 /* EISA bus talks 64-bits to GIO */
80#define SGIMC_GIOPAR_HPC264     0x00000020 /* 2nd HPX talks 64-bits to GIO */
81#define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
82#define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
83#define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
84#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
85#define SGIMC_GIOPAR_ONEBUS     0x00000400 /* Exists one GIO64 pipelined bus */
86#define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
87#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
88#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
89#define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
90#define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
91
92        __u32 _unused9;
93        volatile __u32 cputp;   /* CPU bus arb time period */
94
95        __u32 _unused10[3];
96        volatile __u32 lbursttp;        /* Time period for long bursts */
97
98        /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
99         * be the same size. The size encoding for supported SIMMs is bellow */
100        __u32 _unused11[9];
101        volatile __u32 mconfig0;        /* Memory config register zero */
102        __u32 _unused12;
103        volatile __u32 mconfig1;        /* Memory config register one */
104#define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
105#define SGIMC_MCONFIG_RMASK     0x00001f00 /* Ram config bitmask */
106#define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
107#define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
108
109        __u32 _unused13;
110        volatile __u32 cmacc;        /* Mem access config for CPU */
111        __u32 _unused14;
112        volatile __u32 gmacc;        /* Mem access config for GIO */
113
114        /* This define applies to both cmacc and gmacc registers above. */
115#define SGIMC_MACC_ALIASBIG     0x20000000 /* 512MB home for alias */
116
117        /* Error address/status regs from GIO and CPU perspectives. */
118        __u32 _unused15;
119        volatile __u32 cerr;    /* Error address reg for CPU */
120        __u32 _unused16;
121        volatile __u32 cstat;   /* Status reg for CPU */
122#define SGIMC_CSTAT_RD          0x00000100 /* read parity error */
123#define SGIMC_CSTAT_PAR         0x00000200 /* CPU parity error */
124#define SGIMC_CSTAT_ADDR        0x00000400 /* memory bus error bad addr */
125#define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
126#define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
127#define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
128#define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
129#define SGIMC_CSTAT_RD_PAR      (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
130
131        __u32 _unused17;
132        volatile __u32 gerr;    /* Error address reg for GIO */
133        __u32 _unused18;
134        volatile __u32 gstat;   /* Status reg for GIO */
135#define SGIMC_GSTAT_RD          0x00000100 /* read parity error */
136#define SGIMC_GSTAT_WR          0x00000200 /* write parity error */
137#define SGIMC_GSTAT_TIME        0x00000400 /* GIO bus timed out */
138#define SGIMC_GSTAT_PROM        0x00000800 /* write to PROM when PROM_EN not set */
139#define SGIMC_GSTAT_ADDR        0x00001000 /* parity error on addr cycle */
140#define SGIMC_GSTAT_BC          0x00002000 /* parity error on byte count cycle */
141#define SGIMC_GSTAT_PIO_RD      0x00004000 /* read data parity on pio */
142#define SGIMC_GSTAT_PIO_WR      0x00008000 /* write data parity on pio */
143
144        /* Special hard bus locking registers. */
145        __u32 _unused19;
146        volatile __u32 syssembit;               /* Uni-bit system semaphore */
147        __u32 _unused20;
148        volatile __u32 mlock;           /* Global GIO memory access lock */
149        __u32 _unused21;
150        volatile __u32 elock;           /* Locks EISA from GIO accesses */
151
152        /* GIO dma control registers. */
153        __u32 _unused22[15];
154        volatile __u32 gio_dma_trans;   /* DMA mask to translation GIO addrs */
155        __u32 _unused23;
156        volatile __u32 gio_dma_sbits;   /* DMA GIO addr substitution bits */
157        __u32 _unused24;
158        volatile __u32 dma_intr_cause;  /* DMA IRQ cause indicator bits */
159        __u32 _unused25;
160        volatile __u32 dma_ctrl;                /* Main DMA control reg */
161
162        /* DMA TLB entry 0 */
163        __u32 _unused26[5];
164        volatile __u32 dtlb_hi0;
165        __u32 _unused27;
166        volatile __u32 dtlb_lo0;
167
168        /* DMA TLB entry 1 */
169        __u32 _unused28;
170        volatile __u32 dtlb_hi1;
171        __u32 _unused29;
172        volatile __u32 dtlb_lo1;
173
174        /* DMA TLB entry 2 */
175        __u32 _unused30;
176        volatile __u32 dtlb_hi2;
177        __u32 _unused31;
178        volatile __u32 dtlb_lo2;
179
180        /* DMA TLB entry 3 */
181        __u32 _unused32;
182        volatile __u32 dtlb_hi3;
183        __u32 _unused33;
184        volatile __u32 dtlb_lo3;
185       
186        __u32 _unused34[0x0392];
187       
188        __u32 _unused35;
189        volatile __u32 rpsscounter;     /* Chirps at 100ns */
190
191        __u32 _unused36[0x1000/4-2*4];
192       
193        __u32 _unused37;
194        volatile __u32 maddronly;               /* Address DMA goes at */
195        __u32 _unused38;
196        volatile __u32 maddrpdeflts;    /* Same as above, plus set defaults */
197        __u32 _unused39;
198        volatile __u32 dmasz;           /* DMA count */
199        __u32 _unused40;
200        volatile __u32 ssize;           /* DMA stride size */
201        __u32 _unused41;
202        volatile __u32 gmaddronly;      /* Set GIO DMA but don't start trans */
203        __u32 _unused42;
204        volatile __u32 dmaddnpgo;               /* Set GIO DMA addr + start transfer */
205        __u32 _unused43;
206        volatile __u32 dmamode;         /* DMA mode config bit settings */
207        __u32 _unused44;
208        volatile __u32 dmaccount;               /* Zoom and byte count for DMA */
209        __u32 _unused45;
210        volatile __u32 dmastart;                /* Pedal to the metal. */
211        __u32 _unused46;
212        volatile __u32 dmarunning;      /* DMA op is in progress */
213        __u32 _unused47;
214        volatile __u32 maddrdefstart;   /* Set dma addr, defaults, and kick it */
215};
216
217extern struct sgimc_regs *sgimc;
218#define SGIMC_BASE              0x1fa00000      /* physical */
219
220/* Base location of the two ram banks found in IP2[0268] machines. */
221#define SGIMC_SEG0_BADDR        0x08000000
222#define SGIMC_SEG1_BADDR        0x20000000
223
224/* Maximum size of the above banks are per machine. */
225#define SGIMC_SEG0_SIZE_ALL             0x10000000 /* 256MB */
226#define SGIMC_SEG1_SIZE_IP20_IP22       0x08000000 /* 128MB */
227#define SGIMC_SEG1_SIZE_IP26_IP28       0x20000000 /* 512MB */
228
229extern void sgimc_init(void);
230
231#endif /* _SGI_MC_H */
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