| 1 | /* ********************************************************************* |
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| 2 | * SB1250 Board Support Package |
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| 3 | * |
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| 4 | * SCD Constants and Macros File: sb1250_scd.h |
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| 5 | * |
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| 6 | * This module contains constants and macros useful for |
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| 7 | * manipulating the System Control and Debug module on the 1250. |
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| 8 | * |
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| 9 | * SB1250 specification level: User's manual 1/02/02 |
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| 10 | * |
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| 11 | * Author: Mitch Lichtenberg |
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| 12 | * |
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| 13 | ********************************************************************* |
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| 14 | * |
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| 15 | * Copyright 2000,2001,2002,2003 |
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| 16 | * Broadcom Corporation. All rights reserved. |
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| 17 | * |
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| 18 | * This program is free software; you can redistribute it and/or |
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| 19 | * modify it under the terms of the GNU General Public License as |
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| 20 | * published by the Free Software Foundation; either version 2 of |
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| 21 | * the License, or (at your option) any later version. |
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| 22 | * |
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| 23 | * This program is distributed in the hope that it will be useful, |
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| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 26 | * GNU General Public License for more details. |
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| 27 | * |
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| 28 | * You should have received a copy of the GNU General Public License |
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| 29 | * along with this program; if not, write to the Free Software |
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| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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| 31 | * MA 02111-1307 USA |
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| 32 | ********************************************************************* */ |
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| 33 | |
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| 34 | #ifndef _SB1250_SCD_H |
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| 35 | #define _SB1250_SCD_H |
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| 36 | |
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| 37 | #include "sb1250_defs.h" |
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| 38 | |
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| 39 | /* ********************************************************************* |
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| 40 | * System control/debug registers |
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| 41 | ********************************************************************* */ |
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| 42 | |
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| 43 | /* |
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| 44 | * System Revision Register (Table 4-1) |
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| 45 | */ |
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| 46 | |
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| 47 | #define M_SYS_RESERVED _SB_MAKEMASK(8,0) |
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| 48 | |
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| 49 | #define S_SYS_REVISION _SB_MAKE64(8) |
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| 50 | #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) |
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| 51 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) |
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| 52 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) |
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| 53 | |
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| 54 | #if SIBYTE_HDR_FEATURE_CHIP(1250) |
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| 55 | #define K_SYS_REVISION_BCM1250_PASS1 1 |
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| 56 | #define K_SYS_REVISION_BCM1250_PASS2 3 |
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| 57 | #define K_SYS_REVISION_BCM1250_A10 11 |
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| 58 | #define K_SYS_REVISION_BCM1250_PASS2_2 16 |
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| 59 | #define K_SYS_REVISION_BCM1250_B2 17 |
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| 60 | #define K_SYS_REVISION_BCM1250_PASS3 32 |
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| 61 | #define K_SYS_REVISION_BCM1250_C1 33 |
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| 62 | |
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| 63 | /* XXX: discourage people from using these constants. */ |
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| 64 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 |
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| 65 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 |
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| 66 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 |
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| 67 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 |
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| 68 | #endif /* 1250 */ |
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| 69 | |
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| 70 | #if SIBYTE_HDR_FEATURE_CHIP(112x) |
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| 71 | #define K_SYS_REVISION_BCM112x_A1 32 |
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| 72 | #define K_SYS_REVISION_BCM112x_A2 33 |
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| 73 | #endif /* 112x */ |
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| 74 | |
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| 75 | /* XXX: discourage people from using these constants. */ |
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| 76 | #define S_SYS_PART _SB_MAKE64(16) |
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| 77 | #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) |
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| 78 | #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) |
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| 79 | #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) |
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| 80 | |
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| 81 | /* XXX: discourage people from using these constants. */ |
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| 82 | #define K_SYS_PART_SB1250 0x1250 |
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| 83 | #define K_SYS_PART_BCM1120 0x1121 |
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| 84 | #define K_SYS_PART_BCM1125 0x1123 |
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| 85 | #define K_SYS_PART_BCM1125H 0x1124 |
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| 86 | |
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| 87 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ |
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| 88 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) |
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| 89 | #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) |
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| 90 | #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) |
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| 91 | #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) |
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| 92 | |
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| 93 | #define K_SYS_SOC_TYPE_BCM1250 0x0 |
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| 94 | #define K_SYS_SOC_TYPE_BCM1120 0x1 |
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| 95 | #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ |
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| 96 | #define K_SYS_SOC_TYPE_BCM1125 0x3 |
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| 97 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 |
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| 98 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ |
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| 99 | |
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| 100 | /* |
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| 101 | * Calculate correct SOC type given a copy of system revision register. |
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| 102 | * |
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| 103 | * (For the assembler version, sysrev and dest may be the same register. |
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| 104 | * Also, it clobbers AT.) |
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| 105 | */ |
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| 106 | #ifdef __ASSEMBLER__ |
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| 107 | #define SYS_SOC_TYPE(dest, sysrev) \ |
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| 108 | .set push ; \ |
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| 109 | .set reorder ; \ |
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| 110 | dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ |
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| 111 | andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ |
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| 112 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ |
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| 113 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ |
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| 114 | b 992f ; \ |
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| 115 | 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ |
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| 116 | 992: \ |
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| 117 | .set pop |
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| 118 | #else |
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| 119 | #define SYS_SOC_TYPE(sysrev) \ |
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| 120 | ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ |
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| 121 | || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ |
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| 122 | ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) |
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| 123 | #endif |
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| 124 | |
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| 125 | #define S_SYS_WID _SB_MAKE64(32) |
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| 126 | #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) |
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| 127 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) |
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| 128 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) |
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| 129 | |
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| 130 | /* System Manufacturing Register |
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| 131 | * Register: SCD_SYSTEM_MANUF |
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| 132 | */ |
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| 133 | |
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| 134 | /* Wafer ID: bits 31:0 */ |
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| 135 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) |
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| 136 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) |
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| 137 | #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) |
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| 138 | #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) |
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| 139 | |
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| 140 | #define S_SYS_BIN _SB_MAKE64(32) |
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| 141 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) |
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| 142 | #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) |
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| 143 | #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) |
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| 144 | |
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| 145 | /* Wafer ID: bits 39:36 */ |
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| 146 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) |
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| 147 | #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) |
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| 148 | #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) |
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| 149 | #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) |
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| 150 | |
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| 151 | /* Wafer ID: bits 39:0 */ |
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| 152 | #define S_SYS_WAFERID_300 _SB_MAKE64(0) |
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| 153 | #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) |
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| 154 | #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) |
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| 155 | #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) |
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| 156 | |
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| 157 | #define S_SYS_XPOS _SB_MAKE64(40) |
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| 158 | #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) |
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| 159 | #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) |
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| 160 | #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) |
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| 161 | |
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| 162 | #define S_SYS_YPOS _SB_MAKE64(46) |
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| 163 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) |
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| 164 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) |
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| 165 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) |
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| 166 | |
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| 167 | /* |
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| 168 | * System Config Register (Table 4-2) |
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| 169 | * Register: SCD_SYSTEM_CFG |
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| 170 | */ |
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| 171 | |
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| 172 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) |
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| 173 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) |
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| 174 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) |
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| 175 | #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) |
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| 176 | |
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| 177 | #define S_SYS_PLL_DIV _SB_MAKE64(7) |
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| 178 | #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) |
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| 179 | #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) |
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| 180 | #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) |
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| 181 | |
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| 182 | #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) |
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| 183 | #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) |
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| 184 | #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) |
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| 185 | #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) |
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| 186 | #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) |
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| 187 | |
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| 188 | #define S_SYS_BOOT_MODE _SB_MAKE64(17) |
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| 189 | #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) |
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| 190 | #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) |
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| 191 | #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) |
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| 192 | #define K_SYS_BOOT_MODE_ROM32 0 |
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| 193 | #define K_SYS_BOOT_MODE_ROM8 1 |
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| 194 | #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 |
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| 195 | #define K_SYS_BOOT_MODE_SMBUS_BIG 3 |
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| 196 | |
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| 197 | #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) |
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| 198 | #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) |
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| 199 | #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) |
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| 200 | #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) |
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| 201 | #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) |
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| 202 | #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) |
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| 203 | #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) |
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| 204 | |
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| 205 | #define S_SYS_CONFIG 26 |
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| 206 | #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) |
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| 207 | #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) |
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| 208 | #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) |
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| 209 | |
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| 210 | /* The following bits are writeable by JTAG only. */ |
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| 211 | |
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| 212 | #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) |
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| 213 | #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) |
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| 214 | |
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| 215 | #define S_SYS_CLKCOUNT 34 |
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| 216 | #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) |
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| 217 | #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) |
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| 218 | #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) |
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| 219 | |
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| 220 | #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) |
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| 221 | |
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| 222 | #define S_SYS_PLL_IREF 43 |
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| 223 | #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) |
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| 224 | |
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| 225 | #define S_SYS_PLL_VCO 45 |
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| 226 | #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) |
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| 227 | |
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| 228 | #define S_SYS_PLL_VREG 47 |
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| 229 | #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) |
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| 230 | |
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| 231 | #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) |
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| 232 | #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) |
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| 233 | #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) |
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| 234 | #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) |
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| 235 | #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) |
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| 236 | |
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| 237 | /* End of bits writable by JTAG only. */ |
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| 238 | |
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| 239 | #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) |
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| 240 | #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) |
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| 241 | |
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| 242 | #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) |
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| 243 | #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) |
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| 244 | |
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| 245 | #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) |
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| 246 | #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) |
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| 247 | #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) |
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| 248 | |
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| 249 | #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) |
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| 250 | #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) |
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| 251 | |
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| 252 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 253 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) |
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| 254 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 255 | |
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| 256 | |
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| 257 | /* |
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| 258 | * Mailbox Registers (Table 4-3) |
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| 259 | * Registers: SCD_MBOX_CPU_x |
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| 260 | */ |
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| 261 | |
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| 262 | #define S_MBOX_INT_3 0 |
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| 263 | #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) |
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| 264 | #define S_MBOX_INT_2 16 |
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| 265 | #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) |
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| 266 | #define S_MBOX_INT_1 32 |
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| 267 | #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) |
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| 268 | #define S_MBOX_INT_0 48 |
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| 269 | #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) |
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| 270 | |
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| 271 | /* |
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| 272 | * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) |
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| 273 | * Registers: SCD_WDOG_INIT_CNT_x |
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| 274 | */ |
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| 275 | |
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| 276 | #define V_SCD_WDOG_FREQ 1000000 |
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| 277 | |
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| 278 | #define S_SCD_WDOG_INIT 0 |
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| 279 | #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) |
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| 280 | |
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| 281 | #define S_SCD_WDOG_CNT 0 |
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| 282 | #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) |
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| 283 | |
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| 284 | #define S_SCD_WDOG_ENABLE 0 |
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| 285 | #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) |
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| 286 | |
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| 287 | #define S_SCD_WDOG_RESET_TYPE 2 |
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| 288 | #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) |
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| 289 | #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) |
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| 290 | #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) |
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| 291 | |
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| 292 | #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ |
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| 293 | #define K_SCD_WDOG_RESET_SOFT 1 |
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| 294 | #define K_SCD_WDOG_RESET_CPU0 3 |
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| 295 | #define K_SCD_WDOG_RESET_CPU1 5 |
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| 296 | #define K_SCD_WDOG_RESET_BOTH_CPUS 7 |
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| 297 | |
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| 298 | /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ |
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| 299 | #if SIBYTE_HDR_FEATURE(1250, PASS3) |
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| 300 | #define S_SCD_WDOG_HAS_RESET 8 |
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| 301 | #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) |
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| 302 | #endif |
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| 303 | |
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| 304 | |
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| 305 | /* |
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| 306 | * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) |
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| 307 | */ |
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| 308 | |
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| 309 | #define V_SCD_TIMER_FREQ 1000000 |
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| 310 | |
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| 311 | #define S_SCD_TIMER_INIT 0 |
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| 312 | #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) |
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| 313 | #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) |
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| 314 | #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) |
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| 315 | |
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| 316 | #define S_SCD_TIMER_CNT 0 |
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| 317 | #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) |
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| 318 | #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) |
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| 319 | #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) |
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| 320 | |
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| 321 | #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) |
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| 322 | #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) |
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| 323 | #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE |
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| 324 | |
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| 325 | /* |
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| 326 | * System Performance Counters |
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| 327 | */ |
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| 328 | |
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| 329 | #define S_SPC_CFG_SRC0 0 |
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| 330 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) |
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| 331 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) |
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| 332 | #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) |
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| 333 | |
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| 334 | #define S_SPC_CFG_SRC1 8 |
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| 335 | #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) |
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| 336 | #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) |
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| 337 | #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) |
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| 338 | |
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| 339 | #define S_SPC_CFG_SRC2 16 |
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| 340 | #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) |
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| 341 | #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) |
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| 342 | #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) |
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| 343 | |
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| 344 | #define S_SPC_CFG_SRC3 24 |
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| 345 | #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) |
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| 346 | #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) |
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| 347 | #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) |
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| 348 | |
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| 349 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) |
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| 350 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) |
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| 351 | |
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| 352 | |
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| 353 | /* |
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| 354 | * Bus Watcher |
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| 355 | */ |
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| 356 | |
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| 357 | #define S_SCD_BERR_TID 8 |
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| 358 | #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) |
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| 359 | #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) |
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| 360 | #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) |
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| 361 | |
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| 362 | #define S_SCD_BERR_RID 18 |
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| 363 | #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) |
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| 364 | #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) |
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| 365 | #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) |
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| 366 | |
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| 367 | #define S_SCD_BERR_DCODE 22 |
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| 368 | #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) |
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| 369 | #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) |
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| 370 | #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) |
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| 371 | |
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| 372 | #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) |
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| 373 | |
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| 374 | |
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| 375 | #define S_SCD_L2ECC_CORR_D 0 |
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| 376 | #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) |
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| 377 | #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) |
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| 378 | #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) |
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| 379 | |
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| 380 | #define S_SCD_L2ECC_BAD_D 8 |
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| 381 | #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) |
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| 382 | #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) |
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| 383 | #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) |
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| 384 | |
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| 385 | #define S_SCD_L2ECC_CORR_T 16 |
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| 386 | #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) |
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| 387 | #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) |
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| 388 | #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) |
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| 389 | |
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| 390 | #define S_SCD_L2ECC_BAD_T 24 |
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| 391 | #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) |
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| 392 | #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) |
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| 393 | #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) |
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| 394 | |
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| 395 | #define S_SCD_MEM_ECC_CORR 0 |
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| 396 | #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) |
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| 397 | #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) |
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| 398 | #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) |
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| 399 | |
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| 400 | #define S_SCD_MEM_ECC_BAD 8 |
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| 401 | #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) |
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| 402 | #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) |
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| 403 | #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) |
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| 404 | |
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| 405 | #define S_SCD_MEM_BUSERR 16 |
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| 406 | #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) |
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| 407 | #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) |
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| 408 | #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) |
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| 409 | |
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| 410 | |
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| 411 | /* |
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| 412 | * Address Trap Registers |
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| 413 | */ |
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| 414 | |
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| 415 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) |
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| 416 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) |
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| 417 | |
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| 418 | #define S_ATRAP_CFG_CNT 0 |
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| 419 | #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) |
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| 420 | #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) |
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| 421 | #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) |
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| 422 | |
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| 423 | #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) |
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| 424 | #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) |
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| 425 | #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) |
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| 426 | #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) |
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| 427 | #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) |
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| 428 | |
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| 429 | #define S_ATRAP_CFG_AGENTID 8 |
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| 430 | #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) |
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| 431 | #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) |
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| 432 | #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) |
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| 433 | |
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| 434 | #define K_BUS_AGENT_CPU0 0 |
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| 435 | #define K_BUS_AGENT_CPU1 1 |
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| 436 | #define K_BUS_AGENT_IOB0 2 |
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| 437 | #define K_BUS_AGENT_IOB1 3 |
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| 438 | #define K_BUS_AGENT_SCD 4 |
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| 439 | #define K_BUS_AGENT_RESERVED 5 |
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| 440 | #define K_BUS_AGENT_L2C 6 |
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| 441 | #define K_BUS_AGENT_MC 7 |
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| 442 | |
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| 443 | #define S_ATRAP_CFG_CATTR 12 |
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| 444 | #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) |
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| 445 | #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) |
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| 446 | #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) |
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| 447 | |
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| 448 | #define K_ATRAP_CFG_CATTR_IGNORE 0 |
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| 449 | #define K_ATRAP_CFG_CATTR_UNC 1 |
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| 450 | #define K_ATRAP_CFG_CATTR_CACHEABLE 2 |
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| 451 | #define K_ATRAP_CFG_CATTR_NONCOH 3 |
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| 452 | #define K_ATRAP_CFG_CATTR_COHERENT 4 |
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| 453 | #define K_ATRAP_CFG_CATTR_NOTUNC 5 |
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| 454 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 |
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| 455 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 |
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| 456 | |
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| 457 | /* |
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| 458 | * Trace Buffer Config register |
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| 459 | */ |
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| 460 | |
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| 461 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) |
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| 462 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) |
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| 463 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) |
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| 464 | #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) |
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| 465 | #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) |
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| 466 | #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) |
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| 467 | #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) |
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| 468 | #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) |
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| 469 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 470 | #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) |
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| 471 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 472 | |
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| 473 | #define S_SCD_TRACE_CFG_CUR_ADDR 10 |
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| 474 | #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) |
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| 475 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) |
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| 476 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) |
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| 477 | |
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| 478 | /* |
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| 479 | * Trace Event registers |
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| 480 | */ |
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| 481 | |
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| 482 | #define S_SCD_TREVT_ADDR_MATCH 0 |
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| 483 | #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) |
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| 484 | #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) |
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| 485 | #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) |
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| 486 | |
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| 487 | #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) |
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| 488 | #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) |
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| 489 | #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) |
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| 490 | #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) |
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| 491 | #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) |
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| 492 | #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) |
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| 493 | #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) |
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| 494 | |
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| 495 | #define S_SCD_TREVT_REQID 12 |
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| 496 | #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) |
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| 497 | #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) |
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| 498 | #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) |
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| 499 | |
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| 500 | #define S_SCD_TREVT_RESPID 16 |
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| 501 | #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) |
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| 502 | #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) |
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| 503 | #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) |
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| 504 | |
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| 505 | #define S_SCD_TREVT_DATAID 20 |
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| 506 | #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) |
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| 507 | #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) |
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| 508 | #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) |
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| 509 | |
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| 510 | #define S_SCD_TREVT_COUNT 24 |
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| 511 | #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) |
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| 512 | #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) |
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| 513 | #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) |
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| 514 | |
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| 515 | /* |
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| 516 | * Trace Sequence registers |
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| 517 | */ |
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| 518 | |
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| 519 | #define S_SCD_TRSEQ_EVENT4 0 |
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| 520 | #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) |
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| 521 | #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) |
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| 522 | #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) |
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| 523 | |
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| 524 | #define S_SCD_TRSEQ_EVENT3 4 |
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| 525 | #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) |
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| 526 | #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) |
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| 527 | #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) |
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| 528 | |
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| 529 | #define S_SCD_TRSEQ_EVENT2 8 |
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| 530 | #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) |
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| 531 | #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) |
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| 532 | #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) |
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| 533 | |
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| 534 | #define S_SCD_TRSEQ_EVENT1 12 |
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| 535 | #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) |
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| 536 | #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) |
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| 537 | #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) |
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| 538 | |
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| 539 | #define K_SCD_TRSEQ_E0 0 |
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| 540 | #define K_SCD_TRSEQ_E1 1 |
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| 541 | #define K_SCD_TRSEQ_E2 2 |
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| 542 | #define K_SCD_TRSEQ_E3 3 |
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| 543 | #define K_SCD_TRSEQ_E0_E1 4 |
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| 544 | #define K_SCD_TRSEQ_E1_E2 5 |
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| 545 | #define K_SCD_TRSEQ_E2_E3 6 |
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| 546 | #define K_SCD_TRSEQ_E0_E1_E2 7 |
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| 547 | #define K_SCD_TRSEQ_E0_E1_E2_E3 8 |
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| 548 | #define K_SCD_TRSEQ_E0E1 9 |
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| 549 | #define K_SCD_TRSEQ_E0E1E2 10 |
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| 550 | #define K_SCD_TRSEQ_E0E1E2E3 11 |
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| 551 | #define K_SCD_TRSEQ_E0E1_E2 12 |
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| 552 | #define K_SCD_TRSEQ_E0E1_E2E3 13 |
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| 553 | #define K_SCD_TRSEQ_E0E1_E2_E3 14 |
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| 554 | #define K_SCD_TRSEQ_IGNORED 15 |
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| 555 | |
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| 556 | #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ |
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| 557 | V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ |
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| 558 | V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ |
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| 559 | V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) |
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| 560 | |
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| 561 | #define S_SCD_TRSEQ_FUNCTION 16 |
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| 562 | #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) |
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| 563 | #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) |
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| 564 | #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) |
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| 565 | |
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| 566 | #define K_SCD_TRSEQ_FUNC_NOP 0 |
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| 567 | #define K_SCD_TRSEQ_FUNC_START 1 |
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| 568 | #define K_SCD_TRSEQ_FUNC_STOP 2 |
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| 569 | #define K_SCD_TRSEQ_FUNC_FREEZE 3 |
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| 570 | |
|---|
| 571 | #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) |
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| 572 | #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) |
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| 573 | #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) |
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| 574 | #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) |
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| 575 | |
|---|
| 576 | #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) |
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| 577 | #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) |
|---|
| 578 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) |
|---|
| 579 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) |
|---|
| 580 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) |
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| 581 | |
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| 582 | #endif |
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