| 1 | /*****************************************************************************/ |
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| 2 | |
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| 3 | /* |
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| 4 | * cd1400.h -- cd1400 UART hardware info. |
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| 5 | * |
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| 6 | * Copyright (C) 1996-1998 Stallion Technologies |
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| 7 | * Copyright (C) 1994-1996 Greg Ungerer. |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or modify |
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| 10 | * it under the terms of the GNU General Public License as published by |
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| 11 | * the Free Software Foundation; either version 2 of the License, or |
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| 12 | * (at your option) any later version. |
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| 13 | * |
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| 14 | * This program is distributed in the hope that it will be useful, |
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| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 17 | * GNU General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with this program; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 22 | */ |
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| 23 | |
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| 24 | /*****************************************************************************/ |
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| 25 | #ifndef _CD1400_H |
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| 26 | #define _CD1400_H |
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| 27 | /*****************************************************************************/ |
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| 28 | |
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| 29 | /* |
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| 30 | * Define the number of async ports per cd1400 uart chip. |
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| 31 | */ |
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| 32 | #define CD1400_PORTS 4 |
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| 33 | |
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| 34 | /* |
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| 35 | * Define the cd1400 uarts internal FIFO sizes. |
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| 36 | */ |
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| 37 | #define CD1400_TXFIFOSIZE 12 |
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| 38 | #define CD1400_RXFIFOSIZE 12 |
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| 39 | |
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| 40 | /* |
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| 41 | * Local RX FIFO thresh hold level. Also define the RTS thresh hold |
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| 42 | * based on the RX thresh hold. |
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| 43 | */ |
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| 44 | #define FIFO_RXTHRESHOLD 6 |
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| 45 | #define FIFO_RTSTHRESHOLD 7 |
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| 46 | |
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| 47 | /*****************************************************************************/ |
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| 48 | |
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| 49 | /* |
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| 50 | * Define the cd1400 register addresses. These are all the valid |
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| 51 | * registers with the cd1400. Some are global, some virtual, some |
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| 52 | * per port. |
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| 53 | */ |
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| 54 | #define GFRCR 0x40 |
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| 55 | #define CAR 0x68 |
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| 56 | #define GCR 0x4b |
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| 57 | #define SVRR 0x67 |
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| 58 | #define RICR 0x44 |
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| 59 | #define TICR 0x45 |
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| 60 | #define MICR 0x46 |
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| 61 | #define RIR 0x6b |
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| 62 | #define TIR 0x6a |
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| 63 | #define MIR 0x69 |
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| 64 | #define PPR 0x7e |
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| 65 | |
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| 66 | #define RIVR 0x43 |
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| 67 | #define TIVR 0x42 |
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| 68 | #define MIVR 0x41 |
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| 69 | #define TDR 0x63 |
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| 70 | #define RDSR 0x62 |
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| 71 | #define MISR 0x4c |
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| 72 | #define EOSRR 0x60 |
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| 73 | |
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| 74 | #define LIVR 0x18 |
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| 75 | #define CCR 0x05 |
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| 76 | #define SRER 0x06 |
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| 77 | #define COR1 0x08 |
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| 78 | #define COR2 0x09 |
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| 79 | #define COR3 0x0a |
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| 80 | #define COR4 0x1e |
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| 81 | #define COR5 0x1f |
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| 82 | #define CCSR 0x0b |
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| 83 | #define RDCR 0x0e |
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| 84 | #define SCHR1 0x1a |
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| 85 | #define SCHR2 0x1b |
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| 86 | #define SCHR3 0x1c |
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| 87 | #define SCHR4 0x1d |
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| 88 | #define SCRL 0x22 |
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| 89 | #define SCRH 0x23 |
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| 90 | #define LNC 0x24 |
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| 91 | #define MCOR1 0x15 |
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| 92 | #define MCOR2 0x16 |
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| 93 | #define RTPR 0x21 |
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| 94 | #define MSVR1 0x6c |
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| 95 | #define MSVR2 0x6d |
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| 96 | #define PSVR 0x6f |
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| 97 | #define RBPR 0x78 |
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| 98 | #define RCOR 0x7c |
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| 99 | #define TBPR 0x72 |
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| 100 | #define TCOR 0x76 |
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| 101 | |
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| 102 | /*****************************************************************************/ |
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| 103 | |
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| 104 | /* |
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| 105 | * Define the set of baud rate clock divisors. |
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| 106 | */ |
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| 107 | #define CD1400_CLK0 8 |
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| 108 | #define CD1400_CLK1 32 |
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| 109 | #define CD1400_CLK2 128 |
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| 110 | #define CD1400_CLK3 512 |
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| 111 | #define CD1400_CLK4 2048 |
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| 112 | |
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| 113 | #define CD1400_NUMCLKS 5 |
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| 114 | |
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| 115 | /*****************************************************************************/ |
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| 116 | |
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| 117 | /* |
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| 118 | * Define the clock pre-scalar value to be a 5 ms clock. This should be |
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| 119 | * OK for now. It would probably be better to make it 10 ms, but we |
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| 120 | * can't fit that divisor into 8 bits! |
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| 121 | */ |
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| 122 | #define PPR_SCALAR 244 |
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| 123 | |
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| 124 | /*****************************************************************************/ |
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| 125 | |
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| 126 | /* |
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| 127 | * Define values used to set character size options. |
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| 128 | */ |
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| 129 | #define COR1_CHL5 0x00 |
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| 130 | #define COR1_CHL6 0x01 |
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| 131 | #define COR1_CHL7 0x02 |
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| 132 | #define COR1_CHL8 0x03 |
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| 133 | |
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| 134 | /* |
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| 135 | * Define values used to set the number of stop bits. |
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| 136 | */ |
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| 137 | #define COR1_STOP1 0x00 |
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| 138 | #define COR1_STOP15 0x04 |
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| 139 | #define COR1_STOP2 0x08 |
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| 140 | |
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| 141 | /* |
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| 142 | * Define values used to set the parity scheme in use. |
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| 143 | */ |
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| 144 | #define COR1_PARNONE 0x00 |
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| 145 | #define COR1_PARFORCE 0x20 |
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| 146 | #define COR1_PARENB 0x40 |
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| 147 | #define COR1_PARIGNORE 0x10 |
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| 148 | |
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| 149 | #define COR1_PARODD 0x80 |
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| 150 | #define COR1_PAREVEN 0x00 |
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| 151 | |
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| 152 | #define COR2_IXM 0x80 |
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| 153 | #define COR2_TXIBE 0x40 |
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| 154 | #define COR2_ETC 0x20 |
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| 155 | #define COR2_LLM 0x10 |
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| 156 | #define COR2_RLM 0x08 |
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| 157 | #define COR2_RTSAO 0x04 |
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| 158 | #define COR2_CTSAE 0x02 |
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| 159 | |
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| 160 | #define COR3_SCDRNG 0x80 |
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| 161 | #define COR3_SCD34 0x40 |
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| 162 | #define COR3_FCT 0x20 |
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| 163 | #define COR3_SCD12 0x10 |
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| 164 | |
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| 165 | /* |
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| 166 | * Define values used by COR4. |
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| 167 | */ |
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| 168 | #define COR4_BRKINT 0x08 |
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| 169 | #define COR4_IGNBRK 0x18 |
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| 170 | |
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| 171 | /*****************************************************************************/ |
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| 172 | |
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| 173 | /* |
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| 174 | * Define the modem control register values. |
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| 175 | * Note that the actual hardware is a little different to the conventional |
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| 176 | * pin names on the cd1400. |
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| 177 | */ |
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| 178 | #define MSVR1_DTR 0x01 |
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| 179 | #define MSVR1_DSR 0x10 |
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| 180 | #define MSVR1_RI 0x20 |
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| 181 | #define MSVR1_CTS 0x40 |
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| 182 | #define MSVR1_DCD 0x80 |
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| 183 | |
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| 184 | #define MSVR2_RTS 0x02 |
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| 185 | #define MSVR2_DSR 0x10 |
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| 186 | #define MSVR2_RI 0x20 |
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| 187 | #define MSVR2_CTS 0x40 |
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| 188 | #define MSVR2_DCD 0x80 |
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| 189 | |
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| 190 | #define MCOR1_DCD 0x80 |
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| 191 | #define MCOR1_CTS 0x40 |
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| 192 | #define MCOR1_RI 0x20 |
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| 193 | #define MCOR1_DSR 0x10 |
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| 194 | |
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| 195 | #define MCOR2_DCD 0x80 |
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| 196 | #define MCOR2_CTS 0x40 |
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| 197 | #define MCOR2_RI 0x20 |
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| 198 | #define MCOR2_DSR 0x10 |
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| 199 | |
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| 200 | /*****************************************************************************/ |
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| 201 | |
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| 202 | /* |
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| 203 | * Define the bits used with the service (interrupt) enable register. |
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| 204 | */ |
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| 205 | #define SRER_NNDT 0x01 |
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| 206 | #define SRER_TXEMPTY 0x02 |
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| 207 | #define SRER_TXDATA 0x04 |
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| 208 | #define SRER_RXDATA 0x10 |
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| 209 | #define SRER_MODEM 0x80 |
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| 210 | |
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| 211 | /*****************************************************************************/ |
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| 212 | |
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| 213 | /* |
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| 214 | * Define operational commands for the command register. |
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| 215 | */ |
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| 216 | #define CCR_RESET 0x80 |
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| 217 | #define CCR_CORCHANGE 0x4e |
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| 218 | #define CCR_SENDCH 0x20 |
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| 219 | #define CCR_CHANCTRL 0x10 |
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| 220 | |
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| 221 | #define CCR_TXENABLE (CCR_CHANCTRL | 0x08) |
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| 222 | #define CCR_TXDISABLE (CCR_CHANCTRL | 0x04) |
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| 223 | #define CCR_RXENABLE (CCR_CHANCTRL | 0x02) |
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| 224 | #define CCR_RXDISABLE (CCR_CHANCTRL | 0x01) |
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| 225 | |
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| 226 | #define CCR_SENDSCHR1 (CCR_SENDCH | 0x01) |
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| 227 | #define CCR_SENDSCHR2 (CCR_SENDCH | 0x02) |
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| 228 | #define CCR_SENDSCHR3 (CCR_SENDCH | 0x03) |
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| 229 | #define CCR_SENDSCHR4 (CCR_SENDCH | 0x04) |
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| 230 | |
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| 231 | #define CCR_RESETCHAN (CCR_RESET | 0x00) |
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| 232 | #define CCR_RESETFULL (CCR_RESET | 0x01) |
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| 233 | #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02) |
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| 234 | |
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| 235 | #define CCR_MAXWAIT 10000 |
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| 236 | |
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| 237 | /*****************************************************************************/ |
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| 238 | |
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| 239 | /* |
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| 240 | * Define the valid acknowledgement types (for hw ack cycle). |
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| 241 | */ |
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| 242 | #define ACK_TYPMASK 0x07 |
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| 243 | #define ACK_TYPTX 0x02 |
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| 244 | #define ACK_TYPMDM 0x01 |
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| 245 | #define ACK_TYPRXGOOD 0x03 |
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| 246 | #define ACK_TYPRXBAD 0x07 |
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| 247 | |
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| 248 | #define SVRR_RX 0x01 |
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| 249 | #define SVRR_TX 0x02 |
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| 250 | #define SVRR_MDM 0x04 |
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| 251 | |
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| 252 | #define ST_OVERRUN 0x01 |
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| 253 | #define ST_FRAMING 0x02 |
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| 254 | #define ST_PARITY 0x04 |
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| 255 | #define ST_BREAK 0x08 |
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| 256 | #define ST_SCHAR1 0x10 |
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| 257 | #define ST_SCHAR2 0x20 |
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| 258 | #define ST_SCHAR3 0x30 |
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| 259 | #define ST_SCHAR4 0x40 |
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| 260 | #define ST_RANGE 0x70 |
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| 261 | #define ST_SCHARMASK 0x70 |
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| 262 | #define ST_TIMEOUT 0x80 |
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| 263 | |
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| 264 | #define MISR_DCD 0x80 |
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| 265 | #define MISR_CTS 0x40 |
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| 266 | #define MISR_RI 0x20 |
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| 267 | #define MISR_DSR 0x10 |
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| 268 | |
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| 269 | /*****************************************************************************/ |
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| 270 | |
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| 271 | /* |
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| 272 | * Defines for the CCSR status register. |
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| 273 | */ |
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| 274 | #define CCSR_RXENABLED 0x80 |
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| 275 | #define CCSR_RXFLOWON 0x40 |
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| 276 | #define CCSR_RXFLOWOFF 0x20 |
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| 277 | #define CCSR_TXENABLED 0x08 |
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| 278 | #define CCSR_TXFLOWON 0x04 |
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| 279 | #define CCSR_TXFLOWOFF 0x02 |
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| 280 | |
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| 281 | /*****************************************************************************/ |
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| 282 | |
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| 283 | /* |
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| 284 | * Define the embedded commands. |
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| 285 | */ |
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| 286 | #define ETC_CMD 0x00 |
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| 287 | #define ETC_STARTBREAK 0x81 |
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| 288 | #define ETC_DELAY 0x82 |
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| 289 | #define ETC_STOPBREAK 0x83 |
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| 290 | |
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| 291 | /*****************************************************************************/ |
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| 292 | #endif |
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