| 1 | /* |
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| 2 | * cobalt-nvram.h : defines for the various fields in the cobalt NVRAM |
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| 3 | * |
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| 4 | * Copyright 2001,2002 Sun Microsystems, Inc. |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef COBALT_NVRAM_H |
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| 8 | #define COBALT_NVRAM_H |
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| 9 | |
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| 10 | #include <linux/nvram.h> |
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| 11 | |
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| 12 | #define COBT_CMOS_INFO_MAX 0x7f /* top address allowed */ |
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| 13 | #define COBT_CMOS_BIOS_DRIVE_INFO 0x12 /* drive info would go here */ |
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| 14 | |
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| 15 | #define COBT_CMOS_CKS_START NVRAM_OFFSET(0x0e) |
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| 16 | #define COBT_CMOS_CKS_END NVRAM_OFFSET(0x7f) |
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| 17 | |
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| 18 | /* flag bytes - 16 flags for now, leave room for more */ |
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| 19 | #define COBT_CMOS_FLAG_BYTE_0 NVRAM_OFFSET(0x10) |
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| 20 | #define COBT_CMOS_FLAG_BYTE_1 NVRAM_OFFSET(0x11) |
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| 21 | |
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| 22 | /* flags in flag bytes - up to 16 */ |
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| 23 | #define COBT_CMOS_FLAG_MIN 0x0001 |
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| 24 | #define COBT_CMOS_CONSOLE_FLAG 0x0001 /* console on/off */ |
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| 25 | #define COBT_CMOS_DEBUG_FLAG 0x0002 /* ROM debug messages */ |
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| 26 | #define COBT_CMOS_AUTO_PROMPT_FLAG 0x0004 /* boot to ROM prompt? */ |
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| 27 | #define COBT_CMOS_CLEAN_BOOT_FLAG 0x0008 /* set by a clean shutdown */ |
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| 28 | #define COBT_CMOS_HW_NOPROBE_FLAG 0x0010 /* go easy on the probing */ |
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| 29 | #define COBT_CMOS_SYSFAULT_FLAG 0x0020 /* system fault detected */ |
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| 30 | #define COBT_CMOS_OOPSPANIC_FLAG 0x0040 /* panic on oops */ |
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| 31 | #define COBT_CMOS_DELAY_CACHE_FLAG 0x0080 /* delay cache initialization */ |
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| 32 | #define COBT_CMOS_NOLOGO_FLAG 0x0100 /* hide "C" logo @ boot */ |
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| 33 | #define COBT_CMOS_VERSION_FLAG 0x0200 /* the version field is valid */ |
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| 34 | #define COBT_CMOS_FLAG_MAX 0x0200 |
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| 35 | |
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| 36 | /* leave byte 0x12 blank - Linux looks for drive info here */ |
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| 37 | |
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| 38 | /* CMOS structure version, valid if COBT_CMOS_VERSION_FLAG is true */ |
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| 39 | #define COBT_CMOS_VERSION NVRAM_OFFSET(0x13) |
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| 40 | #define COBT_CMOS_VER_BTOCODE 1 /* min. version needed for btocode */ |
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| 41 | |
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| 42 | /* index of default boot method */ |
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| 43 | #define COBT_CMOS_BOOT_METHOD NVRAM_OFFSET(0x20) |
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| 44 | #define COBT_CMOS_BOOT_METHOD_DISK 0 |
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| 45 | #define COBT_CMOS_BOOT_METHOD_ROM 1 |
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| 46 | #define COBT_CMOS_BOOT_METHOD_NET 2 |
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| 47 | |
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| 48 | #define COBT_CMOS_BOOT_DEV_MIN NVRAM_OFFSET(0x21) |
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| 49 | /* major #, minor # of first through fourth boot device */ |
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| 50 | #define COBT_CMOS_BOOT_DEV0_MAJ NVRAM_OFFSET(0x21) |
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| 51 | #define COBT_CMOS_BOOT_DEV0_MIN NVRAM_OFFSET(0x22) |
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| 52 | #define COBT_CMOS_BOOT_DEV1_MAJ NVRAM_OFFSET(0x23) |
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| 53 | #define COBT_CMOS_BOOT_DEV1_MIN NVRAM_OFFSET(0x24) |
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| 54 | #define COBT_CMOS_BOOT_DEV2_MAJ NVRAM_OFFSET(0x25) |
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| 55 | #define COBT_CMOS_BOOT_DEV2_MIN NVRAM_OFFSET(0x26) |
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| 56 | #define COBT_CMOS_BOOT_DEV3_MAJ NVRAM_OFFSET(0x27) |
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| 57 | #define COBT_CMOS_BOOT_DEV3_MIN NVRAM_OFFSET(0x28) |
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| 58 | #define COBT_CMOS_BOOT_DEV_MAX NVRAM_OFFSET(0x28) |
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| 59 | |
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| 60 | /* checksum of bytes 0xe-0x7f */ |
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| 61 | #define COBT_CMOS_CHECKSUM NVRAM_OFFSET(0x2e) |
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| 62 | |
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| 63 | /* running uptime counter, units of 5 minutes (32 bits =~ 41000 years) */ |
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| 64 | #define COBT_CMOS_UPTIME_0 NVRAM_OFFSET(0x30) |
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| 65 | #define COBT_CMOS_UPTIME_1 NVRAM_OFFSET(0x31) |
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| 66 | #define COBT_CMOS_UPTIME_2 NVRAM_OFFSET(0x32) |
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| 67 | #define COBT_CMOS_UPTIME_3 NVRAM_OFFSET(0x33) |
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| 68 | |
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| 69 | /* count of successful boots (32 bits) */ |
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| 70 | #define COBT_CMOS_BOOTCOUNT_0 NVRAM_OFFSET(0x38) |
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| 71 | #define COBT_CMOS_BOOTCOUNT_1 NVRAM_OFFSET(0x39) |
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| 72 | #define COBT_CMOS_BOOTCOUNT_2 NVRAM_OFFSET(0x3a) |
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| 73 | #define COBT_CMOS_BOOTCOUNT_3 NVRAM_OFFSET(0x3b) |
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| 74 | |
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| 75 | /* 13 bytes: system serial number, same as on the back of the system */ |
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| 76 | #define COBT_CMOS_SYS_SERNUM_LEN 13 |
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| 77 | #define COBT_CMOS_SYS_SERNUM_0 NVRAM_OFFSET(0x40) |
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| 78 | #define COBT_CMOS_SYS_SERNUM_1 NVRAM_OFFSET(0x41) |
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| 79 | #define COBT_CMOS_SYS_SERNUM_2 NVRAM_OFFSET(0x42) |
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| 80 | #define COBT_CMOS_SYS_SERNUM_3 NVRAM_OFFSET(0x43) |
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| 81 | #define COBT_CMOS_SYS_SERNUM_4 NVRAM_OFFSET(0x44) |
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| 82 | #define COBT_CMOS_SYS_SERNUM_5 NVRAM_OFFSET(0x45) |
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| 83 | #define COBT_CMOS_SYS_SERNUM_6 NVRAM_OFFSET(0x46) |
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| 84 | #define COBT_CMOS_SYS_SERNUM_7 NVRAM_OFFSET(0x47) |
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| 85 | #define COBT_CMOS_SYS_SERNUM_8 NVRAM_OFFSET(0x48) |
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| 86 | #define COBT_CMOS_SYS_SERNUM_9 NVRAM_OFFSET(0x49) |
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| 87 | #define COBT_CMOS_SYS_SERNUM_10 NVRAM_OFFSET(0x4a) |
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| 88 | #define COBT_CMOS_SYS_SERNUM_11 NVRAM_OFFSET(0x4b) |
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| 89 | #define COBT_CMOS_SYS_SERNUM_12 NVRAM_OFFSET(0x4c) |
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| 90 | /* checksum for serial num - 1 byte */ |
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| 91 | #define COBT_CMOS_SYS_SERNUM_CSUM NVRAM_OFFSET(0x4f) |
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| 92 | |
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| 93 | #define COBT_CMOS_ROM_REV_MAJ NVRAM_OFFSET(0x50) |
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| 94 | #define COBT_CMOS_ROM_REV_MIN NVRAM_OFFSET(0x51) |
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| 95 | #define COBT_CMOS_ROM_REV_REV NVRAM_OFFSET(0x52) |
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| 96 | |
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| 97 | #define COBT_CMOS_BTO_CODE_0 NVRAM_OFFSET(0x53) |
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| 98 | #define COBT_CMOS_BTO_CODE_1 NVRAM_OFFSET(0x54) |
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| 99 | #define COBT_CMOS_BTO_CODE_2 NVRAM_OFFSET(0x55) |
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| 100 | #define COBT_CMOS_BTO_CODE_3 NVRAM_OFFSET(0x56) |
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| 101 | |
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| 102 | #define COBT_CMOS_BTO_IP_CSUM NVRAM_OFFSET(0x57) |
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| 103 | #define COBT_CMOS_BTO_IP_0 NVRAM_OFFSET(0x58) |
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| 104 | #define COBT_CMOS_BTO_IP_1 NVRAM_OFFSET(0x59) |
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| 105 | #define COBT_CMOS_BTO_IP_2 NVRAM_OFFSET(0x5a) |
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| 106 | #define COBT_CMOS_BTO_IP_3 NVRAM_OFFSET(0x5b) |
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| 107 | |
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| 108 | #endif /* COBALT_NVRAM_H */ |
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