| 1 | |
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| 2 | #ifndef _SCC_H |
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| 3 | #define _SCC_H |
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| 4 | |
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| 5 | |
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| 6 | /* selection of hardware types */ |
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| 7 | |
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| 8 | #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */ |
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| 9 | #define EAGLE 0x01 /* hardware type for EAGLE card */ |
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| 10 | #define PC100 0x02 /* hardware type for PC100 card */ |
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| 11 | #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */ |
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| 12 | #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */ |
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| 13 | #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */ |
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| 14 | |
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| 15 | /* DEV ioctl() commands */ |
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| 16 | |
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| 17 | enum SCC_ioctl_cmds { |
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| 18 | SIOCSCCRESERVED = SIOCDEVPRIVATE, |
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| 19 | SIOCSCCCFG, |
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| 20 | SIOCSCCINI, |
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| 21 | SIOCSCCCHANINI, |
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| 22 | SIOCSCCSMEM, |
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| 23 | SIOCSCCGKISS, |
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| 24 | SIOCSCCSKISS, |
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| 25 | SIOCSCCGSTAT, |
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| 26 | SIOCSCCCAL |
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| 27 | }; |
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| 28 | |
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| 29 | /* Device parameter control (from WAMPES) */ |
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| 30 | |
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| 31 | enum L1_params { |
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| 32 | PARAM_DATA, |
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| 33 | PARAM_TXDELAY, |
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| 34 | PARAM_PERSIST, |
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| 35 | PARAM_SLOTTIME, |
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| 36 | PARAM_TXTAIL, |
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| 37 | PARAM_FULLDUP, |
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| 38 | PARAM_SOFTDCD, /* was: PARAM_HW */ |
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| 39 | PARAM_MUTE, /* ??? */ |
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| 40 | PARAM_DTR, |
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| 41 | PARAM_RTS, |
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| 42 | PARAM_SPEED, |
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| 43 | PARAM_ENDDELAY, /* ??? */ |
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| 44 | PARAM_GROUP, |
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| 45 | PARAM_IDLE, |
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| 46 | PARAM_MIN, |
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| 47 | PARAM_MAXKEY, |
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| 48 | PARAM_WAIT, |
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| 49 | PARAM_MAXDEFER, |
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| 50 | PARAM_TX, |
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| 51 | PARAM_HWEVENT = 31, |
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| 52 | PARAM_RETURN = 255 /* reset kiss mode */ |
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| 53 | }; |
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| 54 | |
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| 55 | /* fulldup parameter */ |
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| 56 | |
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| 57 | enum FULLDUP_modes { |
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| 58 | KISS_DUPLEX_HALF, /* normal CSMA operation */ |
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| 59 | KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */ |
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| 60 | KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */ |
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| 61 | KISS_DUPLEX_OPTIMA /* fullduplex, let the protocol layer control the hw */ |
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| 62 | }; |
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| 63 | |
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| 64 | /* misc. parameters */ |
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| 65 | |
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| 66 | #define TIMER_OFF 65535U /* to switch off timers */ |
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| 67 | #define NO_SUCH_PARAM 65534U /* param not implemented */ |
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| 68 | |
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| 69 | /* HWEVENT parameter */ |
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| 70 | |
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| 71 | enum HWEVENT_opts { |
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| 72 | HWEV_DCD_ON, |
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| 73 | HWEV_DCD_OFF, |
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| 74 | HWEV_ALL_SENT |
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| 75 | }; |
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| 76 | |
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| 77 | /* channel grouping */ |
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| 78 | |
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| 79 | #define RXGROUP 0100 /* if set, only tx when all channels clear */ |
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| 80 | #define TXGROUP 0200 /* if set, don't transmit simultaneously */ |
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| 81 | |
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| 82 | /* Tx/Rx clock sources */ |
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| 83 | |
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| 84 | enum CLOCK_sources { |
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| 85 | CLK_DPLL, /* normal halfduplex operation */ |
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| 86 | CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */ |
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| 87 | CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ |
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| 88 | /* modems without clock regeneration */ |
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| 89 | CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */ |
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| 90 | /* MODEMs without clock recovery */ |
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| 91 | }; |
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| 92 | |
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| 93 | /* Tx state */ |
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| 94 | |
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| 95 | enum TX_state { |
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| 96 | TXS_IDLE, /* Transmitter off, no data pending */ |
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| 97 | TXS_BUSY, /* waiting for permission to send / tailtime */ |
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| 98 | TXS_ACTIVE, /* Transmitter on, sending data */ |
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| 99 | TXS_NEWFRAME, /* reset CRC and send (next) frame */ |
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| 100 | TXS_IDLE2, /* Transmitter on, no data pending */ |
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| 101 | TXS_WAIT, /* Waiting for Mintime to expire */ |
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| 102 | TXS_TIMEOUT /* We had a transmission timeout */ |
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| 103 | }; |
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| 104 | |
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| 105 | typedef unsigned long io_port; /* type definition for an 'io port address' */ |
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| 106 | |
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| 107 | /* SCC statistical information */ |
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| 108 | |
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| 109 | struct scc_stat { |
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| 110 | long rxints; /* Receiver interrupts */ |
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| 111 | long txints; /* Transmitter interrupts */ |
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| 112 | long exints; /* External/status interrupts */ |
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| 113 | long spints; /* Special receiver interrupts */ |
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| 114 | |
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| 115 | long txframes; /* Packets sent */ |
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| 116 | long rxframes; /* Number of Frames Actually Received */ |
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| 117 | long rxerrs; /* CRC Errors */ |
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| 118 | long txerrs; /* KISS errors */ |
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| 119 | |
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| 120 | unsigned int nospace; /* "Out of buffers" */ |
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| 121 | unsigned int rx_over; /* Receiver Overruns */ |
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| 122 | unsigned int tx_under; /* Transmitter Underruns */ |
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| 123 | |
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| 124 | unsigned int tx_state; /* Transmitter state */ |
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| 125 | int tx_queued; /* tx frames enqueued */ |
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| 126 | |
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| 127 | unsigned int maxqueue; /* allocated tx_buffers */ |
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| 128 | unsigned int bufsize; /* used buffersize */ |
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| 129 | }; |
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| 130 | |
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| 131 | struct scc_modem { |
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| 132 | long speed; /* Line speed, bps */ |
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| 133 | char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */ |
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| 134 | char nrz; /* NRZ instead of NRZI */ |
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| 135 | }; |
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| 136 | |
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| 137 | struct scc_kiss_cmd { |
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| 138 | int command; /* one of the KISS-Commands defined above */ |
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| 139 | unsigned param; /* KISS-Param */ |
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| 140 | }; |
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| 141 | |
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| 142 | struct scc_hw_config { |
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| 143 | io_port data_a; /* data port channel A */ |
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| 144 | io_port ctrl_a; /* control port channel A */ |
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| 145 | io_port data_b; /* data port channel B */ |
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| 146 | io_port ctrl_b; /* control port channel B */ |
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| 147 | io_port vector_latch; /* INTACK-Latch (#) */ |
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| 148 | io_port special; /* special function port */ |
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| 149 | |
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| 150 | int irq; /* irq */ |
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| 151 | long clock; /* clock */ |
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| 152 | char option; /* command for function port */ |
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| 153 | |
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| 154 | char brand; /* hardware type */ |
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| 155 | char escc; /* use ext. features of a 8580/85180/85280 */ |
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| 156 | }; |
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| 157 | |
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| 158 | /* (#) only one INTACK latch allowed. */ |
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| 159 | |
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| 160 | |
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| 161 | struct scc_mem_config { |
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| 162 | unsigned int dummy; |
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| 163 | unsigned int bufsize; |
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| 164 | }; |
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| 165 | |
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| 166 | struct scc_calibrate { |
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| 167 | unsigned int time; |
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| 168 | unsigned char pattern; |
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| 169 | }; |
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| 170 | |
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| 171 | #endif /* defined(_SCC_H) */ |
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